JPH0219087A - Time axis error correction device - Google Patents

Abstract

PURPOSE:To attain time axis correction without changing the format of a home use VTR by extracting a luminance signal subject to FM demodulation from a reproducing video signal, writing the signal into a prescribed memory in the timing at the back edge side of a synchronizing signal and reading a reproducing luminance signal recorded into a memory by a constant clock without time axis fluctuation component. CONSTITUTION:The FM luminance signal is separated from the reproducing video signal by a bypass filter 15, demodulated by an FM demodulator 16, clamped by a clamp circuit 17 and inputted to an A/D converter 18. Moreover, the center potential of the back edge of the synchronizing signal of the clamped reproducing luminance signal is detected by a center potential detector 24 and the signal is subject to synchronizing separation by a slice circuit 25 depending on the potential. The synchronizing signal causes a write reset pulse to be generated and a reproduced luminance signal is written in a timing memory 19 for a write reset pulse. Thus, the stable time axis correction is attained without changing the format of a home use VTR.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a time axis error correction device for correcting time axis fluctuations of a reproduced video signal accompanied by time axis fluctuations of a video tape recorder or the like.

2. Description of the Related Art In recording and reproducing apparatuses such as video tape recorders (VTRs), relative speed fluctuations between a signal detector and a recording medium cause time axis fluctuations in reproduced video signals. A time-base error correction device (TBC) is used as a means to correct the reproduced video signal with such time-base fluctuations.Since the time-base error correction device is a technology required for professional VTRs, etc., there are many However, it has not yet been introduced into home VTRs.Therefore, as a conventional time axis error correction device, the
ional Technical Report Vo.
l, 31No, 6Dec, 19ss r Mll
The time axis error correction device for a commercial VTR described in detail in 71-7 (VTRAU-600J) will be described.

FIG. 4 shows a block diagram of this time axis error correction device. In the figure, a luminance signal separated from a reproduced video signal and subjected to FM demodulation is input to an input terminal 1, and a synchronization signal is separated by a synchronization signal separation circuit (H, S, S) 6. The separated synchronization signal is processed by an automatic frequency control circuit (
AFC) e, which outputs a master clock synchronized with the synchronization signal.

The output master clock is automatically controlled by the automatic control circuit (PC).
7 and is phase-compared with a TBC burst signal separated from the input luminance signal by a burst separation circuit 8, phase-modulated according to the phase difference, and output as a write clock. The input luminance signal containing the time axis fluctuation component is sampled by the shim/D converter 2 using a write clock that is phase-synchronized with the phase-modulated input luminance signal and written to the memory 3, and the time obtained from the reference oscillator 1o is It is read out from the memory 3 using a constant readout clock that does not involve axis fluctuation components. The luminance signal read from the memory 3 is converted back to an analog signal by the D/A converter 4, and then a reference sync signal without time axis fluctuation components formed by the reference clock from the reference oscillator 1o is added. 11 and output to an output terminal 12. Furthermore, during high-speed playback and high-speed reverse playback, switching the write clock to the clock from the voltage controlled oscillator (VC; The structure is designed to respond to instantaneous changes.

Problems to be Solved by the Invention However, the above-mentioned time axis error correction device has been introduced into commercial VTRs, and if this method is directly introduced into home VTRs, the following problems will arise. .

- In the case of home VTRs, 3/N and waveform reproduction of reproduced signals are poorer than that of commercial VTRs, so malfunctions tend to occur in synchronization signal detection, and sufficient performance cannot be expected.

■ A burst signal for KTBC is added to the luminance signal during recording, and it is used to perform time axis correction.In order to implement this, the format of current home VTRs must be changed. This will cause compatibility problems.

In view of this point, the present invention provides an S
/N and waveform reproduction, and also works well with household V.
It is an object of the present invention to provide a time axis error correction device that can perform time axis correction without changing the TR format.

Means for Solving the Problems The time axis error correction device of the present invention corrects FM signals from reproduced video signals.
A means for increasing the demodulated luminance signal, detecting the sync tip potential and back porch potential of the luminance signal, and slicing the sync back porch at the center potential to separate the synchronization signal, and a reference clock from a reference oscillator. write clock generating means for sequentially shifting the phase of the synchronizing signal and selecting and outputting the clock closest to the phase of the synchronizing signal backup obtained by the synchronizing signal separating means from among the phase-shifted clocks; is written to a predetermined memory at the back side timing of the synchronization signal using the selected write clock, and the playback luminance recorded in the memory at the timing of the reference synchronization signal synchronized with the reference clock using a constant clock with no time axis fluctuation component. The configuration includes at least means for reading out signals.

Operation The present invention has the above configuration, and even if the DC potential or input level of the reproduced luminance signal fluctuates in the synchronization signal separation means, the sync signal is not affected by noise due to a relatively sudden rise. The synchronization signal can always be separated at a part of the center of the backwedge, and by using this separated synchronization signal to select the write clock in the write clock generation means, the phase can be instantaneously synchronized with the sink of the reproduced luminance signal without malfunction. It is possible to create a write clock. Using this write clock, the reproduced luminance signal is written to the memory at the reset timing of the backgage side of the separated synchronization signal, and is read from the memory at the reset timing of the reference synchronization signal using a constant reference clock with no time axis fluctuation, thereby stably correcting the time axis. It was designed to do so.

Embodiment Regarding an embodiment of the time axis error correction device of the present invention, the first
This will be explained with reference to the figures. FIG. 1 is a block diagram showing the configuration of the time axis error correction device of this embodiment.

In the figure, a reproduced video signal obtained from a reproduction host 13 is amplified by a head amplifier 14, and then an FM luminance signal is separated by a bypass filter (HPF) 1ts. The separated FM# signal component is sent to an FM demodulator (FM-DIM).
) 16, clamped by a clamp circuit 17, and then input to a MU/D converter 18. In addition, the clamped reproduced luminance signal is processed by a sync tip potential detector 22 that detects the sync tip level, a back porch potential detector 23 that detects the so-called vedestal level w, and the sync tip potential and back porch potential are added and divided into two. The center potential of the sink backgage is detected by the center potential detector 24 which detects the center potential, and the potential is synchronously separated by the slicing circuit 25. The synchronization signal obtained from this slice circuit 25 is transferred to the phase shifter 2.
79 Phase Detector 26. A write clock is generated by inputting it to a write clock generator 57 consisting of a clock selector 28.

The separated synchronization signal is also input to the write reset 29 to generate a write reset pulse. The reproduced luminance signal inputted to the gam/D converter 18 is sampled and converted into a digital signal, and then written to the memory 19 at the timing of a write reset pulse from a write reset 29 using a write clock. memory 1
The reproduced luminance signal written in 9 is read by dividing the reference clock from the reference oscillator 32 by the divider 31 and reading from the output signal using the reference clock at the timing of the readout series reset pass ρ generated by the readout reset 3o. The signal is output, converted into an analog signal by the D/MU converter 20, and outputted to the output terminal 21.

Further, the reference clock from the reference oscillator 32 is transmitted to the frequency divider 3
The signal is frequency-divided by 3 and input to the drum servo 34, and is also used as a reference control signal for the drum motor 36.

Next, the specific operation of this embodiment will be explained in more detail. The reproduced luminance signal demodulated by the 7M demodulator 1e and clamped by the clamp circuit 17 is sent to the sync tip potential detector 22. Back porch potential detector 23. A center potential detector 24 detects the center potential of the sync backgage, and a slice circuit 25 slices the signal using the center potential to separate synchronization signals.

Here, the sync portion of the reproduced luminance signal will be briefly explained.

Generally, the front edge of a sync is only about 1 to 2 μsec away from the video signal portion before the sync, and is therefore easily influenced by the video signal portion and easily distorted. Also, on the back side of the sync, the band of the low-pass filter after FM demodulation is limited, so the slope of the rise of the sync is more abrupt near the center of the sync than near the sync tip and back porch. Therefore, when sync is sliced near the sync center, it is least affected by noise.

Therefore, it can be considered that the vicinity of the center on the back side of the sync has the smallest phase error as a synchronization signal. The synchronization signal obtained by the slice circuit 26 is input to the phase detector 26 of the write clock generator 57. The writing clock to the memory 19 is a reference clock outputted from the reference oscillator 32, which is converted to 2π by the phase shift circuit 27.
The phase is shifted to n signals with different phases by /n, and inputted to the phase detector 26 and clock selector 28, and the phase detector 26 selects the signal whose phase is closest to the backward side of the previous synchronization signal. It is obtained by detecting the signal, selecting a clock from the detection signal in the clock selector 28, and outputting the selected clock. The reproduced luminance signal is sampled by the shim/D converter 18 using this write clock, and the write reset 2 is phase-synchronized with the back side of the previous synchronization signal.
The data is written into the memory 19 at the timing of the write reset pulse from 9, and the previous read reset 3
The data is read out at the timing of the read reset pulse from o, and the time axis is corrected and output. Since writing and reading to and from the memory 19 are asynchronous, the average frequency difference between the synchronization signal from the slice circuit 25 and the reference synchronization signal obtained by dividing the reference clock causes the memory 19
may cause an overflow condition. Therefore, in order to synchronize the average frequency of the synchronization signal from the slice circuit 26 and the reference synchronization signal, the reference signal of the drum servo 34 that controls the drum motor 36 is used as the reference clock from the reference oscillator 32 that generates the read clock. The configuration is such that it is obtained from a signal frequency-divided by a frequency divider 33. By doing so, time axis correction can be performed without overflowing the memory 19.

With the configuration and operation described above, the home VT
Even for reproduced signals with poor S/N and waveform reproduction, the synchronization signal is reliably separated at the center of the sync backgage, and a clock that is phase-synchronized with the synchronization signal is instantly selected to maintain stable time. Axis error correction can be performed and the home VTR can be configured without changing its format.

Next, a second embodiment of the time axis error correction device of the present invention will be described with reference to FIG. In the same figure, the first
Circuits that are the same as those in the figures are given the same numbers, and therefore their explanations will be omitted.

In FIG. 2, when the S/N of the input reproduction signal is poor, the synchronization signal separated by the slice circuit 26 contains many phase errors caused by noise as electrical jitter components. In order to reduce electrical jitter from this synchronization signal, this synchronization signal is passed through a phase comparator 36. low pass phi μ
ri68. The variable oscillator 379 is input to a so-called FC loop consisting of a branching unit 3B. This five FC1v-p connects a variable oscillator 37 to a synchronizing signal separated from the slice circuit 26.
The variable oscillator 37 is feedback-controlled so as to be phase-synchronized with the signal obtained by frequency-dividing the clock from the variable oscillator 38, and the synchronization signal generated by dividing the controlled signal from the variable oscillator 37 is The clock is configured to be sent to the write clock generating means.

Since the synchronization signal output from the FC/L/- loop is feedback-controlled, it can be regarded as the synchronization signal from the slice circuit 26 averaged by the low-pass filter 58. Therefore, it does not respond to high frequency components such as electrical jitter caused by noise, but can sufficiently respond to and detect mechanical jitter of low frequency components. However, although it tends to become unresponsive to high-frequency time axis fluctuations such as skew and head tapping, the effect of improving minute fluctuation noise due to electrical jitter components on the screen is considerably greater. Therefore, with the above configuration and operation, even in a reproduced signal with a poor S/N ratio, electrical jitter due to noise can be generated by averaging the synchronization signal separated at the center potential of the sync backgage using a so-called five FC loop. In addition to being able to perform time axis correction without changing the format of the home VTR, it is possible to configure the home VTR without changing its format.

Next, a third embodiment of the time axis error correction device of the present invention will be described with reference to FIG. In the same figure, the first
Circuits that are the same as those in the figures are given the same numbers, and therefore their explanations will be omitted. In FIG. 3, the low-pass converted color signal output from the head amplifier 14 and separated by the low-pass filter 39 is composed of a frequency converter 1i (HET) 4o, a burst gate 42° phase control circuit (MPC) 4s. The signal is converted to the original subcarrier frequency by an automatic phase control loop (ApcIv-P), and becomes a carrier color signal.

This carrier color signal is phase-compared with the reference subcarrier obtained by dividing the reference clock output from the reference oscillator 32 by the frequency divider 63, so that the carrier wave phase fluctuation component due to time axis fluctuation is eliminated. sufficiently removed. The carrier color signal outputted from the comb filter 41 is passed through the comb filter 41 and adjacent crosstalk noise is sufficiently removed.
The reference subcarrier obtained from the subcarrier is decoded by the orthogonal two-phase carrier obtained by passing it through the phase shifter 64, thereby obtaining two baseband color signals.

These two color signals are baseband signals.

It has a time axis fluctuation component similar to the luminance signal.

Therefore, like the luminance signal, these two color signals are input to the MU/D converters 46 and 48 respectively, written to the memories 46 and 49 by the write clock, read out by the reference clock, and then sent to the encoder circuit 61. is input. The two color signals inputted to the encoder circuit 51 are encoded by a reference carrier wave obtained by frequency-dividing the reference tally clock by a divider 62, and output as a time-base corrected carrier wave color signal. The time-axis corrected carrier color signal is added to the luminance signal similarly time-axis corrected by an adder 55 and outputted to an output terminal 56.

With the above-described configuration and operation, it is possible to realize a circuit that can perform time axis correction on color signals as well as luminance signals.

Effects of the Invention As described above, the time axis error correction device of the present invention can reliably generate a synchronization signal at a part of the center of the sync backgage, even in playback signals with poor S/N and waveform reproduction, such as those from home VTRs. Stable time axis correction can be performed by separating and instantly selecting a clock whose phase is synchronized with the synchronizing signal, and moreover, it can be realized with a simple configuration without changing the format of a home VTR.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a time axis error correction device according to an embodiment of the present invention, and FIG. 2 is a schematic diagram of a second embodiment of the present invention.
FIG. 3 is a block diagram of a third embodiment of the present invention, and FIG. 4 is a block diagram of a conventional time axis error correction device. 13...Playback head, 14...Head amplifier. 16... Bypass filter, 16...
yMat adjuster, 17... Clamp circuit, 1B.
- Mark/Mu/D converter. 19...Memory, 2o...D/MU converter, 21...Output terminal, 22...Sync chip potential detector, 23... ...Back porch potential detector, 24... Sink center potential detector, 25... Slice circuit, 26... Phase detector TFI device, 27... Phase shifter, 28.
... Clock selection circuit, 29 ... mark - write reset pulse generator, 3o ... read reset pulse generator, 31.33 ... mountain frequency divider, 32 ...
...Reference oscillator, 34...Drum servo,
35. River... Drum motor.

Claims (2)

[Claims] (1) A synchronizing signal separating means for separating a synchronizing signal from an FM demodulated reproduced luminance signal, a write clock generating means for generating a clock phase-synchronized with the synchronizing signal obtained from the synchronizing signal separating means, and the reproduced luminance signal. means for writing into the memory at the timing of the back edge side of the synchronization signal using the write clock from the write clock generation means, and a reference synchronization obtained by dividing a constant reference clock with no time axis fluctuation component from the reference oscillator. and means for reading out the reproduced luminance signal recorded in the memory at the timing of the signal, and the synchronizing signal separating means includes:
A sync tip potential and a back porch potential of the reproduced luminance signal are detected, and a synchronization signal is detected by slicing the back edge of the sync at the center potential, and the write clock generating means generates a reference clock from the reference oscillator. A time-base error correction device characterized in that the clock closest to the phase of the back edge of the synchronization signal is selected and outputted from among a plurality of clocks generated by sequentially shifting the phase. (2) The synchronization signal separation means detects the sync tip potential and back porch potential of the reproduced luminance signal, and separates the sync signal by slicing the back edge of the sync at the center potential and the signal from the variable frequency oscillator. A variable frequency oscillator is feedback-controlled so as to phase synchronize the frequency-divided and generated synchronization signal, and the frequency-divided and generated synchronization signal is sent to the write clock generation means. The time axis error correction device according to claim 1.