JPS62188483A - Error of time axis correcting device - Google Patents

Abstract

PURPOSE:To attain highly accurate and stable time axis error correction by forming a means for shifting the phase of a phase synchronizing signal in accordance with a speed error correcting signal and obtaining a phase correcting clock signal and a means for A/D converting a reproduced video signal on the basis of the phase correcting clock signal. CONSTITUTION:The 2nd phase shifter 8 selects a clock signal from a phase synchronizing clock signal and a delay clock signal delayed in each 1/8 clock in accordance with a speed error correcting signal to obtain a phase correcting clock signal. An A/D converter 3 A/D converts a reproduced video signal on the basis of the phase correcting clock signal to control writing in a memory device 10. Reading from the memory device 10 and the operation of a D/A converter 11 are controlled by a reference clock signal and a reproduced video signal removed at its time axis error component is outputted to an output terminal 12. The reproduced video signal is A/D converted and the digital signal is written in the memory device and read out by the reference clock signal to execute D/A conversion. Consequently, time axis variation can be removed with rapid follow-up and highly accuracy and stability.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to high-speed and
This relates to a time axis error correction device that obtains a high-performance tracking clock signal, removes time axis fluctuations in a reproduced video signal, and obtains a high quality video signal. In order to remove the axis error component, the reproduced video signal is converted into iA/D using a clock signal that is phase-synchronized with the time axis error of the reproduced video signal obtained from the VCO, AFe circuit, etc., and written to the storage device.
An analog error voltage of the VCO, FC circuit, etc. is used as a speed error voltage, and a modulated clock signal obtained by analog phase modulating the reference clock signal according to this speed error voltage is read out from the storage device. A time axis error correction device that performs D/A conversion has been proposed.

Problems to be Solved by the Invention However, in the above configuration, the speed error is detected as a voltage level or pulse width using an all-analog phase comparator, and this speed error is converted into a modulation voltage of an analog phase modulator to generate a clock signal. Since the speed is phase modulated, there is a problem that accurate and stable speed error detection and phase modulation cannot be performed due to the influence of capacitor leakage, component variations, temperature characteristics, noise, etc. Further, in order to perform the detection and modulation with high precision, complicated adjustments are required, which poses a major problem in mass production.

Furthermore, since the speed error voltage is detected as an analog quantity,
In order to perform storage or complicated conversion processing, analog signal processing has problems with accuracy and stability, and digital signal processing requires a digital converter such as an A/D converter.

In view of the above, the present invention provides a time-base error correction device that performs highly accurate and highly stable time-base error correction and does not require adjustment by performing the correction using digital signal processing.

Means for Solving the Problems The present invention provides a reference clock signal and its 17N clock (N
=2 1=1.2. ...) The speed error is expressed as the difference in binary code between the detection time length of one horizontal scanning period of the reproduced video signal detected using the delayed clock signal delayed by 100 seconds and the one horizontal scanning reference time length obtained by counting the reference clock signal. Obtain it as a signal and write it into a storage device, predict the speed error in the next horizontal scanning period by polynomial approximation from the speed error signal at the current time and the speed error signal in the previous horizontal scanning period, and obtain a speed error correction signal. The reference clock signal is one of the reproduced video signals.
The phase synchronized clock signal is phase-shifted and phase-synchronized to a reference position for each horizontal scan, and the reproduced video signal is converted into iA/D using a phase-corrected clock signal whose phase is shifted according to the speed error correction signal, and the storage device This is a time axis error correction device that writes data to H, reads it from the storage device (2) using a predetermined stable clock signal, performs D/M conversion, and removes time axis fluctuations of the reproduced video signal.

Operation The present invention has the above-described configuration to convert the reproduced video signal into A/
By synchronizing the phase of the reference clock signal of the clock signal to be D-converted with the reference position for each horizontal scan of the reproduced video signal, the low frequency component of the time axis fluctuation is removed, and the speed error of the reproduced video signal is reduced. Digitally detects the reference clock signal with an accuracy of 17 N clocks, predicts the speed error in the next horizontal scanning period, and corrects the speed error, thereby removing high frequency components of time axis fluctuations and achieving high accuracy. Time axis errors can be removed with high stability.

Examples Examples of the present invention will be described below. Figure 1 is a block diagram of the time axis error correction device of this embodiment, and Figure 2 is a block diagram of the time axis error correction device of this embodiment.
FIG. 3 is a waveform diagram of the time axis error of the reproduced video signal, and FIG. 4 is a waveform diagram of the phase shifter 5 of the phase shifter 5, and FIG. 4 is a waveform diagram of the time axis error of the reproduced video signal.FIG. 6 is a block diagram of the speed error correction signal generator 7 and the second phase shifter 8, and FIG. 6 is a waveform diagram explaining the operation of FIG. 5.

In this embodiment, a reference clock signal and a delayed clock signal of 1A clock each are used, and the speed error correction is performed by 3
An example of approximating a second order term will be explained.

The reproduced video signal is input from an input terminal 1 to an A/D converter 3 and a burst signal detector 4. The detected burst signal output from the burst signal detector 4 is input to the first phase shifter 6, and, for example, the rising edge of the first wave is detected. In the first phase shifter 6, delayed clock signals C1D, I!, which are delayed by the reference clock signal B and IA clock from the first burst signal M! :, F, G, H, and I, and select the closest clock signal f I H (H: horizontal scanning period) to output a phase synchronized clock signal Ji.

The reference clock signal B is generated by the reference clock signal generator 9 in phase synchronization with the reference H input from the input terminal 2. The speed error detector 6 detected the 1H time length of the detection burst signal using the reference clock signal and seven delayed clock signals delayed by one clock, and counted the reference signal. The difference from the 1H time length is output as a speed error signal Δvi. △ in Figure 3
v1 is this speed error signal, which is given, for example, as a 6-bit binary code. In this case, the speed error range is ±4 clocks, the sign bit is 1 bit from the higher order among the 6 bits, the speed error per clock is 2 bits, and the speed error within the clock is 3 bits.

In the speed error correction signal generator 7, the speed error signal ΔV
ii Write it into the storage device at any time, and predict the next speed error ΔV'n-z by approximating the cubic term equation from the current time ΔVn and n previous times Δvn-11Δvn-2, and generate the speed error correction signal Y.
n+, (t) ffi outputs 0. FIG. 4 is a waveform diagram explaining the operation.

The speed error correction signal y(t) is approximated by the following equation.

Y(t)=at+bt2+ct3 Here, the horizontal scanning period at the current time=zn, and YH++ (
t) is the speed error correction signal within the next horizontal scanning period, and t
= 19'('rcx: count number in IH.

HCK IHCK: IH count number 0≦t≦1), then Yn+t(t)=atubt2+Ct'=f
(a+2bt+3ct2)at =JXn+1(t)d
tYn++ (0) = O+ Yn+1(1) = ΔV
'n+1! n+1(t): Speed error differential signal, Δy6+
, :Given by the predicted speed error signal.〇The second phase shifter 8 receives this speed error correction signal Yn+
1 ("According to step 3, a clock signal is selected from the phase-synchronized clock signal and a delayed clock signal of each IA clock to obtain a phase-corrected clock signal.0 This phase-corrected clock signal is used in the Elim/D converter 3 to Playback video signal i A
/D conversion and controls writing to the storage device 1°. The reading of the storage device 1o and the D/MU converter 11 are controlled by the reference clock signal, and a reproduced video signal from which the time axis error component has been removed is outputted to the output terminal 12.

The speed error correction described above will be briefly explained with reference to FIGS.

A reproduced H signal of a reproduced video signal is input to the input terminal 13, a speed error signal Δv1 is input to the input terminal 14, and a phase synchronized clock signal is input to the input terminal 15. The storage device 16 is a 6-bit shift register and sequentially shifts the speed error signal to Δvn with respect to the current time n.

ΔV, . . . Δvn-2 are output to the arithmetic unit 17. The calculator 17 calculates the coefficient abc based on the cubic term approximation, and calculates the speed error differential signal xn+1(t
) e Output. This xn++ (t) (Figure 6L) is the pulse at a predetermined position of 1H and its sign bit signal,
For example, when Δv′n+1=oo0101, 1H
The number of pulses to be phase corrected, that is, six pulses, is generated within the period. After the up/down counter 18 is cleared by the reproduced H signal, the speed difference differential signal Xn+1(t
) t clock and up/dou with the sign bit signal
n is controlled and counted, and a speed error correction signal Yn++(
t) (Fig. 6 M, N, O) i Output.

This count up or down is the Yyl+t(t
) =fxn++(t)df. The selector 20 generates a clock signal 1cK1 from the phase synchronized clock signal (CL) and the delayed clock signal (CX2 to CK8) according to the speed error correction signal Yn+1(i).
, CK2° . . . and outputted to the output terminal 29 as a phase correction clock signal. The D-FF 19 controls the clock switching timing based on the phase corrected clock signal delayed by the delay device 21.

As described above, according to this embodiment, a phase-synchronized clock signal is obtained by synchronizing the phase of the reference clock signal with the burst signal of the reproduced video signal, and the speed error of the reproduced video signal is calculated using the reference clock signal of the column clock. The speed error correction signal is obtained by directly detecting the speed error signal with accuracy, predicting the speed error within the next horizontal scanning period by cubic term approximation from this speed error signal, and sequentially shifting the phase of the phase synchronized clock signal. The reproduced video signal is subjected to 7M/D conversion using the obtained phase correction clock signal and written to a storage device, and is read out using the reference clock signal and subjected to D/M conversion, thereby achieving high-speed tracking, highly accurate and highly stable time axis fluctuation removal. can be done. In addition, since the phase synchronized clock signal and correction clock signal can be obtained through complete digital signal processing, there is no need for a vCO or analog phase modulator, and there is no need for circuit adjustment. There is also little deterioration in characteristics.

Furthermore, since the reproduced video signal read from the storage device has time axis fluctuations completely removed, it is very convenient for subsequent signal processing.

In this embodiment, a reference clock signal and a delayed clock signal corresponding to each column clock are used to generate a phase synchronized clock signal, detect a speed error, and generate a phase correction clock signal. A similar effect can be obtained by performing the above processing using only the multiplied clock signal and the delayed clock signal of its dedicated clock. In this case, many delay devices are not required, and delay variations and clock There is also little deterioration in accuracy due to changes in duty.

As described in detail, according to the present invention, the time axis error of the reproduced video signal is reduced to 1/N clocks of the reference clock signal.

It is possible to obtain a clock signal that is phase-synchronized with not only the low frequency component but also the high frequency component of this time axis error, so the time axis error component of the reproduced video signal is stabilized with high precision. can be removed. Also,
Since the entire system is digital signal processing, there is no need for circuit adjustments.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a time axis error correction device according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of the first phase shifter of the embodiment, and FIG. 3 is a diagram of the reproduced video signal of the embodiment. A waveform diagram of the time axis error, FIG. 4 is a waveform diagram for obtaining the speed error correction signal of the same embodiment, and FIG. 6 is a block diagram of the speed error correction signal generator and the second phase shifter of the same embodiment, FIG. 6 is a waveform diagram illustrating the operation of FIG. 6. 3... A/D converter, 4. Old... burst signal detector,
6...First phase shifter, 6°°°...° speed error detector, 7... Speed error correction signal detector, 8... Second phase shifter, 9... Reference clock signal generator , 10...
Storage device, 11...D/A converter. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 2 cause JLI LI LI Ll-Yuhaari Tsumagi Figure 3 Hn-2Hn-+ Hn HntTHntt Hn+s
Figure 4

Claims (4)

[Claims] (1) The speed is calculated from the difference between the detected time length of one horizontal scanning period of the reproduced video signal containing the time axis error component and the reference time length of one horizontal scanning period obtained by counting a predetermined number of reference clock signals. means for obtaining an error signal; means for storing the speed error signal in a storage device; means for predicting a speed error signal within a period to obtain a speed error correction signal; and means for shifting and synchronizing the phase of the reference clock signal to a reference position for each horizontal scan of the reproduced video signal to obtain a phase synchronized clock signal. means for phase-shifting the phase-synchronized clock signal according to the speed error correction signal to obtain a phase-corrected clock signal; and means for A/D converting the reproduced video signal using the phase-corrected clock signal. A time axis error correction device characterized in that it has at least. (2) Reference clock signal and 1/2 of this reference clock signal
The method is characterized in that the time length of one horizontal scanning period of the reproduced video signal is detected using N-1 delayed clock signals delayed by N clocks (N=2^nn=1, 2,...). A time axis error correction device according to claim 1. (3) L times the reference clock signal (L=2^l, l=1,
2...) and M-1 delayed multiplied clock signals that are delayed by 1/M clocks (M=2^mm=1, 2...) of this multiplied clock signal. 2. The time axis error correction device according to claim 1, wherein the time length of one horizontal scanning period of the signal is detected. (4) A speed error correction signal within the next horizontal scanning period is obtained by polynomial approximation from the current time of the speed error signal and the speed error signals of several horizontal scanning periods before that. The time axis error correction device according to item 1 or 3.