JP3123612B2 - Time axis correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001] The present invention relates to a time axis correction apparatus for generating a clock of a predetermined frequency that tracks jitter contained in an input video signal in a video signal recording / reproducing apparatus or the like.

[0002]

2. Description of the Related Art Conventionally, a digital TBC (Time Base) has been used as a device for removing jitter (Jitter: uncoordinated fluctuation) included in an input video signal as described above.
A time axis correction device called a se collector (time base collector) is known.

[0003] For example, a clock following a jitter contained in an input video signal is generated by a clock generation circuit, and the input video signal is sampled with the clock to be converted into a digital signal. The data is read out from the memory at a stable and constant clock in consideration of the jitter during one horizontal synchronization period and is converted into an analog signal, thereby obtaining an input video signal containing no jitter.

Here, a circuit configuration of a conventional digital TBC is shown in FIG.

[0005] As shown in FIG. 3, a video signal containing jitter inputted from the input terminal 1 includes a horizontal synchronizing signal and a burst signal. When a video signal containing jitter is input from the input terminal 1, the horizontal synchronizing signal and the burst signal included in the video signal are separated by a synchronizing signal separating circuit 2, and the horizontal synchronizing signal is separated into a phase synchronizing circuit ( PL
L: Phase lock loop) 3 and the burst signal is input to the phase comparison circuit 4.

A phase synchronization circuit (PLL circuit) 3 generates a clock having the same frequency as the burst signal phase-locked to the horizontal synchronization signal separated by the synchronization signal separation circuit 2. The phase comparison circuit 4 detects a velocity error by comparing the phase of the output of the phase synchronization circuit 3 with the burst signal from the synchronization signal separation circuit 2.

[0007] The output of the phase comparison circuit 4 is input to a first level conversion circuit 5 and after its output level is adjusted,
It is input to the first phase shift circuit 6. The first phase shift circuit 6 operates in accordance with the phase difference signal supplied from the phase comparison circuit 4 via the first level conversion circuit 5 to control the phase synchronization circuit 3
Is phase shifted. As a result, a clock having the same phase and the same frequency as the burst signal is obtained.

[0008] The output of the first phase shift circuit 6 is input to a first frequency multiplying circuit 7 and converted into a signal of N times frequency.

As a result, the first A / D conversion circuit 8 samples the video signal input from the input terminal 1 and writes the data to the first memory circuit 9. Here, the state of jitter removal will be described with reference to FIG. In FIG. 4 (a), the curve (a)
Indicates the jitter of the video signal input from the input terminal 1 in FIG.

The jitter of the video signal is determined by the input terminal 1, the synchronization signal separation circuit 2, the phase synchronization circuit 3, the phase comparison circuit 4, the first level conversion circuit 5, the first phase shift circuit 6,
The first frequency multiplier circuit 7, the first A / D converter circuit 8, and the
Since the burst signal is removed for each burst signal by the circuit composed of one memory circuit 9, the jitter becomes 0 at the burst signal, and the phase of the video signal changes within one horizontal synchronization period as time elapses, and the amount of jitter decreases. Change. The phase error within one horizontal synchronization period is called a velocity error.
FIG. 4B is a graph showing the velocity error amount (here, the velocity error is shown by linear approximation). 4 (a) and 4 (b), t1, t2, t
3, t4 and t5 are phase errors detected by the phase comparison circuit 4 in FIG.

The data written in the first memory circuit 9 of FIG. 2 to eliminate the velocity error is stored in the first D / D
At the time of conversion into analog data by the A conversion circuit 10, the clock is phase-shifted by a velocity error.

Hereinafter, the operation will be described with reference to FIG.

In FIG. 2, reference numeral 11 denotes a second A / A for converting the output of the phase comparison circuit 4 from analog data to digital data.
The first timing signal generation circuit 12 converts the data into digital data for each horizontal synchronization period and writes the digital data into the second memory circuit 13.

The data written in the second memory circuit 13 is supplied from a second timing signal generation circuit 15 to which a reference clock having the same frequency as the burst signal input from the clock input terminal 14 is input, every one horizontal synchronization period. The signal is read by the generated timing signal, and is converted into an analog signal by the second D / A conversion circuit 16.

Based on the data output from the second D / A conversion circuit 16, a sawtooth-shaped velocity error correction waveform signal as shown in FIG. Although various methods are conceivable for the method of the waveform signal generating circuit 17, a waveform obtained by linear approximation is shown in FIG. That is, the waveform signal generation circuit 17 generates a ramp wave that linearly changes from 0 to V in one horizontal synchronization period with respect to the voltage V output from the second D / A conversion circuit 16.

The velocity error correction waveform signal generated by the waveform signal generation circuit 17 is supplied to the second level conversion circuit 1.
After the level is adjusted at 8, it is output to the second phase shift circuit 19. In accordance with the velocity error correction waveform signal, the second phase shift circuit 19 supplies the clock input terminal 14
Phase shifts the reference clock input from
The signal is sent to the frequency multiplying circuit 20, converted into a signal of n times frequency, read clock from the first memory circuit 9 and the first D
It is used as a conversion clock of the / A conversion circuit 10. An output from the second D / A conversion circuit 10 is obtained from a clock output terminal 21.

Here, the data read timing from the second memory circuit 13 must precede the data read timing from the second memory circuit 13 by one horizontal synchronization period. This is because when the waveform signal generation circuit 17 generates a velocity error correction waveform signal,
This is because the velocity error value at the end of the one horizontal synchronization period is required.

As described above, the jitter contained in the input video signal can be removed.

[0019]

However, in the above conventional example, since the input / output characteristics of the second phase shift circuit 19 and the phase comparison circuit 4 are different, the second level conversion circuit 18 is required to absorb the difference. become.

Therefore, between the velocity error removed by the clock output from the second phase shift circuit 19 and the velocity error actually detected by the phase comparison circuit 4, the second level conversion circuit 18 There is an error that depends on the conversion accuracy of.

In particular, when the input / output characteristics of the second phase shift circuit 19 and the phase comparison circuit 4 are not linear, the circuit configuration of the second level conversion circuit 18 becomes very complicated, and the level conversion accuracy is reduced. . Further, in the conventional example, there is a problem that the circuit configurations of the second phase shift circuit 19 and the second frequency multiplier circuit 20 are complicated.

The present invention has been made in view of the above circumstances, and has a simple configuration for correcting a time axis in an input video signal.
Accurately corrects velocity errors in the input video signal
It can, moreover, easily and sure adjusting loop gain
To provide a time axis correction device that can be actually performed
A and purpose.

[0023]

[0024]

Means for Solving the Problems] To achieve the above Symbol purpose time base correction apparatus according to claim 1 of the present invention, the input according to the write clock synchronized in phase with the input video signal
Write the video signal to the memory and follow the read clock.
Reading the video signal from the memory
This is a time axis correction device that corrects the time axis of the input video signal.
Thus, the phase synchronized with the synchronization signal in the input video signal
A phase synchronization signal generation means for generating a phase synchronization signal, the position
Using the phase synchronization signal to generate the write clock
A write clock generating means for outputting to the serial memory, the
The burst signal in the input video signal and the phase synchronization signal are
Input and the position of the burst signal and the phase synchronization signal.
A first phase comparator for detecting a phase difference, and the first phase ratio
A read clock having the same input / output characteristics as the comparator
Input a clock and a reference signal according to
A second phase for detecting a phase difference from the read clock
A comparator , the output of the second phase comparator and the first
An adder for adding the output of the phase comparator, output of the adder
A loop filter to which power is supplied, and the loop filter
Generating the read clock having a frequency according to the output of
An oscillator for outputting to the memory .
You.

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram of a time axis correction device provided with a clock generation device according to the present invention. This time axis correction device is the same as the conventional example shown in FIG. 2 except for a portion surrounded by a broken line. Therefore, the same reference numerals are given to the drawings, and description thereof will be omitted.

In FIG. 1, reference numeral 22 denotes a phase comparing circuit (first phase comparing means) which is a first phase comparing circuit (first phase comparing circuit) for comparing the phase of a stable reference clock input from the clock input terminal 14 with a target clock. (First phase comparing means).

The first phase comparing circuit 22 and the second phase comparing circuit (second phase comparing means) 4 for detecting a velocity error have the same internal configuration and the same input / output characteristics. Circuit. Reference numeral 23 denotes an output of the first phase comparison circuit 22 and a velocity error voltage value, that is,
An adder (adding means) for adding the output of the second phase comparison circuit 4 has a sufficient gain in a low frequency range, a loop filter for determining a response speed, and a voltage control oscillator (25) as an oscillating means. VCO: Voltage ControlledOscillato
r) and 26 are frequency dividers which divide the frequency of the output clock of the voltage controlled oscillator 25 by N and supply it to one input of the first phase comparator 22.

The first and second phase comparison circuits 22 and 4
As long as they have substantially the same input / output characteristics, they may have different circuit configurations, or may be adjustable so that they have substantially the same input / output characteristics even if they have different input / output characteristics.

Next, the operation of the portion surrounded by the broken line in FIG. 1 will be described. First phase comparison circuit 22, loop filter 2
4. A loop including the voltage controlled oscillator 25 and the frequency dividing circuit 26 constitutes a PLL circuit A. When the output of the adder 23 is zero, the clock output terminal 25a (ie, the output of the voltage controlled oscillator 25) Is adjusted so that a target clock of a predetermined frequency is obtained.

Here, if the input voltage of the velocity error voltage to the adder 23 is V1, the PLL circuit A locks the phase so that the output voltage of the first phase comparison circuit 22 becomes -V1. .

This is because when the first phase comparison circuit 22 has the same input / output characteristics as the second phase comparison circuit 4 for detecting a velocity error, the two inputs of the second phase comparison circuit 4 Indicates that the absolute value of the detected velocity error is the same as that of the detected velocity error, but the signs are different. That is, when the velocity error is obtained by linear approximation of 0 to φ, the phase difference between the output clock of the PLL circuit A and the output clock of the frequency divider 26 is 0 to
It changes linearly to -φ. That is, the clock output terminal 21
Provides a clock that follows the velocity error.

The other operations in FIG. 1 are the same as those in FIG.
And the description thereof is omitted.

[0046]

As described above in detail , the time axis of the present invention
According to the correction device , the velocity in the input video signal can be
City error can be accurately corrected, moreover, the first
Including the output of the second phase comparator and the output of the second phase comparator.
If the gain can be adjusted easily and reliably
This has the effect.

[0047]

[Brief description of the drawings]

FIG. 1 is a block diagram of a time axis correction device including a clock generation device according to an embodiment of the present invention.

[2] Conventional Examples time base correction with a clock generator of
It is a block diagram of an apparatus .

FIG. 3 is a waveform diagram of a video signal.

FIG. 4 is a diagram illustrating a state of a velocity error.

[Explanation of symbols]

 4 Phase Comparison Circuit (Second Phase Comparison Means) 22 Phase Comparison Circuit (First Phase Comparison Means) 23 Adder (Addition Means) 25 Voltage Controlled Oscillator (Oscillation Means)

Claims (1)

(57) [Claims] 1. A write clock phase-synchronized with an input video signal .
Write the input video signal to the memory according to the lock,
The video signal from the memory according to a read clock
To correct the time axis of the input video signal
A time-base correction device, comprising: a phase synchronization device that performs phase synchronization with a synchronization signal in the input video signal.
A phase synchronization signal generation means for generating a signal, generating the write clock by using the phase synchronization signal
Write clock generating means for outputting to the memory
When the burst signal in the input video signal and the phase synchronization signal
And the burst signal and the phase synchronization signal
A first phase comparator for detecting a phase difference between the first and second phase comparators, and
Input a clock according to the read clock and a reference signal.
To detect the phase difference between the reference signal and the read clock.
A second phase comparator for output, an output of the second phase comparator of the first phase comparator
An adder for adding an output, a loop filter output of the adder is supplied, the read frequency according to the output of said loop filter
An oscillator for generating a clock and outputting the clock to the memory.
A time axis correction device, characterized in that: