KR930010692B1 - Phase detecting and compensating circuit of clock signal of digital system - Google Patents

Abstract

Digital system which generates the different clock signals with two or more crystals, detects the phase difference and compensates the detected phase difference. This circuit compensates the phase difference per unit of 1 byte, 1 frame and 1 block. This system blocks include the 1st, 2nd crystals (10,20) which drive F1,F2 oscillating outputs, an 1/M division circuit (40) which divides F1 signal into 1/M divided signal, an 1/N division circuit (60) which outputs F2 signal, a 1st phase detection circuit (70) which generates 1st compensated signal, a 2nd phase detection circuit (80) which generates 2nd compensated signal, and a 1st phase compensation circuit (30) and 2nd phase compensation circuit (50).

Description

Clock Signal Phase Detection and Correction Circuit of Digital System

1 is a block diagram of a typical CD-WO encoding system.

2 is a general PLL circuit diagram.

3 is a block diagram of a clock signal phase detection and correction circuit according to the present invention.

4 is a detailed circuit diagram of one embodiment of FIG.

5 is an operation timing diagram of each part of FIG.

6 is a system configuration of an example in which the present invention is applied to FIG.

* Explanation of symbols for main parts of the drawings

10: first crystal 20: second crystal

30: 1st phase correction circuit 40: 1 / M division circuit

50: 2nd phase correction circuit 60: 1 / N division circuit

70: first phase detection circuit 80: second phase detection circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase detection and correction circuit, and more particularly to a phase difference generated between clock signals in a digital system using two or more different clock signals as two or more crystals. A clock signal phase detection and correction circuit for detecting and correcting a detected phase difference.

In digital systems where two or more crystals are used, such as in digital audio systems such as digital audio tape recorders (DAT) or compact disk players (CDP), system clock signals and analog-to-digital converters The required A / D conversion clock signal must be synchronized for every predetermined unit.

1 is a block diagram of an encoding system of a typical Compact Disk-Write Once read many (CD-WO). The first and second crystals (1 and 3) and the first and second division circuits (2 and 4) are shown in FIG. C), an A / D converter 5, a static random access memory (S-RAM) 6, an error correction circuit 7, and a modulation circuit 8. In FIG. 1, clock signals of different frequencies are oscillated in the first crystal 1 and the second crystal 3, respectively, and are divided by the first and second division circuits 2 and 4, respectively. When the audio signal input through the audio signal input terminal 9 is input to the A / D converter 5, the A / D converter 5 outputs the audio signal from the first frequency divider circuit 2. The digital audio data is converted into digital audio data, and the converted digital audio data is stored in the S-RAM 6 in synchronization with a clock signal output from the first division circuit 2. In addition, the digital audio data stored in the S-RAM 6 is error corrected coded in the error correction circuit 7, modulated in the modulation circuit 8, and output as serial data to be recorded on a compact disc (not shown). do. At this time, the clock signal output from the second division circuit 4 is used as the system clock signal during read, error correction coding and modulation of the digital audio data stored in the S-RAM 6.

On the other hand, in the circuit of FIG. 1, six clock signals of the L channel and the R channel are generally included between the synchronization signal and the synchronization signal (one frame interval). The phase must be in phase between the A / D conversion clock signal which is the output clock signal of the division circuit 2 and the system clock signal which is the output clock signal of the second division circuit 4. However, if the phase of the oscillation signal changes due to a product error or other cause of the first crystal 1 and the second crystal 3, the output clock signal of the first and second division circuits 2 and 4 The phase difference occurs, and the phase difference increases with time.

In order to correct the phase difference between the two signals as described above, a phase locked loop (PLL) circuit as shown in FIG. 2 has been generally used as a phase detection and correction circuit. When the signal of the frequency oscillated by the first crystal 11 of FIG. 2 is divided by the first division circuit 12 and used as the A / D conversion clock signal ADCLK, the system clock signal SYSCLK is first used as the second division circuit ( In step 17), the phase difference between the signal divided by the predetermined signal and the A / D conversion clock signal ADCLK is detected by the phase detection circuit 13 to generate a phase difference signal, and the low phase pass signal is generated as a low pass filter (LPF) 14. Aftermath. Then, the voltage controlled oscillator (VCO) 15 controls the signal of the oscillation frequency of the second crystal 16 according to the output voltage level of the LPF 14 to output the system clock signal SYSCLK. Therefore, the phase of the A / D conversion clock signal ADCLK and the system clock signal SYSCLK can be matched.

If the PLL circuit is used as described above, the phase difference between the two signals can be corrected, but the circuit becomes complicated and there is a problem that noise may occur due to the analog device by using a passive device.

Accordingly, an object of the present invention is to detect and detect a phase difference generated between clock signals without using an analog element in a phase detection and correction circuit of a digital system that uses two or more crystals to generate two or more different clock signals. The present invention provides a clock signal abnormality detection and correction circuit capable of correcting a phase difference.

Another object of the present invention is a phase detection and correction circuit of a digital system that uses two or more crystals to generate two or more different clock signals, wherein a phase difference occurs between one clock signal and one frame. The present invention provides a clock signal phase detection and correction circuit capable of correcting a phase difference for each desired unit such as 1 block unit.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram according to the present invention, in which the first and second crystals 10 and 20 and the first crystal 10 which oscillate and output the first and second signals F1 and F2 of different frequencies, respectively. The 1 / M division circuit 40 for dividing the first signal F1 to be output 1 / M and the second signal F2 output from the second crystal 20 are 1 / N for division of the 1 / M division circuit 40. 1 / N frequency division circuit 60 connected to 1 / N frequency division circuit 60, 1 / M frequency division circuit 40, and 1 / N frequency division circuit 60 for outputting a signal having the same frequency as that of the output signal. The output signal of the 1 / M frequency division circuit 40 is shifted to 1 by the transition of the output signal of the 1 / M frequency division circuit 40 from the first logic state to the second logic state when the output signal is in the first logic state. A first phase detection circuit 70 for detecting a phase difference that is faster than a phase of an output signal of the / N division circuit 60 to generate a first correction signal in a first logical state during the phase difference period, and a 1 / M division circuit ( 40) and the 1 / N division circuit 60 Understanding that the output signal of the 1 / N division circuit 60 transitions from the first logic state to the second logic state when the output signal of the 1 / M division circuit 40 is in the first logic state 1 / N division circuit 60 Second phase detection circuit (80) for detecting a phase difference where the phase of the output signal is faster than the phase of the output signal of the 1 / M division circuit (40) and generating a second correction signal in a first logical state during the phase difference period. Is connected to the first crystal 10 and the first phase detection circuit 70. The first signal F is logically multiplied with the output signal of the first phase detection circuit 70 to generate the first correction signal and the first signal during the generation period. The first phase correction circuit 30, the phase correction to the first logical state, the second crystal 20 and the second phase detection circuit 80 is connected to the second signal F2 of the second phase detection circuit 80 And a second phase correction circuit 50 which phase-corrects the second signal to the first logical state during the generation of the second correction signal by logical multiplication with the output signal.

An operation example of FIG. 3 according to the present invention will be described below.

When the power supply is turned on and the first and second signals F1 and F2 of different frequencies are respectively oscillated in the first and second crystals 10 and 20 of FIG. 3, the first phase correction circuit 30 The phase of one signal F1 is corrected and output as the first clock signal CLK1, and the second phase correction circuit 50 corrects the phase of the second signal F2 and output as the second clock signal CLK2. In this case, for example, when the first clock signal CLK1 is used as the A / D conversion clock signal ADCLK, the second clock signal CLK2 is used as the system clock signal SYSCLK.

The first signal F1 is divided into 1 / M by the 1 / M division circuit 40 and then input to the first phase detection circuit 70, and the second signal F2 is 1 / N by the 1 / N division circuit 60. After being divided, it is input to the second phase detection circuit 80 to detect the phase difference between the two signals. At this time, the second signal F2 is divided by 1 / N such that the first signal F1 is equal to the frequency of the 1 / M divided signal. In other words, the first and second signals F1 and F2 are divided by 1 / M and 1 / N, respectively, so that F1 / M = F2 / N.

The first and second phase detection circuits 70 and 80 detect the phase difference between the output signal of the 1 / M divider circuit 40 and the output signal of the 1 / N divider circuit 60 which are theoretically equal in frequency. . At this time, when the phase difference occurs, the first phase detection circuit 70 outputs the output signal of the 1 / M division circuit 40 to the second logic state when the output signal of the 1 / N division circuit 60 is in the first logic state. Detects a phase difference such that the phase of the output signal of the 1 / M frequency division circuit 40 is earlier than the phase of the output signal of the 1 / N frequency division circuit 60 and shifts to the first correction state of the first logical state during the phase difference period. A signal is generated and output to the first phase correction circuit 30. In addition, the second phase detection circuit 80 transitions the output signal of the 1 / N division circuit 60 from the first logic state to the second logic state when the 1 / M division circuit 40 is in the first logic state. By detecting the phase difference such that the phase of the output signal of the 1 / N division circuit 60 becomes faster than the phase of the output signal of the 1 / M division circuit 40, the second correction signal in the first logical state is detected during the phase difference period. Is generated and output to the second phase correction circuit 50. In this case, the first logic state refers to a logic flow state and the second logic state refers to a logic state. The first and second phase correction circuits 30 and 50 then multiply the first and second signals F1 and F2 by the first and second correction signals, respectively, during the first and second correction signal generation periods. The second signals F1 and F2 are phase-corrected in the first logic situation and output as the first and second clock signals CLK1 and CLK2. At this time, if the 1 / M division value of the 1 / M division circuit 40 and the 1 / N division value of the 1 / N division circuit 60 are adjusted, the phase correction timings of the first and second clock signals CLK1 and CLK2 can be adjusted. The phase difference can be corrected for each desired unit such as 1 byte, 1 frame, 1 block unit of data.

FIG. 4 is a detailed circuit diagram of one embodiment of FIG. 3, wherein the first and second crystals 10 and 20, the first and second phase correction circuits 30 and 50, and 1 / M division are similar to those of FIG. A circuit 40, a 1 / N division circuit 60, and first and second phase detection circuits 70 and 80 are formed.

In the configuration of FIG. 4, the first phase correction circuit 30 includes an AND gate 31 for ANDing the first signal F1 of the first crystal 10 and the output signal of the first phase detection circuit 70, and the AND gate ( The D flip-flop 32 which divides the output of 31) into 1/2 is output.

The second phase correction circuit 50 performs an AND gate 51 to logically multiply the second signal F2 of the second crystal 20 by the output signal of the second phase detection circuit 80 and the output of the AND gate 51. It consists of the D flip-flop 52 which divides into 1/2 and outputs.

)가 앤드게이트(31)의 일입력단에 접속되는 D플립플롭(72)으로 구성한다.The first phase detection circuit 70 has an inverter 71 for inverting the output signal of the 1 / N division circuit 60, a data input terminal D and a set terminal S connected to the power supply voltage Vcc. The clock terminal CLK is connected to the output terminal of the M division circuit 40, and the reset terminal R is connected to the output terminal of the inverter 71, and the inverted output terminal (

Is a D flip flop 72 connected to one input terminal of the AND gate 31.

)가 앤드게이트(51)의 일입력단에 접속되는 D플립플롭(82)으로 구성한다.The second phase detection circuit 80 includes an inverter 81 for inverting the output signal of the 1 / M division circuit 40, a data input terminal D, and a set terminal S connected to the power supply voltage Vcc. The clock terminal CLK is connected to the output terminal of the N division circuit 60, the reset terminal R is connected to the output terminal of the inverter 81, and the inverted output terminal (

Is composed of a D flip-flop 82 connected to one input terminal of the AND gate 51.

5 is an operation timing diagram of each part of FIG. 4.

An operation example of FIG. 4 according to the present invention will now be described in detail with reference to the timing diagram of FIG. 5.

Now, when the power is turned on and the first and second signals F1 and F2 of different frequencies are oscillated in the first and second crystals 10 and 20 of FIG. 4, the D flip of the first phase correction circuit 30 is performed. The flop 32 inputs a signal whose output signal of the first signal F1 and the first phase detection circuit 70 are logically multiplied by the AND gate 31 into the clock terminal CLK, and divides the signal by half. The output signal of the second flip-flop 52 of the second phase correction circuit 50 is the output signal of the second signal F2 and the second phase detection circuit 80 through the AND gate (Q). The signal multiplied by 51 is input to the clock terminal CLK, and divided into 1/2 and output as the second clock signal CLK2 through the non-inverting output terminal Q. In this case, for example, when the first clock signal CLK1 is used as the A / D conversion clock signal ADCLK, the second clock signal CLK2 is used as the system clock signal SYSCLK.

The first signal F1 is divided by 1 / M by the 1 / M division circuit 40 and then inputted to the clock terminal CLK of the D flip-flop 72 and inverted by the inverter 81 to be D flip-flop 82 Is input to the reset terminal (R). In addition, the second signal F2 is divided into 1 / N by the 1 / N division circuit 60 and then inputted to the clock terminal CLK of the D flip-flop 82 and inverted by the inverter 71 to be inverted by the D flip-flop 72. Is input to the reset terminal (R). At this time, the second signal F2 is divided by 1 / N such that the frequency of the first signal FIRK 1 / M is divided. In other words, the first and second signals F1 and F2 are divided into 1 / M and 1 / N, respectively, so that F1 / M = F2 / N. It is for.

In this state, if the first signal F1 and the second signal F2 are the same before starting, they should theoretically be exactly in phase. However, the phase of the oscillation signal is changed due to a product error or other causes of the first crystal 10 and the second crystal 20, so that the output of the 1 / M division circuit 40 becomes as shown in FIG. When the output of the N division circuit 60 becomes as shown in (b) of FIG. 5A, the phase of the output signal of the 1 / M division circuit 40 becomes faster than the phase of the output signal of the 1 / N division circuit 60. In the T1, T2, T5, and T6 sections of Fig. 5a, the inverted signal of the output signal of the 1 / N division circuit 60 becomes the logic high, which is the second logical state, so that the reset terminal R of the D flip-flop 72 The output signal of the 1 / M division circuit 40 enters the rising edge (↑) state, which transitions from the logic logic low in the first logic state to the logic logic high in the second logic state. 72 is input to the clock terminal CLK.

)를 통하여 제5a도의 (c)와 같은 논리 ＂로우＂의 제1보정신호(P11,P12,P13,P14)를 앤드게이트(31)로 출력한다. 따라서 상기 P11,P12,P13,P14의 제1보정신호가 발생하는 기간동안 제1신호 F1의 위상을 논리 ＂로우＂로 보정한다.The D flip-flop 72 is then set by the logic " high " signal and " up " state and reset when the inverted signal of the 1 / N division circuit 60 is a logic low. (

The first correction signals P11, P12, P13, and P14 of the logic flow as shown in (c) of FIG. 5A are outputted to the AND gate 31 through FIG. Therefore, the phase of the first signal F1 is corrected to a logic low during the period during which the first correction signals of P11, P12, P13, and P14 are generated.

The output signal of the 1 / M division circuit 40 is divided in the sections T3, T4, and T7 of FIG. 5A in which the phase of the output signal of the 1 / N division circuit 60 is faster than the phase of the output signal of the 1 M division circuit 40. The inverted signal of < RTI ID = 0.0 > is a < / RTI > logic " high " It is input to the clock terminal CLK of 82.

)를 통하여 제5a도의 (d)와 같은 논리 ＂로우＂의 제2보정신호(P21,P22,P23)를 앤드게이트(51)로 출력한다 따라서 위상차 만큼 즉, 상기 P21,P22,P23를 앤드게이트(51)로 출력한다. 따라서 위상차 만큼 즉, 상기 P21,P22,P23의 제2보정신호가 발생하는 기간동안 제2신호 F2의 위상을 논리 ＂로우＂로 보정한다.Then, the D flip-flop 82 is set by the " rising (↑) " state and reset when the inverted signal of the output signal of the 1 / M division channel 40 is a logic low.

And outputs the second correction signals P21, P22, P23 of the logic flow as shown in (d) of FIG. 5A to the AND gate 51. Therefore, the P21, P22, P23 as the phase difference, i.e. Output to (51). Accordingly, the phase of the second signal F2 is corrected to a logic low during the period in which the second correction signals of P21, P22, and P23 are generated by the phase difference.

Therefore, when the first signal F1 of oscillation output of the first crystal 10 is equal to (a) of FIG. 5b and the second signal F2 of oscillation output of the second crystal 20 is equal to (b) of FIG. 5b. If a phase difference occurs between the two signals and the first correction signal is output from the D flip-flop 72 in the T12, T13, and T15 sections as shown in (c) of FIG. 5b, the second correction signal is output from (d) of FIG. If it is outputted from the D flip flop 82 in the T11 and T14 sections as shown in the figure, a signal such as (e) of FIG. 5B is input to the clock terminal CLK of the D flip flop 32 and the clock of the D flip flop 52 is A signal as shown in FIG. 5B (f) is input to the terminal CLK. That is, the phase difference generated between the first and second phase correction circuits 30 and 50 in the first and second phase correction circuits 30 and 50, respectively, is corrected by the first and second correction signals, thereby providing the first and second clock signals. CLK1 and CLK2 are synchronized.

On the other hand, when F1 / M = F2 / N is satisfied, the 1 / M division value of the 1 / M division circuit 40 and the 1 / N division value of the 1 / N division circuit 60 are adjusted. The phase difference of signals as shown in (a) and (b) can be corrected for each desired unit such as 1 byte, 1 frame, 1 block unit of data.

6 is a system configuration diagram of an example in which the phase detection and correction circuit according to the present invention is applied to the encoding system of the CD-WO of FIG. 1 described above, and reference numeral 100 denotes a phase detection and correction circuit according to the present invention. Therefore, even if a phase difference occurs between the oscillation signals of the first crystal 1 and the second crystal 3 of FIG. 6, the phase can be matched for each desired unit between the A / D converted clock signal ADCLK and the system clock signal SYSCLK. .

It should be noted that the present invention can be used as the phase detector 13 in the general PLL circuit as shown in FIG. 2, and can be used for various other purposes in digital systems such as DAT.

As described above, the present invention is a digital system that uses two or more crystals to generate two or more different clock signals, and includes a circuit for detecting a phase difference and correcting the detected phase difference when a phase difference occurs between clock signals. There is an advantage that can be configured in simple logic without using. In addition, there is an advantage that the phase difference can be corrected for each desired unit by adjusting the division value for phase detection.

Claims (3)

A clock signal phase detection and correction circuit of a digital system having first and second crystals 10 and 20 oscillating and outputting first and second signals having different frequencies, respectively, The 1 / M division circuit 40 for dividing the output first signal by 1 / M and the second signal output from the second crystal 20 are divided by 1 / N for the 1 / N division circuit 40. A 1 / N division circuit 60 for outputting a signal having the same frequency as that of the output signal, and a 1 / N division circuit 60 connected to the 1 / M division circuit 40 and 1 / N division circuit 60, respectively. Phase of the output signal of the 1 / M division circuit 40 is shifted when the output signal of the 1 / M division circuit 40 transitions from the first logic state to the second logic state when the output signal of A first phase detection circuit 70 for detecting a phase difference that is earlier than a phase of the output signal of the 1 / N division circuit 60 to generate a first correction signal in a first logical state during the phase difference period, and It is connected to the M division circuit 40 and the first / N division circuit 60, and when the output signal of the 1 / M division circuit 40 is in the first logical state, the output signal of the 1 / N division circuit 60 becomes the first signal. By shifting from the logic state to the second logic state, the phase difference at which the phase of the output signal of the 1 / N division circuit 60 becomes faster than the phase of the output signal of the 1 / M division circuit 40 is detected, and the phase shift period is changed. A second phase detection circuit 80 for generating a second correction signal in a logical state, the first crystal 10 and the first phase detection circuit 70, and connecting the first signal to the first phase detection circuit; A first phase correction circuit 30 which phase-corrects the first signal to a first logic state during the generation period of the first correction signal by logically multiplying the output signal of the circuit 70, and the second crystal 20 and the first phase correction circuit 30; Connected to a two-phase detection circuit 80 and logically multiplying the second signal by an output signal of the second phase detection circuit 80 to generate a second signal during the generation period of the second correction signal. A clock signal phase detection and correction circuit of a digital system, characterized by comprising a second phase correction circuit (50) for phase correction to a first logical state. The AND gate 31 of claim 1, wherein the first phase correction circuit 30 logically multiplies the first signal of the first crystal 10 by the output signal of the first phase detection circuit 70; And a D flip-flop (32) for dividing the output of the AND gate (31) by half to output the clock signal phase detection and correction circuit of the digital system. 3. The inverter of claim 2, wherein the first phase detection circuit 70 inverts the output signal of the 1 / N division circuit 40, and a data input terminal and a set terminal are connected to a power supply voltage. The clock terminal is connected to the output terminal of the 1 / M division circuit 40, the reset terminal is connected to the output terminal of the inverter 71, and the inverted output terminal is connected to one input terminal of the AND gate 31. Clock signal phase detection and correction circuit of a digital system.

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