JPH0744680B2 - Time axis error correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICABILITY The present invention provides high-speed operation for time-axis fluctuations contained in reproduced video signals.
The present invention relates to a time axis error correction device that obtains a clock signal that tracks high performance and removes a time axis fluctuation of a reproduced video signal to obtain a high quality video signal.

Conventional technology In order to remove the time axis error component of the reproduced video signal of the conventional VTR, etc., the reproduced video signal is A / D-convert and write to storage device
The error voltage of the analog amount of the circuit etc. is used as the speed error voltage, and the modulated clock signal obtained by analog-phase-modulating the reference clock signal according to this speed error voltage is read from the storage device and D / A converted. There has been proposed a time axis error correction device that does.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above configuration, the speed error is detected as a voltage level or a pulse width by using the analog phase comparator, and this speed error is converted into the modulation voltage of the analog phase modulator to obtain the clock signal. Since the phase modulation is performed, there is a problem that it is not possible to accurately and stably detect the speed error and the phase modulation due to the influence of the leakage of the capacitor, the variation of the parts, the temperature characteristic, the noise and the like. Further, in order to perform the above-mentioned detection and modulation with high accuracy, complicated adjustment is necessary, which is a big problem in mass production.

Furthermore, since the speed error voltage is detected as an analog quantity,
Precision is required in analog signal processing to store or perform complex conversion processing. There is a problem in stability, and digital converters such as A / D converters are required to process digital signals. Also, A / D conversion is performed using a clock signal that contains a speed error, and the speed error correction is completed by reading from the storage device and D / A conversion.
The / D-converted sample values themselves contain time-axis fluctuation components due to velocity errors, which poses a serious problem in filtering and image processing by digital signal processing after that.

In view of the above point, the present invention provides a time axis error correction device that does not require adjustment by performing time axis error correction with high accuracy and high stability and performing correction by digital signal processing.

SUMMARY OF THE INVENTION The present invention provides a reference clock signal and its 1 / N clock (N = 2).
ⁿ n = 1,2, ...) 1 horizontal scanning reference time length of counting the reference clock signal and the detection time length of 1 horizontal scanning period of the reproduced video signal detected using the delayed clock signal The difference is written in the storage device I obtained as a speed error signal by a binary code, and the speed error in the next horizontal scanning period is predicted by polynomial approximation from the speed error signal at the current time and the speed error signal in the previous several horizontal scanning periods. To obtain the speed error correction signal,
The reference clock signal is phase-shifted to a reference position for each horizontal scanning of the reproduced video signal to perform phase synchronization, and the phase-synchronized clock signal is phase-shifted according to the speed error correction signal. A time-axis error correction device for A / D converting a reproduced video signal, writing the same in a storage device II, reading from the storage device II with a predetermined stable clock signal, and performing D / A conversion to remove a time-axis fluctuation of the reproduced video signal. Is.

Operation According to the present invention, the clock signal for A / D converting the reproduced video signal having the above-described configuration synchronizes the phase of the reference clock signal with the reference position for each horizontal scanning of the reproduced video signal to reduce the fluctuation of the time axis. Synchronizing with the band frequency component, digitally detecting the speed error of the reproduced video signal with an accuracy of 1 / N clock of the reference clock signal, predicting the speed error in the next horizontal scanning period, and correcting the speed error. By synchronizing with the high frequency component of the time base fluctuation by
It is possible to remove a time axis error with high accuracy and high stability that does not leave a time axis error in the D-converted sample value.

Examples Examples of the present invention will be described below. FIG. 1 is a block diagram of a time axis error correction device of this embodiment, and FIG.
3 is an operation waveform diagram of the phase shifter 5, FIG. 3 is a waveform diagram of the time axis error of the reproduced video signal, and FIG. 4 is a time axis error predicted by a cubic polynomial approximation of the velocity error to obtain a velocity error correction signal. Waveform diagram, FIG. 5 is a block diagram of the speed error correction signal detector 7 and the second phase shifter 8, and FIG. 6 is a waveform diagram for explaining the operation of FIG.

In the present embodiment, a reference clock signal and a delayed clock signal for each 1/8 clock thereof are used, and the speed error correction is 3
Description will be made by taking a case of the second-order polynomial approximation as an example.

The reproduced video signal is input from the input terminal 1 to the A / D converter 3 and the burst signal detector 4. The detected burst signal output from the burst signal detector 4 is input to the first phase shifter 5 and, for example, the rising edge of the first wave is detected. Second
FIG. A shows this first burst signal. In the first phase shifter 5, the first burst signal A, the reference clock signal B and the delayed clock signal delayed by 1/8 clock
The phases of C, D, E, F, G, H, and I are compared, and the closest clock signal is selected every 1H (H: horizontal scanning period), and the phase-locked clock signal J is output. The reference clock signal B is generated by the reference clock signal generator 9 in phase synchronization with the reference H input from the input terminal 2. The speed error detector 6 detects the 1H time length of the detected burst signal using the reference clock signal and seven delayed clock signals delayed by 1/8 clock, and counts the reference clock signal. The difference from the 1H time length is output as the speed error signal ΔVi. ΔVi in FIG. 3 is this speed error signal, which is given by, for example, a 6-bit binary code. In this case, the speed error range is ± 4 clocks, the sign bit is 1 bit from the high order of 6 bits, and the speed error per clock is 2 bits,
The speed error in the clock is 3 bits.

In the speed error correction signal generator 7, the speed error signal ΔVi
Is written into the storage device at any time, and the next speed error ΔV ′ _{n + 1} is predicted by approximating a third-order polynomial from ΔV _{n at the} current time and ΔV _n-1 and ΔV _n-2 before that. The error correction signal Y _{n + 1} (t) is output. FIG. 4 is a waveform diagram for explaining the operation.

The speed error correction signal Y (t) is approximated by the following equation.

Y (t) = at + bt ² + ct ³ Here, the horizontal scanning period at the current time is n, and Y _{n + 1} (t) is a speed error correction signal in the next horizontal scanning period, (Count number in TCK: 1H, count number in 1HCK: 1H 0 ≦ t ≦
Assuming 1), Y _{n + 1} (t) = at + bt ² + ct ³ = ∫ (a + 2bt + 3ct ² ) dt = ∫ (X _{n + 1} (t) dt Y _{n + 1} (0) = 0, Y _{n + 1} (1) = ΔV ′ _{n + 1} X _{n + 1} (t): Velocity error differential signal, ΔV ′ _{n + 1} : Predicted velocity error signal To be

The second phase shifter 8 uses the speed error correction signal Y
_{According to n + 1} (t), a clock signal is selected from the phase-locked clock signal and delayed clock signals of 1/8 clock to obtain a phase-corrected clock signal. The reproduced video signal is A / D converted by the A / D converter 3 by this phase correction clock signal, and writing in the storage device 10 is controlled. The reading of the storage device 10 and the D / A converter 11 are controlled by the reference clock signal, and the reproduction video signal from which the time axis error component is removed is output to the output terminal 12.

Next, the speed error correction will be described with reference to FIGS. 5 and 6.

The playback H signal of the playback video signal is input to the input terminal 13.
The speed error signal ΔVi is input to 14 and the phase synchronization clock signal is input to the input terminal 15. The storage device 16 is a 6-bit shift register, which sequentially shifts the speed error signal to obtain the current time n.
, ΔV _n , ΔV _n-1 , and ΔV _n-2 are output to the calculator 17. The calculator 17 calculates the coefficient abc on the basis of the above third-order polynomial approximation and outputs the speed error differential signal X _{n + 1} (t) at each time T. This X _{n + 1} (t) (FIG. 6L) consists of a pulse at a predetermined position of 1H and its sign bit signal. For example, when ΔV ′ _{n + 1} = 000101, the phase should be corrected within the 1H period. number,
That is, five pulses are generated. up / doun counter 1
Reference numeral 8 indicates that the reproduced H signal is queried, and then the speed difference differential signal X _{n + 1} (t) is used as a clock to up the code bit signal.
/ doun is controlled and counted, speed error correction signal Y
_{n + 1} (t) (FIG. 6, M, N, O) is output. This count up
Or doun corresponds to the integral of Y _{n + 1} (t) = ∫X _{n + 1} (t) dt. In the selector 20, the clock signal is CK according to the speed error correction signal Y _{n + 1} (t) from the phase synchronization clock signal (CK2) and the delayed clock signals (CK2 to CK8).
It is sequentially switched to 1, CK2, ... And output to the output terminal 29 as a phase correction clock signal. The D-FF 19 controls the clock switching timing by the phase correction clock signal delayed by the delay device 21.

As described above, according to the present embodiment, the reference clock signal is phase-synchronized with the burst signal of the reproduced video signal to obtain the phase-synchronized clock signal, and the speed error of the reproduced video signal is reduced to 1/8 of that using the reference clock signal. It is directly detected with the accuracy of the clock, the velocity error in the next horizontal scanning period is predicted from this velocity error signal by the third-order polynomial approximation to obtain the velocity error correction signal, and the phase of the phase synchronization clock signal is sequentially shifted. The reproduced video signal is A / D converted with the phase correction clock signal obtained and written in the storage device, and the D / A conversion is performed with the reference clock signal to perform high-speed follow-up, highly accurate and highly stable removal of time axis fluctuations. Can be done. In addition, since the phase-locked clock signal and the correction clock signal can be obtained by complete digital signal processing, no VCO or analog phase modulator is required and no circuit adjustment is required, which may be caused by component variations or signal processing system noise. Little deterioration in characteristics.

Further, since the time axis fluctuation has already been removed from the sample value of the reproduced video signal that has been A / D converted, it is very convenient for subsequent signal processing.

In this embodiment, the phase-locked clock signal is generated, the speed error is detected, and the phase-corrected clock signal is generated by using the reference clock signal and the delayed clock signals of 1 / 8th of the reference clock signal. The same effect can be obtained by performing the above processing using only the reference clock signal and the delayed clock signal of the multiplied clock signal and its 1/2 clock. In this case, many delay units are not required and delay variation There is little deterioration in accuracy due to changes in the clock duty.

As described above, according to the present invention, the time base error of the reproduced video signal is detected with the accuracy of 1 / N clock of the reference clock signal, and not only the low band frequency component of this time base error but also the high band Since it is possible to obtain a clock signal in which even the frequency component is phase-synchronized, the time axis error component of the reproduced video signal can be accurately and stably removed. In addition, since all system digital signal processing is performed, no circuit adjustment or the like is necessary.

[Brief description of drawings]

FIG. 1 is a block diagram of a time axis error correction apparatus according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of a first phase shifter of the same embodiment, and FIG. 3 is a reproduced video signal of the same embodiment. FIG. 4 is a waveform diagram of the time axis error, FIG. 4 is a waveform diagram for obtaining the speed error correction signal of the same embodiment, and FIG. 5 is a block diagram of the speed error correction signal generator and the second phase shifter of the same embodiment, FIG. 6 is a waveform diagram for explaining the operation of FIG. 3 ... A / D converter, 4 ... Burst signal detector, 5 ...
First phase shifter, 6 ... Speed error detector, 7 ... Speed error correction signal detector, 8 ... Second phase shifter, 9
...... Reference clock signal generator, 10 …… Storage device, 11 ……
D / A converter.

Front page continued (72) Inventor Shigeru Awamoto 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. ) References Japanese Patent Laid-Open No. 53-148317 (JP, A) Actually published 54-126682 (JP, U)

Claims (4)

[Claims] 1. A reference time length of one horizontal scanning period obtained by counting a predetermined number of reference clock signals and a time length of one horizontal scanning period of a reproduced video signal including a time axis error component are detected using the reference clock signal. Means for obtaining the speed error signal from the difference between the detected detection time length, means for storing the speed error signal in the storage device, the speed error signal at the current time and the previous several horizontal scanning periods stored in the storage device. Means for obtaining a speed error correction signal by predicting a speed error signal within the next horizontal scanning period from the speed error signal, and shifting the phase of the reference clock signal to a reference position for each horizontal scanning of the reproduced video signal. Means for obtaining a phase-locked clock signal; means for phase-shifting the phase-locked clock according to the speed error correction signal to obtain a phase-corrected clock signal; Time base error correcting apparatus characterized by having at least a means for A / D conversion of video signals. 2. A reference clock signal and N- delayed by 1 / N (N = 2 ⁿ , n = 1, 2, ...) Of this reference clock signal.
3. The method according to claim 1, wherein the time length of one horizontal scanning period of the reproduced video signal is detected and the phase synchronization clock signal and the phase correction / correction clock signal are generated by using one delay clock signal. The time axis error correction device described. 3. L times the reference clock signal (L = 2 ^l , l =
1, 2 ...) and a multiplied clock signal delayed by 1 / M clock (M = 2 ^m , m = 1,2 ...) of this multiplied clock signal are used. The time axis error correction apparatus according to claim 1, wherein the time length of one horizontal scanning period of the reproduced video signal is detected and the phase synchronization clock signal and the phase correction clock signal are generated. 4. A speed error correction signal in the next horizontal scanning period is obtained by polynomial approximation from the current time of the speed error signal and the speed error signals in several horizontal scanning periods before that. The time axis error correction device according to the second or third term.