JPS63131787A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To form a stable clock generating circuit concerning a temperature characteristic, etc., by changing a time width from the starting time point of the inclination part of a trapezoidal wave up to a sampling point (lock point) based on reproducing speed information. CONSTITUTION:For the phase comparison of a resetting type AFC circuit, a trapezoidal wave sample holding system is adopted, and a means 20 to detect the reproducing speed information from the horizontal synchronizing signal of an input reproducing video signal is provided. With the reproducing speed information, a time width A from the starting point time of the inclination part of a trapezoidal wave signal up to a sampling time point is changed in accordance with a reproducing speed. Since the time width A is changed in accordance with the reproducing speed, even at the time of a resetting type AFC circuit, it follows the change of a reproducing horizontal synchronizing signal correctly. Thus, the direct current gain of an AFC loop can be increased and the circuit intensifies to a temperature characteristic, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a lock signal generation circuit suitable as a write clock generation circuit for, for example, a time axis error correction device for reproduced video signals.

[Essentials of invention]

The present invention uses a loose set type AFC circuit as a clock signal forming circuit that forms a clock signal synchronized with a reproduced video signal, and even if a trapezoidal wave sample-hold method with a simple configuration is used for phase comparison, A during variable speed playback by using playback speed information
This allows the FC to follow accurately.

[Conventional technology]

For example, a reproduced video signal from a VTR includes a time axis error, and a time axis error correction device is used to remove this error.

Figure 3 shows an overview of this time axis error correction device.
The reproduced video signal SV through the input terminal (1) is converted into a digital video signal by the A/D converter (2). This digital video signal is synchronized with the reproduced video signal SV.
Therefore, the data is written to the memo January 3) by the write clock signal WCK having the same time axis error as the reproduced video signal.

The written digital video signal is read from the memo January 3) by the read clock signal RCK, which has the same frequency as the write clock signal WCK but has no time axis error, from the read clock generation circuit (4). time axis error is removed.

This digital video signal having no time axis error is returned to an analog video signal by the D/A converter (5). Since the video signal from this D/A converter (5) does not include a synchronization signal and a burst signal, this analog video signal is transferred to the synchronization signal and burst signal addition circuit (6).
), and after a synchronization signal and a burst signal are added thereto, it is led out to an output terminal (7).

The write clock signal WCK forming circuit (8) is an AFC.
Consists of circuits. That is, the reproduced video signal SV from the input terminal (1) is supplied to the synchronization separation circuit (81), from which a reproduced horizontal synchronization signal is obtained, and this reproduced horizontal synchronization signal is supplied to the phase comparison circuit (82). . On the other hand, (83
) is a variable frequency oscillation circuit for obtaining an oscillation output signal with a frequency of N-fH (fH is the reproduction horizontal synchronization frequency), and the oscillation output signal is supplied to the frequency divider circuit (84) and divided into 1/N. It will be done. The output signal CH of the frequency dividing circuit (84) is supplied to a phase comparator circuit (82), where the phase is compared with the reproduced horizontal synchronizing signal. The comparison error output is passed through a low-pass filter (85) to a variable frequency oscillation circuit (83).
and is controlled so that its oscillation output signal is phase-locked with the reproduced horizontal synchronization signal.

That is, the output signal of the variable frequency oscillation circuit (83) includes the same phase error as the time axis error included in the reproduced video signal SV. The output signal of this variable frequency oscillation circuit (83) becomes the write clock signal WCK.

[Problem that the invention seeks to solve]

As the write clock signal forming circuit (8) as described above, a reset type AFC circuit is used that resets the variable frequency oscillation circuit (83) and the frequency dividing circuit (84) by a signal synchronized with the horizontal synchronization signal. There are many things that happen.

Incidentally, it would be advantageous in terms of configuration and cost if a so-called trapezoidal sample-and-hold system could be used as the phase comparator circuit of the AFC circuit.

Furthermore, in order to be able to ignore the influence of temperature characteristics, etc. in the AFC circuit, it is desirable to increase the DC gain of the AFC loop.

However, when using a reset type AFC circuit and a trapezoidal sample-hold type phase comparator circuit, the AFC loop cannot be used for the reproduced video signal during variable speed playback other than normal playback. The reason why AFC cannot follow up when the DC gain is high is as follows.

In the case of phase comparison using the trapezoidal wave sample and hold method, a trapezoidal wave SL (FIG. 4B) is formed based on the signal CH (FIG. 4A) from the frequency dividing circuit (84). On the other hand, the sampling pulse SP formed based on the horizontal synchronization signal (C in the same figure)
As a result, the slope portion of the trapezoidal wave SL is sampled as shown in the figure. This sampling value is then supplied to the variable frequency oscillation circuit via a low-pass filter to control its oscillation frequency. In this case, when the phase is locked, the time width A from the start point of the slope portion of the trapezoidal wave to the sampling point (lock point) is constant.

Since the slope of the trapezoidal wave SL is constant, if the DC gain of the AFC loop is high, the lock phase in the slope part of the trapezoidal wave will hardly change even if the playback horizontal frequency changes as in variable speed playback. . Therefore, the time width A remains approximately constant regardless of the playback speed even during variable speed playback.

Since the time width B from the phase lock point of the slope part of the trapezoidal wave to the start point of the slope part of the next trapezoidal wave changes according to the playback speed during variable speed playback, AFC can accurately track it. It means you haven't done it.

That is, for example, at a certain playback speed, the number of pulses of the write clock signal WCK included in one horizontal period is 1.
Assume that there are 000 shots. The frequency division counter is reset to zero by the pulse SP and starts counting from there. It is assumed that the slope portion of the trapezoidal wave SL starts when the signal WCK is counted 900 times.

If the AFCI circuit is tracking accurately, the signal WC will be detected within the period of the reproduced horizontal synchronizing signal, that is, within the sampling pulse interval.
Originally, the barrel was supposed to contain 1000 K rounds.

During variable speed playback, the playback horizontal synchronization frequency changes depending on the playback speed, so the frequency of the signal WCK also changes, so the signal W
The time for CK's 900 shots @B will also change. However, since the time @A does not change, the number of pulses of the signal WCK included within this time width A differs depending on the difference in reproduction speed. Therefore, originally, the time width between sample pulses is the signal WCK
What should have been 1000 shots has changed depending on the playback speed. This means that AFC is not tracking accurately. Since the AFC circuit is a reset type, it only appears to be locked even though it is not tracking accurately.

As mentioned above, when adopting the trapezoidal sample and hold method for phase comparison of a reset type AFC circuit, the AFC
The drawback is that the DC gain of the loop cannot be increased and it is easily affected by temperature characteristics.

This invention improves this drawback.

[Means for solving problems]

In this invention, a trapezoidal wave sample and hold method is adopted for phase comparison of a reset type AFC circuit, and a means is provided for detecting reproduction speed information from a horizontal synchronization signal of a manually reproduced video signal. The time width A from the start point of the fq4 diagonal portion of the wave signal to the sampling point is changed in accordance with the playback speed.

(Function) Since the time width A changes depending on the playback speed, even a reset type AFC circuit can accurately follow changes in the playback horizontal synchronization signal. Therefore, the DC gain of the AFC loop can be increased, making it more resistant to temperature characteristics.

〔Example〕

FIG. 1 shows an embodiment of the present invention.

(11) is a variable frequency oscillation circuit that obtains a signal with a frequency of N-fH, from which a clock signal CK controlled to be synchronized with a reproduced horizontal synchronizing signal is obtained as will be described later. This clock signal CK is supplied to a frequency dividing circuit (12), and from this, a signal C whose frequency is divided by 1/N is output.
H (FIG. 2A and D) is obtained, which is supplied to the trapezoidal waveforming circuit (13). This trapezoidal waveforming circuit (13) is composed of, for example, a charging/discharging circuit. For example, as shown in FIG. 2B and FIG. formed, ['
1) When CH becomes high level, a discharge occurs instantaneously and a trapezoidal wave SL is formed. In this case, the second
As shown in FIGS. B and E, the inclination angle of the inclined portion can be changed by, for example, changing the magnitude of the charging current or changing the charging time constant using an external signal.

The trapezoidal wave signal SL from this trapezoidal wave forming circuit (13) is supplied to a sample hold circuit (14).

On the other hand, the reproduced video signal SV is supplied to the synchronization separation circuit (16) through the input terminal (15) to separate the reproduced horizontal synchronization signal, and this reproduced horizontal synchronization signal is supplied to the sampling and reset pulse forming circuit (17). , from this pulse SP synchronized with the reproduced horizontal synchronization signal (Fig. 2 C and F
) is obtained, and this pulse SP is sent to the sample and hold circuit (
14) as a sampling pulse, thereby sampling the slope portion of the trapezoidal wave SL, and holding the sampled value. The hold output is then supplied to the variable frequency oscillation circuit (11) via the low-pass filter (18) and amplifier (19), and its oscillation frequency is controlled.

In this case, the variable frequency oscillation circuit (11) is one whose voltage-frequency conversion characteristics are as linear as possible.

The pulse SP is also supplied as a reset pulse to the variable frequency oscillation circuit (11) and the frequency dividing circuit (12),
The oscillation circuit (11) is reset by stopping its output during the pulse width period of the reset pulse, and the counter constituting the frequency dividing circuit (12) is reset to a zero count value.

In this case, the reproduced horizontal synchronization signal from the synchronization separation circuit (16) is supplied to the reproduction speed detection circuit (20),
For example, by measuring the period of the reproduced horizontal synchronization signal,
It is detected at what reproduction speed the input reproduction video signal SV is reproduced. This playback speed detection signal is then supplied to a trapezoidal wave forming circuit (13), and the side of the slope portion of the trapezoidal wave is changed according to the playback speed. In this case, when the reproduction synchronization signal frequency becomes high, the slope becomes steeper, and when it becomes low, the slope becomes gentler.

For example, FIGS. 2A to 2C show the frequency dividing circuit (12) for a reproduced video signal during variable speed reproduction at a certain predetermined reproduction speed v1.
output signal CH, trapezoidal wave SL, sampling pulse SP
In this case, the fq4 oblique angle of the trapezoidal wave SL is B1, while D-F in the same figure shows playback during variable speed playback when the playback horizontal synchronization signal frequency is higher than this at a playback speed v2. For each signal CH, SL, and SP in the case of a video signal, if the slope angle of the trapezoidal wave SL is B2, then B2>B1.

At this time, since the DC gain of the AFC loop is set high, the sample and hold outputs are at the same level in the locked state. The time width from the sampling point (lock point) of the slope part of the trapezoidal wave to the start point of the slope part of the next trapezoidal wave is 81% at playback speed ■1.
At playback speed v2, B2 (B2 < Bt) is obtained, but the number of pulses of the clock GK included in the time width B and B2 is the same number. In addition, the time width from the start point of the slope part of the trapezoidal wave SL to the sampling point also changes depending on the playback speed, so at playback speed Vl it is A1, at playback speed v2 it is A2, and at playback speed V2 it is A2.
1≠A2, and in addition, A2<A depending on the playback speed.
It becomes 1. The number of pulses of the clock signal WCK included in 1 and A2 in this time width is also the same number.

Therefore, the number of pulses of the clock signal WCK included within the time width of A1+81 is equal to the number of pulses of the clock signal WCK included within the time width of A2''B2.In other words, even if the playback speed changes, the AFC follows this exactly.

In the above example, the slope angle of the slope part of the trapezoidal wave was changed by the playback speed information, but if the offset voltage of the amplifier (19) is changed by the playback speed information, the lock point in the slope part can be changed. Similarly, the time width from the start point of the slope portion to the lock point can be changed depending on the playback speed.

Further, the present invention is applicable not only to the case of forming a write clock signal for time axis error correction, but also to all cases of obtaining a clock signal synchronized with a reproduced video signal.

〔Effect of the invention〕

As described above, according to the present invention, the reset type AFC circuit In this case, it has become possible to increase the DC gain of the AFC loop even when trapezoidal wave sample and hold is used for the phase comparison.

Therefore, it is possible to construct a lock generation circuit that is stable in terms of temperature characteristics, etc., and the construction is simple because the trapezoidal wave sample-and-hold method phase comparison is used.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a timing chart for explaining the same, and FIG. 3 is a block diagram of an example of a time axis error correction device to which the present invention is applied.
FIG. 4 is a timing chart for explaining this. (11) is a variable frequency oscillation circuit, (12) is a frequency dividing circuit,
(13) is a trapezoidal wave forming circuit, (14) is a sample hold circuit, (16) is a sync separation circuit, (17) is a sampling and reset pulse forming circuit, (18) is a low pass filter, (20) is a playback speed detection It is a circuit. Makishaku 3, 1 rare positive circuit n year old repaired diagram Figure 3

Claims (1)

[Claims] A synchronization separation circuit that separates a reproduced horizontal synchronization signal from a reproduced video signal, a variable frequency oscillation circuit that obtains a signal with a frequency N times the horizontal frequency, and an output signal of the variable frequency oscillation circuit that is A frequency dividing circuit that divides the frequency into N, a trapezoidal wave forming circuit that forms a trapezoidal wave signal based on the output signal of this frequency dividing circuit, and a trapezoidal wave forming circuit that samples and holds the slope part of the trapezoidal wave signal from this trapezoidal wave forming circuit. a low-pass filter to which the output of the sample-and-hold circuit is supplied and outputs a signal for controlling the oscillation frequency of the variable frequency oscillation circuit; a pulse forming circuit that generates a sampling pulse to the sample hold circuit and a reset signal to the variable frequency oscillation circuit and frequency divider circuit; and a playback speed detection circuit that detects the playback speed from the playback horizontal synchronization signal from the synchronization separation circuit. The time width from the start point of the slope portion of the trapezoidal wave signal in the sample hold circuit to the sampling point is changed in accordance with the playback speed based on the playback speed detection output, and the variable frequency oscillation is performed in accordance with the playback speed. A clock signal generation circuit that obtains a clock signal synchronized with a reproduced video signal from the circuit.