JPH03121686A - Clock signal recovery circuit - Google Patents

Abstract

PURPOSE:To obtain a stable PLL output with fast locking by varying a gain of a low pass filter so as to increase the response speed when an output signal of a phase comparator is change within a short time at the specific search mode. CONSTITUTION:The circuit is provided with an input terminal 1, a synchronizing signal discrimination extraction circuit 2, a phase comparator output switching signal generating circuit 3, a phase comparator 4, a phase comparator output changeover switch 5, a low pass filter 6, a voltage controlled oscillator 7, a 1/n frequency divider 8 and an output terminal 9. When the state in the specific search mode is changed and an output signal of the phase comparator 4 outputted to the low pass filter 6 is changed within a short time, the PLL loop is locked quickly to a stable point by increasing the gain of the low pass filter 6 and increasing the voltage change outputted to the voltage controlled oscillator 7. Thus, the stable PLL output with fast locking is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a video tape recorder (hereinafter referred to as a VTR).

Conventional technology In a digital signal processing circuit such as a TBG (time pace corrector) of a VTR, a write pulse to the memory is generally used to reset the address of the memory using a reference signal obtained based on a horizontal synchronization signal or a burst signal. A reset pulse is generated by a voltage controlled oscillator (hereinafter abbreviated as ``CO'') of a clock PLL circuit whose phase is locked to a reference signal, and is used as a write clock to the memory. In this PLL circuit, if a skew of a certain period or more occurs during head switching, the operation of the phase comparator is completely inhibited for a certain period of time based on the information of the head switching signal and the vertical synchronization signal. Resetting the divider circuit,
Alternatively, the presetting is configured to be performed based on an input signal.

Problem to be Solved by the Invention However, when playing back a VTR, the PLLL having the above-mentioned conventional configuration! ! When using a circuit, it is possible to deal with large skews over a certain period of time when one head is switched, but if small skews or large dropouts occur due to expansion and contraction of the Q7, the PLL loop will be disturbed and stability will not be achieved. It takes a certain amount of time to bring the signal to a certain point.To shorten this time, it is possible to increase the response speed of the PLL, but if it is increased too much, there is a limit because it has the negative effect of making it less susceptible to noise. In other words, it takes a certain period of time, for example several 11 periods (H = horizontal scanning period), for the PLL circuit to stably draw in the discontinuous reference signal of the input signal, and during that time the PLL circuit outputs In other words, there was a problem in that the output of the VCO used for the write clock etc. was not guaranteed.

The present invention solves the above problem, and Vc.

The object of the present invention is to provide a clock signal generation circuit that guarantees the output of the clock signal.

Means for Solving the Problems In order to solve the above problems, the clock signal regeneration circuit of the present invention includes a voltage controlled oscillator that outputs a clock signal with a frequency corresponding to an input level, and a voltage controlled oscillator that inputs the clock signal and generates the clock signal t. /n (n Ire positive integer) A frequency divider that divides the frequency by K and outputs it, and a synchronization signal that inputs a synchronization signal and calculates the synchronization signal interval by t1' in fixed clock units based on this synchronization signal, and then calculates the synchronization signal by 11. Synchronization that averages the signal intervals, generates a window signal for the time period in which the next synchronization signal will occur based on this average data, and uses this window signal as a gate signal to extract and output only the synchronization signals at the correct time interval. The synchronization signal outputted from the synchronization signal extraction means and the clock signal frequency-divided by the frequency divider are inputted to a signal extraction means, the phases of these synchronization signals and the clock signal are compared, and the output is normally time-keeping. a phase comparator that outputs a phase signal whose output is held for a long time, and a synchronization signal output from the synchronization signal extraction means, and a phase comparator that outputs a phase signal whose output is held for a long time; A selection means for selecting and outputting two phase signals output from the phase comparator, and a phase signal 4j of the phase comparison visit No. 1171 selected by this selection means are input, and when this phase signal suddenly changes, a gain t is inputted.
and a low-pass filter that converts the signal into f and outputs it to the voltage controlled oscillator.

Operation Using the above configuration, in order to judge whether the input signal, the synchronization signal, is at the correct time interval, the synchronization signal extracting means calculates the time interval of the synchronization signal in units of fixed clocks by the number of tt, and averages the data obtained by the number of tt. Based on this average data, a window signal (pulse) is generated in the area where the next synchronization signal is generated, extracting only the synchronization signals at the correct time interval, and the phase of this extracted synchronization signal is input to the comparator.

If a small skew or a small dropout occurs and the synchronization signal is not extracted because it deviates from the window signal, a phase signal in the mJ state is input to the low bass filter as the output of the 1-phase comparator.

Therefore, 1 phase comparator, low pass filter, ? [A stable clock signal can be obtained because no disturbance is applied to the PLL circuit consisting of a pressure-controlled oscillator and a frequency divider.

Further, when the state changes in the special search mode and the output signal of the phase comparator output to the low-pass filter changes in a short time, the low-pass filter increases the gain and increases the change in the voltage output to the voltage controlled oscillator. Therefore, PLL
1v-pu is quickly drawn to a stable point.

In addition, if a large skew occurs during head switching or a long dropout occurs, the synchronization signal will not be extracted from the open signal extraction means for a long time, so the 1 selection means retains the normal time of the output of the position comparator The phase signal held for a long time is switched from the phase signal held for a long time to a phase signal held for a long time and input to the low-pass filter.

Therefore, since no disturbance is applied to the PLL loop,
A stable clock signal can be obtained.

Example DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below.

FIG. 1 is a block diagram of a clock signal regeneration circuit showing one embodiment of the present invention.

The same W) signal a from input terminal 1 is sent to the synchronous signal discrimination and extraction circuit (
DISCRI)2.

As shown in FIG. 2, the DISCRI 2 counts the time interval of the inputted ti14f word a using a fixed clock in the synchronization signal interval counting circuit (IT) 10, and calculates the DETI
The count data j counted at O is taken by the average opening signal interval data creation circuit (AVE). 11 The average data k is created at VC, and the window generation circuit (WiNDO) In step 12, a quindo signal is created, and as shown in the waveform diagram of FIG. Only a phase comparator output switching signal generation circuit (SELA
) 3 and one input terminal of the phase comparator (PC) 4.

5ELA 3 is a phase signal d and a phase signal e of the output of PC4, which will be described later, according to the time interval at which the output synchronization signal is extracted.
A switching signal fk for switching the phase comparator is generated and output to the phase comparator output selector switch (SWA) 5, as shown in FIG.
The SWA 5 switches the phase signal d and the phase signal e of the PC 4 according to the switching signal f, and outputs it to the low pass filter (LPF) 6 as the 5WA output signal g.

The LPF output signal of LPF 6 is a voltage controlled oscillator (VC
O) 7, the VCO 7 generates a clock signal i5c of r=frequency according to the input and outputs it from the output terminal 9, and the clock signal i is input to the frequency divider 8 (n is a positive integer). The frequency-divided signal C divided by /n is sent to PC4.
is input to the other input terminal.

For PC4, as shown in Fig.
A) 21 and the phase ratio V, which maintains the output for a long period of time (K
B) Consists of 22, PCA 21, PCB
22 both input the output quantity L1 signal and the frequency division signal C,
As shown in No. 64, a trapezoidal wave is formed from the frequency-divided signal C,
Output image 1 (+4 signal has already been sampled and held) A normal phase signal d and a long-term 1711 phase signal ek are output to SWA 5, respectively.

Furthermore, as shown in FIG. 4, the LPF 6 is composed of an active filter, and is
A switching signal generation circuit (SELB) 1 according to the output signal g
7 creates a switching signal m for the resistance changeover switch (SWB) 15, and SX'B 16 creates the resistance (R+) 14 and the resistance (R,
) 15cR,>R, ), and when the output signal g suddenly changes, the resistance (R,) 15 'k r!
Select and increase the active fill gain to output LPF (
g'ij" h k is increasing.

In Fig. 4, 18 is a capacitor, 19 is a resistor (R1
), 20 is an operational amplifier.

With the above configuration, if a small skew or small dropout occurs, the synchronization signal that is out of the window will not be output in DISCRI 2, and since PC4 has an output holding function, no disturbance will be given to the PLL loop. Therefore, the PLL output (clock signal fi
) Vi is output stably.

Furthermore, when the state is changed in the special search mode, the output of the PC 4 changes in a short period of time regardless of whether the synchronizing signal a is within the window, so it is necessary to quickly bring it to a stable point. This is realized by increasing the output signal to the VCO 7 by increasing the active gain of the H, LPF 6.

Furthermore, if a large skew occurs or a large dropout occurs during head switching, and the synchronization signal is not extracted from DISCRI 2 for a long period of time, the output of SWA 5 is changed by 5ELA3, and the holding function is changed from the normal PCA21 phase signal d to the holding function for a long period of time. By switching to the phase signal e of the PCB 22, no disturbance is applied to the PLL tv-de, and the PLL output (clock signal i)
is produced stably.

In this way, even when skew or dropout occurs, or when a special search mode is entered, a stable PLL output can be obtained with fast pull-in.

A bold effect can be obtained by using it in a signal processing circuit such as a VTR.

Advantages of the Invention According to the present invention, by extracting only synchronization signals at correct time intervals using the same 1gl signal extraction means, 4Gl signal can be extracted even when a small skew or a small dropout occurs.
Since no disturbance is caused to the PLL loop, a stable PLL output (clock signal) can be obtained. In addition, when the output signal of the phase comparator changes in a short period of time, such as during special search mode, by increasing the response speed by changing to the gain of the low-pass filter, the speed < PLL
tI/-deo can be stabilized. Furthermore, if a large skew or large dropout occurs, the PLL/L
Since no disturbance is applied to the '- loop, a stable PLL output can be obtained. In this way, a stable PLL output can be obtained with fast pull-in, and great effects can be obtained by using it in a signal processing circuit such as a VTR.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a clock signal regeneration circuit showing an embodiment of the present invention, FIG. 2 is a block diagram of a synchronization signal discrimination and extraction circuit shown in FIG. 1, and FIG. 3 is a block diagram of a phase comparator shown in FIG. 1. Figure 4 is a block diagram of the low-pass filter in Figure 1,
Figure 5 is a waveform diagram of the main parts of the clock signal regeneration circuit in Figure 1;
FIG. 6 is a waveform diagram of the phase comparator of FIG. 3. l...Input terminal, 2...Synchronization signal discrimination extraction circuit, 3
. . . Phase comparator output switching signal generation circuit, 4 . . Phase comparator, 5 . . . Phase comparison output switching switch, 6.
...p-pass filter, 7...voltage controlled oscillator, 8.
... layer frequency divider, 9 ... output terminal, 10 ... synchronization signal interval counting circuit, 11 ... average synchronization signal interval data creation circuit, 12 ... window generation circuit, 13 ... gate circuit %14...Resistance, 15...Resistance, 16...
Resistance selection switch, 17... switching signal creation circuit,
18... Capacitor, 19... Resistor, 20... Operational amplifier, 21... Phase comparator, 22... Phase comparator, 31. . Synchronization signal, b... Output synchronization signal, C... Frequency division signal,
d. e...Phase signal, f...Switching signal 1g...SWA
Output signal, h...LPF output signal, i...clock signal, j.-tt number data, k...average data,!・
...Window signal, m...Switching signal.

Claims (1)

[Claims] 1. A voltage controlled oscillator that outputs a clock signal with a frequency according to the input level, and a frequency divider that receives the clock signal, divides the frequency of this clock signal by 1/n (n is a positive integer), and outputs the divided clock signal. input a synchronization signal, count the synchronization signal intervals in fixed clock units based on this synchronization signal, average the counted synchronization signal intervals, and calculate the time period in which the next synchronization signal will occur based on this average data. generates a window signal of
A synchronizing signal extracting means uses this window signal as a gate signal to extract and output only synchronizing signals at correct time intervals, and a synchronizing signal outputted from the synchronizing signal extracting means and a clock signal frequency-divided by the frequency divider. a phase comparator that compares the phases of the synchronization signal and the clock signal, and outputs a phase signal whose output is held for a normal time and a phase signal whose output is held for a long time; selection means for inputting the output synchronization signal and selecting and outputting two phase signals of the output of the phase comparator according to the time interval at which the synchronization signal is extracted; and the phase selected by the selection means. A clock signal regeneration circuit comprising: a low-pass filter that inputs a phase signal of a comparator, changes gain when the phase signal suddenly changes, and outputs the gain to the voltage-controlled oscillator.