JPH039615A - Phase locked loop type oscillation circuit - Google Patents

Abstract

PURPOSE:To accelerate a response when skew distortion occurs and to stabilize an oscillation frequency by outputting a discrimination signal representing the fact that no synchronizing signal is inputted to a phase comparator, and stopping the frequency division operation of a frequency division circuit for a while until the next synchronizing signal is inputted. CONSTITUTION:A discrimination circuit 9 inputs the detecting pulse of a pulse generation circuit 8, and discriminates the presence/absence of a horizontal synchronizing signal with the timing of the detecting pulse. The discrimination signal representing the absence of the horizontal synchronizing signal is outputted to a sample and hold circuit 10 and a counter control circuit 11 with that timing. The horizontal synchronizing signal is also inputted to a sample and hold circuit 10, and the sample and hold circuit 10 outputs a hold instruction signal that goes to 'H' when, for example, the discrimination signal is inputted, and goes to 'L' when a prescribed number of horizontal signals are inputted afterwards to a sample and hold circuit 4.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a phase-locked oscillator circuit, and particularly to a magnetic recording/reproducing device that quickly responds to changes in period due to skew distortion. Related to phase-locked oscillator circuits.

(Prior Art) Generally, a phase-locked oscillator circuit has a configuration in which the output of a phase comparator is given to a voltage-controlled oscillator via a low-pass filter, and the output of the voltage-controlled oscillator is fed back to the phase comparator (phase-locked loop). A predetermined frequency signal is obtained by performing automatic frequency control. This phase-locked oscillation circuit is applied to various circuits, such as magnetic recording and reproducing devices (
In a VTR (hereinafter also referred to as a VTR), it is employed as a means for generating a signal of a predetermined frequency synchronized with a synchronization signal in a reproduced signal.

That is, the phase comparator constantly compares the phase of the horizontal homogeneous signal obtained from the reproduced video signal and the feedback signal input from the voltage controlled oscillator via the frequency divider. The output voltage of the phase comparator generated by this phase difference is applied to the voltage controlled oscillator via a low-pass filter, and becomes a control voltage for controlling the voltage controlled oscillator. With this control voltage,
The frequency of the output signal of the voltage controlled oscillator changes so that the frequency of the feedback signal and the frequency of the horizontal synchronization signal match. Since the output of the voltage controlled oscillator is divided by, for example, M by a frequency divider and given to the phase comparator, the frequency of the signal output from the voltage controlled oscillator is M times the frequency of the horizontal synchronizing signal.

By the way, in a helical scan type VTR, normally,
Tracks are formed on the tape at an angle, with one track per track.
The video signal for one field is recorded. therefore,
The frequency shift of the horizontal synchronization signal included in the reproduced video signal is
It is determined by the accuracy of the scanning speed of the video head, which is less than 1% for boat fishing. However, in a helical scan type VTR, recording and playback are normally performed using two or more video heads, and at the switching point of the video heads, that is, when the video head switches to the next track, the reproduced image Skew distortion occurs in which the signal νj becomes discontinuous. Therefore, the time from the horizontal synchronization signal immediately before the switching point to the horizontal synchronization signal immediately after the switching point may deviate significantly from the period of the horizontal synchronization signal. Therefore, in the phase-locked oscillator circuit of a conventional VTR, the bandwidth of the low-pass filter is widened ((natural angular frequency ω
By reducing n), it is possible to quickly respond to changes in the frequency of the input synchronization signal.

However, if the response characteristics of the phase-locked loop are made faster, the stability against noise such as disturbance becomes worse, and the oscillation frequency becomes unstable due to the noise. Conventionally, a relatively small frequency division ratio (low oscillation frequency) was required, and high oscillation frequency stability (oscillation frequency jitter) was not required, so these drawbacks were not particularly problematic. did not become.

However, in recent years, methods have been adopted in which arithmetic processing (correlation processing, etc.) is performed on each pixel in the time axis direction to separate the luminance signal and the color signal, which improves response characteristics when skew distortion occurs. Increasingly, there is a growing demand for both high and stable frequency characteristics.

(Problem to be Solved by the Invention) As described above, in the conventional phase-locked oscillator circuit described above, there is a problem that the frequency characteristics deteriorate because it is necessary to speed up the response when skew distortion occurs. was there.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a phase-locked oscillation circuit that can speed up the response when skew distortion occurs and improve the stability of the oscillation frequency.

[Structure of the Invention] (Means for Solving the Problems) A phase synchronized oscillation circuit according to the present invention compares the phase of a synchronization signal obtained from a reproduced video signal from a video head with the phase of a feedback signal, and calculates the phase difference. a phase comparator that outputs an error output based on the error output, a filter that passes only a predetermined frequency component of the error output, a voltage controlled oscillator that outputs a signal with a frequency based on the output of this filter, and an output signal of this voltage controlled oscillator. a frequency dividing circuit that divides the frequency and outputs a feedback signal to the phase comparator; a pulse generating circuit that generates a detection pulse at a timing based on the output of the frequency dividing circuit; a discrimination circuit that outputs a 1 discrimination signal indicating that the periodic signal is not input to the device;
a sample hold circuit that holds the output of the filter for a predetermined period of time at the generation timing of the discrimination signal and supplies it to the voltage controlled oscillator; and a counter control circuit that stops the frequency dividing operation of the frequency dividing circuit.

(Function) In the present invention, when the shift in the period of the synchronization signal obtained from the reproduced video signal exceeds the allowable range based on the width of the detection pulse, the discrimination circuit outputs the discrimination signal. At this point, the phase comparator is outputting the error output before the period shifts,
This error output is held in a sample hold circuit and given to a voltage controlled oscillator. Therefore, the voltage controlled oscillator outputs a signal with a period based on the period of the stable synchronization signal to the frequency dividing circuit. By the counter control circuit,
The frequency division operation of the frequency divider circuit is stopped from the input of the discrimination signal until the next synchronization signal is input, and the phase of the output of the frequency divider circuit is synchronized with the next stable period input to the phase comparator. Matches the phase of the signal.

In other words, even if the period of the synchronization signal deviates significantly, the re-entrainment of the phase-locked loop is performed in a short time.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. FIG. 1 is a block diagram showing an embodiment of a phase-locked oscillation circuit according to the present invention.

A horizontal synchronizing signal separated from the reproduced video signal is input to the input terminal 1. The phase comparator 2 receives this horizontal synchronizing signal and the feedback signal from the frequency dividing circuit 7 as input. The phase comparator 2 compares the phases of the horizontal synchronizing signal and the feedback signal, and outputs an error output based on the phase difference to the filter 3. The filter 3 passes only a predetermined frequency component of the error output of the phase comparator 2 and outputs it to the sample hold circuit 4. The sample hold circuit 4 is a sample hold control circuit 1 which will be described later.
When the hold instruction signal from 0 is L°, the interrogation state is entered, and when the hold instruction signal becomes “H”, the signal passing through the filter 3 is held.The output of the sample and hold circuit 4 is output from the voltage controlled oscillator (hereinafter referred to as vC○) 5. The VCO 5 is composed of, for example, an RC oscillator, an LC oscillator, or a crystal oscillator, and outputs a signal with a frequency corresponding to the output voltage of the sample bold circuit 4. The output of the VCO 5 is output to the output terminal 6 and also to the frequency divider circuit 7.

For example, the frequency dividing circuit 7 divides the output of the VCO 5 to 1/N by counting N outputs of the VCO 5 and outputting one pulse, and uses the divided output as a feedback signal to phase out the output of the VCO 5. The signal is outputted to the comparator 2 and also supplied to the pulse generation circuit 8.

Note that the frequency dividing circuit 7 is controlled by a counter control signal from a counter control circuit 11, which will be described later. The pulse generating circuit 8 generates a detection pulse of a predetermined width including the falling timing of the output pulse of the frequency dividing circuit 7.

On the other hand, the horizontal synchronizing signal from the input terminal 1 is also input to the discrimination circuit 9. The determination circuit 9 inputs the detection pulse of the pulse generation circuit 8, determines the presence or absence of the horizontal synchronization signal at the timing of the detection pulse, and samples and holds the determination signal indicating the absence of the horizontal synchronization signal at this timing to the sample-hold control circuit 1.
0 and is output to the counter control circuit 11.

A horizontal synchronization signal is also input to the sample and hold control circuit 10, and the sample and hold control circuit 10, for example, becomes 'H' when a discrimination signal is input, and then a predetermined number of horizontal synchronization signals are input. By “L 11
A hold instruction signal is output to the sample hold circuit 4.

The horizontal synchronization signal and the discrimination signal are also input to the counter control circuit 11, and the counter control signal is generated and given to the frequency dividing circuit 7 at the timing of the first horizontal synchronization signal after the input of the discrimination signal. .

The frequency dividing circuit 7 is configured to start a new counting operation (frequency dividing operation) when a counter control signal is input.

Note that the hold instruction signal becomes "L" after the change in the frequency division output of the frequency division circuit 7 due to the counter control signal returns to a steady state.
Therefore, the sample bold circuit 4 holds the output of the filter 3 until the transition period of the output state of the frequency-divided output ends.

Further, the phase comparator 2 may be inputted with a horizontal synchronizing signal frequency-divided by a 1/M frequency dividing circuit (not shown). In this case, the output frequency of VCO5 is (N/M)fil (
fH is the horizontal synchronization frequency).Next, the operation of the phase synchronization type oscillator circuit configured as described above will be explained with reference to the timing chart of FIG. Figure 2(a) is
The horizontal synchronization signal input to input terminal 1 is shown in Figure 2 (
b) shows the output of the frequency dividing circuit 7, FIG. 2(C) shows the detection pulse, FIG. 2(d) shows the discrimination signal, and FIG.
2(e) shows a counter control signal, and FIG. 2(f) shows a hold instruction signal.

Now, it is assumed that the horizontal period (63.5 μs) of a reproduced video signal obtained from a video head (not shown) is stable. A horizontal synchronizing signal is input to the phase comparator 2, and
The output of the VCO 5 is divided into 1/N by a frequency dividing circuit 7 and input. A phase comparator 2 compares the phases of these inputs, and provides an error output based on the phase difference to a VCO 5 via a filter 3 and a sample-and-hold circuit 4. As a result, a signal having a frequency N times the horizontal frequency f11 is output from the VCO 5 to the output terminal 7.

Now, when the frequency division ratio N of the frequency divider circuit 7 is 1 and the horizontal period is stable, the output of the frequency divider circuit 7 falls at the falling edge of the horizontal synchronization signal as shown in FIG. ), the pulses shown in (b) are obtained. This frequency-divided output is also given to the pulse generation circuit 8. The pulse generating circuit 8 generates detection pulses that rise and fall at timings before and after the falling edge of the frequency-divided output.

This detection pulse is input to the discrimination circuit 9, and the discrimination circuit 9 detects the presence or absence of a falling edge of the horizontal synchronizing signal at the timing of this detection pulse. Now, when the period of the horizontal synchronization signal is 63.5 μs, the horizontal synchronization signal is detected at the timing of the detection pulse, and the discrimination circuit 9 does not output a discrimination signal. For this reason, the sample hold control circuit 1
The hold instruction signal from 0 is "yes", and the sample hold circuit 4 is in a conductive state. Therefore, in this case, the VCO 5 outputs a stable signal with a period of 63.5 μs.

Now, due to skew distortion, etc., the period of the horizontal synchronization signal becomes 7, as shown in the third horizontal synchronization signal A shown in Fig. 2(a).
When it changes to 0 μs, the discrimination circuit 9 detects that there is no falling edge of the horizontal synchronizing signal at the timing of the detection pulse (FIG. 2(a)).

(C)), and outputs the 1 discrimination signal shown in FIG. 2(d). This discrimination signal is applied to the sample and hold control circuit 10, and the sample and hold υ control circuit 10 outputs a hold instruction signal of "H". As a result, the sample hold circuit 4 holds the filter output from the filter 3. At this point, the error output output from the phase comparator 2 has not changed, and the sample hold circuit 4 holds the error output before the change in the horizontal period and supplies it to the VCO 5.

On the other hand, the discrimination signal is also given to the counter control circuit 11,
The counter control circuit 11 generates a counter control signal at the timing of the first horizontal synchronizing signal A after inputting the discrimination signal and supplies it to the frequency divider circuit 7 (see FIG. 2(e)). 7 starts the frequency dividing operation anew at the timing of the horizontal synchronizing signal A. ■ The output of 005 is a signal with a period of 63.5 μs for the hold instruction signal of “G1”, and the frequency dividing circuit 7 63.5μs after the start of frequency division operation
Outputs a periodic signal. Therefore, the phase of the frequency division output after the frequency division operation starts is a stable horizontal period (63° 5μs).
The phase synchronization signal B matches the phase of the restored horizontal synchronization signal B, and the phase synchronization loop easily becomes locked.

In this manner, in this embodiment, regardless of the characteristics of the filter 3, even if the period of the horizontal synchronization signal deviates significantly, the phase-locked loop can be re-engaged in a short time.

Note that the sample and hold control circuit 10 may be configured with a monostable multivibrator, and the hold instruction signal may be generated at the input timing of the discrimination signal.

Further, the sample and hold circuit 4 is configured to determine the holding time of the output of the filter 3 by taking an OR condition between a predetermined time after inputting the discrimination signal and a time when dropout occurring in the tape head system is detected. It's okay. Furthermore, if noise is generated by playing a track recorded at an azimuth angle different from the azimuth angle of the playback head during special playback such as still image playback, a discrimination signal based on this noise is input. The sample and hold circuit 4 may be configured to perform the holding operation at a later predetermined time.

[Effects of the Invention] As explained above, according to the present invention, it is possible to re-entrain the phase-locked loop in a short time regardless of the characteristics of the filter, and the response characteristics to skew distortion etc. can be quickly determined. At the same time, stability against disturbances such as noise can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a phase-locked starting circuit according to the present invention, and FIG. 2 is a timing chart for explaining the operation of the embodiment. 1... Input terminal, 2... Phase comparator, 3... Filter. 4...Sample hold circuit, 5...VCO. 6... Output terminal, 7... Frequency dividing circuit, 8... Pulse generation circuit, 9... Discrimination circuit, 10... Sample hold control circuit, 11... Counter control circuit.

Claims (2)

[Claims] (1) A phase comparator that compares the phase of the synchronization signal obtained from the reproduced video signal from the video head with the phase of the feedback signal and outputs an error output based on the phase difference, and passes only a predetermined frequency component of the error output. a voltage controlled oscillator that outputs a signal with a frequency based on the output of this filter; a frequency dividing circuit that divides the output signal of this voltage controlled oscillator and outputs a feedback signal to the phase comparator; a pulse generation circuit that generates a detection pulse at a timing based on the output of the circuit; a discrimination circuit that outputs a discrimination signal indicating that a synchronization signal is not input to the phase comparator at the timing of the detection pulse; and the discrimination signal. a sample-and-hold circuit that holds the output of the filter for a predetermined period and supplies it to the voltage-controlled oscillator at the generation timing of the frequency divider; 1. A phase synchronized oscillator circuit comprising: a counter control circuit for stopping frequency division operation of the circuit. (2) The phase-locked oscillator circuit according to claim 1, wherein the sample and hold circuit holds the output of the filter for a preset period or a dropout detection period after inputting the discrimination signal. .