JPH08140058A - Skew correction device - Google Patents

Abstract

PURPOSE: To provide a device for inhibiting erroneous judgement from occuring even when clocks in a PLL circuit are used in a standard/non-standard judgement circuit at all times and also performing skew correction. CONSTITUTION: The loop of a phase comparator 3, a loop filter 4 and a VCO 5 phase synchronizes with horizontal synchronizing signals and the standard/non- standard judgement circuit monitors the frequency relation of the output of the VCO 5 and vertical synchronizing signals and judges standard and non-standard. VCO output and the output phase error output of the phase comparator 3 are added in an adder 31 and the horizontal synchronizing signals H are reproduced as added output L. Since the write reset pulses of a memory 33 are generated based on the L, fetching to the memory 33 is made possible corresponding to skew and then, read at a fixed cycle is performed by a read control circuit 35. PLL reset is not performed even when the skew is generated and the erroneous judgement is prevented from occuring in the judgement output of the standard/nonstandard judgement circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a skew correction device which occurs when a video head of a reproduction signal is switched in a video tape recorder (hereinafter referred to as VTR) or the like.

[0002]

2. Description of the Related Art Generally, in a VTR, a video signal is recorded on a magnetic tape by a plurality of rotary heads and reproduced, and the reproduced signal is reproduced when the signals of the plurality of rotary heads are switched.
Due to the elongation of the tape and the difference in the mounting position of the head,
The reproduction signal becomes discontinuous (skew occurs), and a delay in response to horizontal scanning pull-in appears on the screen of a television receiver (hereinafter referred to as a TV receiver). In order to reduce the distortion due to this skew, various skew correction methods have been proposed.

For example, in Japanese Patent Laid-Open No. 63-204894,
For the PLL circuit to which the horizontal synchronizing signal separated from the skewed video signal is supplied, the presence or absence of the skew of the horizontal synchronizing signal is detected, the PLL circuit is reset when the skew occurs, and the clock skew generated in the PLL circuit is detected. It prevents the fluctuation due to.

The devices disclosed in Japanese Patent Laid-Open Nos. 61-198887 and 61-198888 prevent the disturbance of operation due to dropout by controlling the write address to the time axis correction memory. There is.

Further, in the technique of Japanese Patent Laid-Open No. 62-239783, the residual phase error of the phase comparator of the write clock generating PLL circuit that follows the synchronizing signal included in the reproduced signal is stored, and it is stored before the one revolution of the rotary head. The current phase error is calculated, the oscillation phase of the PLL circuit is changed, and high frequency components such as impact jitter are tracked.

Although the techniques of the above-mentioned JP-A-61-1198887, JP-A-61-198888 and JP-A-62-239783 control writing / reading of the memory, switching of the rotary head during reproduction of the VTR is performed. It does not take measures against the skew that sometimes occurs.

FIG. 6 shows an outline of a conventional skew correction circuit. The reproduction luminance signal is input from the input terminal 1 to the horizontal sync separation circuit 2. The horizontal sync signal separated by the horizontal sync separation circuit 2 is input to a phase comparator 3 which constitutes a phase locked loop (PLL). The phase comparator 32 outputs a phase error between the horizontal synchronizing signal and the frequency division output from the frequency divider 6, and this phase error is supplied to the control terminal of the voltage controlled oscillator (VCO) 5 via the loop filter 4. To be done.
The clock generated by the VCO 5 is supplied to the frequency divider 6,
The frequency is divided here and is input to the phase comparator 3 as a feedback signal.

The reproduced luminance signal from the input terminal 1 is converted into a digital amount by a digital / analog (A / D) converter 7 and then written in the memory 8. The output of the frequency divider 6 is decoded by the decoder 9, and the address initialization pulse for writing in the memory 8 is obtained from this decoder 9. Further, in order to initialize the frequency divider 6 at the timing of the horizontal synchronizing signal when a skew occurs, a window pulse is again obtained from the decoder 9 and supplied to the gate circuit 10. When skew occurs, a pulse is generated from the gate circuit 10 and the frequency divider 6 is reset.

On the other hand, the read address initialization pulse is
The clock from the VCO 5 is frequency-divided by the frequency divider 11 and the coefficient value thereof is decoded by the decoder 12 to be obtained as a pulse having a constant period and supplied to the memory 8. Although not shown, the A / D converter 7 and the memory 8 are
It is driven by the output clock from the VCO 5.

FIG. 7 is a diagram shown for explaining the outline of the operation. FIG. 7A is a diagram showing an image of the reproduction luminance signal (input video) reproduced by the VTR in the horizontal and vertical directions. The step of the video signal before vertical synchronization (V) indicates the skew of the reproduction signal. FIG. 7B shows an image of the output video from the memory 8. FIG. 8 shows a timing example of the skew occurrence portion. FIG. 8 shows the signal waveform of each part of FIG. The frequency divider 6 counts the output clock of the VCO 5, and the decoder 9 generates a write reset pulse WR for the memory 8. When there is a skew, the horizontal synchronizing signal H passes through the gate circuit 10, a reset pulse is generated, and the frequency divider 6 is reset. This causes the feedback signal to be phase aligned with the horizontal sync signal. That is, synchronous pull-in is performed.

As a result, when skew occurs,
The disturbance of the clock from the VCO 5 does not occur and a continuous video signal can be obtained. Although the skew can be corrected by the above conventional method, when the nonstandard signal determination is performed by observing the frequency ratio of the vertical synchronizing signal to the horizontal synchronizing signal using the clock generated here, Due to the skew reset, a situation occurs in which the detection and determination cannot be performed. The non-standard judgment is 2 when the horizontal sync signal is NTSC during the vertical sync interval.
This is performed by detecting whether or not there are 62.5 pieces.

FIG. 9 shows an example of the configuration of the nonstandard detection determination circuit. The clock from the VCO 5 which is phase-synchronized with the horizontal synchronizing signal is counted by the counter 21 which circulates in the cycle of the vertical synchronizing signal. The count output of the counter 21 is decoded by the decoder 22, and the decoded output is a gate inhibition pulse having an error of about ± 0.05% of the vertical period.
That is, the gate inhibit pulse has a vertical period = (clock 9
10 × 262.5 ± α), and α = approximately ± 0.05%. This gate inhibition pulse is input to the gate circuit 23. The gate circuit 23 gates the vertical synchronizing signal V with the gate inhibit pulse. At this time, for example, VTR
When CUE (fast forward reproduction) or REV (rewind reproduction) is performed, the ratio of the vertical synchronizing signal to the horizontal synchronizing signal becomes other than 262.5, a non-standard signal detection pulse is output from the gate circuit 23, and the counter 21 is initialized. At the same time, the decision unit 24 obtains a decision output indicating that the signal is a non-standard signal.

For this determination, the clock needs to be 910 in one horizontal section, for example, NTSC. When skew occurs and the PLL is reset, this 910/1
The relationship of the horizontal lines is broken and V / H = 262.5
Even if the standard signal is a non-standard signal, it malfunctions.

For example, when the skew amount in FIG.
sec. 1.5 μsec at point b. , Then
The measurement result of the vertical period from the point V (c) to V (d) is smaller than the specified value by 1.5 μsec as compared with the case where there is no skew. Therefore, the non-standard detection determination circuit obtains an erroneous determination output that the non-standard signal is input.

[0015]

As described above, in the conventional skew correction device, since the horizontal synchronization PLL circuit is reset when a skew occurs, the clock generated in this PLL circuit is used to generate a non-standard signal. There is a problem that the judgment cannot be made.

Therefore, it is an object of the present invention to provide a skew correction device which prevents an erroneous determination even if the clock generated in the PLL circuit is always used in the standard / non-standard determination circuit.

[0017]

According to the present invention, the PLL circuit is not reset when a skew occurs, and the normal PL
Although it becomes the response of the L circuit, the write reset of the skew correction memory is determined by adding the phase comparison error information to the PLL oscillation phase information.

Specifically, the present invention relates to a phase comparator and V
A PLL circuit for phase-locking oscillation to a horizontal synchronizing signal synchronously separated from a video signal including CO, a phase error between the oscillation phase of the VCO and the output of the phase comparator, and a constant phase with the horizontal synchronizing signal. A phase generator for generating a signal having a relation, a memory for writing the video signal, a decoder for generating a pulse for initializing a write address to the memory by a signal from an output of the phase generator, and a previous write Using the read control circuit for generating the read reset pulse of the first term memory, which resets the read address at a constant period which is the average period of the address initialization pulse, and the n-fold clock of the first term horizontal frequency from the VCO, Measure the vertical sync cycle that is sync-separated from the video signal, and check if the frequency ratio of the horizontal sync frequency to the vertical sync frequency is within the specified value. To detect whether the outside, year video signal and a non-standard signal determination circuit for determining whether the standard signal or a non-standard signal.

[0019]

By the above means, the skip operation for the memory at the time of skew occurrence can be obtained, and the oscillation clock is, for example, NT because the PLL circuit is not reset.
In the case of SC signal input, the relationship of 910 lines / horizontal line is always maintained, so no problem occurs even if the standard / non-standard determination is always performed.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The frequency divider 6 described in FIG. 6 is included in the VCO 5. The horizontal synchronizing signal and the phase information generated by the VCO 5 and divided in frequency are compared in phase by the phase comparator 3. The phase difference information output from the phase comparator 3 is passed through the loop filter 4 and the VCO 5
It is added to the control terminal of.

There is no disturbance such as resetting the PLL circuit. The output K of the VCO 5 and the output I of the phase comparator 3 are input to the adder 31 and added. The addition output L of the adder 31 is decoded by the decoder 32. The decoder 32 generates an address initialization pulse for writing in the memory 33. As a result, the digital video signal from the input terminal 34 is written in the memory 33.

The read address initialization pulse for the memory 33 has the same cycle as the average cycle of the horizontal synchronizing signal, and is generated by the read control circuit 35.
Is supplied to This may be a method in which the response of the PLL circuit is limited to the low frequency range.

The standard / non-standard decision circuit is the circuit itself shown in FIG. That is, the output clock (frequency = n × fH) having a frequency n times the horizontal frequency from the VCO 5 is
It is counted by the counter 21 which circulates in the cycle of the vertical synchronizing signal. The count output of the counter 21 is decoded by the decoder 22, and the decoded output is ± 0.05% of the vertical cycle.
This is a gate-inhibited pulse with a position error. This gate inhibition pulse is input to the gate circuit 23. Gate circuit 23
Then, the vertical synchronizing signal V is gated by the gate prohibiting pulse. At this time, for example, VTR CUE (fast forward playback)
Or REV (rewind reproduction), the ratio of the vertical synchronizing signal to the horizontal synchronizing signal becomes other than 262.5, and the gate circuit 23
A non-standard signal detection pulse is output from the counter, the counter 21 is initialized, and the judgment device 24 obtains a judgment output indicating that the signal is a non-standard signal.

FIG. 2 shows an outline of the skew correction operation. Here, the signals of the respective parts in FIG. 1 are shown. Similarly, the digital video signal (input) is shown by horizontal / vertical time. This signal has a signal phase discontinuous skew due to the switching of the rotary heads as described above before the vertical blanking. The horizontal synchronizing signal phase is indicated by H in the vertical direction, and K is indicated by the output phase of the VCO 5. The phase difference between the phase information H and K is obtained by the phase comparator 3, and the phase error is I. On the contrary, the sum of the oscillation phase information K of the VCO 5 and the phase error I is H. This H
(= Horizontal synchronization) is reproduced as the output phase information L of the adder 31. The decoder 32 decodes this phase information L to generate a write reset pulse, and the memory 33
The timing to write the digital video signal to is determined. Therefore, the writing to the memory 33 coincides with the horizontal synchronizing phase of the video signal on the input side. Therefore, if the reading from the memory 33 is performed at a constant cycle, the signal will be a skew-corrected signal as shown in the output video signal of FIG. Can be read.

FIG. 3 is a timing chart showing the operation of the above circuit. When the horizontal synchronizing signal H arrives at a constant phase with respect to the oscillation phase information K of the VCO 5, the phase error information I obtained from the phase comparator 3 does not change.
However, when a skew occurs, I changes greatly, the output L of the adder 31 is also converted accordingly, and the write timing to the memory 33 also matches the horizontal synchronizing signal. WR
Is a write reset pulse for the memory 33, and RR is a read reset pulse for the memory 33.

The present invention is not limited to the above embodiment. FIG. 3 is an example of a skew correction device composed of a digital circuit. In this embodiment, a FIFO memory is used as the skew correction memory, and if the memory capacity is large, it can operate as a time axis correction device.

The horizontal synchronizing signal from the input terminal 101 is supplied to the sequencer 111 of the digital PLL circuit 102. The sequencer 111 operates with the clock CK from the fixed frequency oscillator 103, and has a pulse HP1 for each horizontal line phase-synchronized with the horizontal synchronization signal, and a pulse H sent from this pulse HP1.
Generate P2. The pulse HP1 is set so as to be generated by being sent rather than the horizontal synchronizing signal. The PLL part is
Register 121, loop filter 123, adder 12
4 and a register 125. The register 121 constitutes a phase comparison unit. The drive pulse for the register 121 is the previous pulse HP1. The drive pulse for the loop filter 123 is the pulse HP2. The loop of the adder 124 and the register 125 is driven by the clock CK.

The output of the register 121 is the gate circuit 10.
4 is supplied to one input terminal. This gate circuit 104
The window pulse from the window circuit 105 is supplied to the other input terminal of the. Window circuit 105
Creates a wind pulse using the oscillation phase information of the VCO. The oscillation phase information of the VCO is input to the adder 106, where it is added to the output from the gate circuit 104. The output of the adder 106 is input to the blanking reset circuit 107. The blanking reset circuit 107 responds to the output of the adder 106 with F
A write reset pulse WR for initializing a write address for the IFO memory 108 and a horizontal blanking pulse WBL for stopping the gate of the write clock in the blanking period are generated and supplied to the FIFO memory 108. The gate circuit 109 stops supplying the clock CK to the memory 108 when the horizontal blanking pulse WBL becomes high level. Here, the cycle of the write reset pulse WR depends on the capacity of the memory 108. For example, if the memory capacity is a capacity of 4H (4 horizontal lines), it becomes a cycle of 3H.

The output of the adder 106 is the oscillation phase information and
Basically, since it is the sum of the phase error information and
The phase of the horizontal sync signal will be expressed. The reason why the window circuit 105 generates a window pulse to limit the timing of the addition operation is to prevent malfunction in the normal case and to limit the maximum skew correction amount.

As a result, in the FIFO memory 108,
The input digital video signal is corrected and written according to the skew. Since the amount of skew during reproduction of a normal VTR is about 1 to 2 μsec, the horizontal blanking time 1
It can be absorbed if the time is 1 μsec. In this circuit,
Horizontal blanking is generated, and a certain amount of the pattern portion is written / read to / from the memory 108 to correct the skew. Also, in this circuit, the circuit is operated using a fixed frequency clock. When the skew amount is large, the error is set to zero and added so that the amount of horizontal blanking generated in the blanking reset circuit 107 is not exceeded. In the FIFO memory 107, the video signal of the time portion in which the clock is driven is written in the memory cell.

FIG. 5 is a timing chart showing the operation of the above device. FIG. 5A shows no skew or small skew, FIG. 5B shows medium skew, and FIG.
Indicates the operation when the skew is large. FIG. 5 (a)
In case of, error addition is stopped, and in case of FIG. 5B, error addition is performed. As a result, the horizontal blanking pulse WBL
The writing start time of the picture part of the part changes. Figure 5
In the case of (c), the skew is large, and the horizontal ranking pulse WBL is prevented from disappearing when the error is added.

This is a basic matter when using the FIFO memory, but at the time of reading, it is not possible to judge how many pixels in the picture portion should be read in a certain horizontal line. For example, suppose that after writing 768 pixels in the m-th line, a skew occurs and the + 1-th line becomes 760 pixels, and the m + 2-th line becomes 768 pixels again. Since the number of read pixels is 768 pixels for each line, the positions of the pixels (patterns) in the read video signal are shifted in the horizontal direction. In order to prevent this, the above configuration operation is performed. Further, the reason why the FIFO memory is used is that there is an advantage that the control circuit can be simplified.

The data read from the memory 108 is
A fixed clock and timing pulse from the read control circuit 201 is given to the blanking reset circuit 202, and a read reset pulse RR having a constant cycle is supplied to the memory 108. Also, the blanking reset circuit 2
The read blanking pulse RBL is output from 02, and the clock supplied from the gate circuit 203 to the memory 108 is stopped during this pulse period.
On the other hand, during this period, the sync addition circuit 204 adds the horizontal sync signal to the read digital video signal and outputs the horizontal sync signal.

[0034]

As described above, according to the present invention, V
A clock that is n times the horizontal synchronizing signal frequency can be obtained while correcting the skew that occurs when the rotary head of the reproduction signal such as TR is switched, and the ratio of the horizontal synchronizing frequency and the vertical synchronizing frequency, which was impossible with the conventional method, is detected. Therefore, non-standard signal discrimination can always be performed, which is industrially effective.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a schematic diagram shown for explaining the operation of the circuit of FIG.

FIG. 3 is a timing chart shown to explain the operation of the circuit of FIG.

FIG. 4 is a diagram showing another embodiment of the present invention.

5 is a timing chart shown for explaining the operation of the circuit of FIG.

FIG. 6 is a diagram showing a conventional skew correction circuit.

FIG. 7 is a schematic diagram shown to explain the operation of the circuit of FIG.

8 is a timing chart shown to explain the operation of the circuit of FIG.

FIG. 9 is a diagram showing an example of a standard / non-standard decision circuit.

[Explanation of symbols]

3 ... Phase comparator, 4 ... Loop filter, 5 ... Voltage controlled oscillator (VCO), 31 ... Adder, 32 ... Decoder, 33
... memory, 35 ... read control circuit, 102 ... digital PLL circuit, 103 ... fixed frequency oscillator, 105 ... window circuit, 104 ... gate circuit, 107, 202 ... blanking reset circuit, 108 ... FIFO memory, 1
09, 203 ... Gate circuit, 201 ... Read control circuit, 204 ... Synchronization addition circuit.

Claims (3)

[Claims] 1. A phase locked loop circuit that includes a phase comparator and a voltage controlled oscillator and oscillates in phase synchronization with a horizontal synchronizing signal that is synchronously separated from an input video signal, oscillation phase information of the voltage controlled oscillator, and the phase. Phase generating means for adding the phase error information output from the comparator to generate a signal having a constant phase relationship with the horizontal synchronizing signal; storage means for writing the input video signal; and phase generating means. A decoder for generating an initialization pulse of a write address of the storage means by an output signal from the storage means and controlling a write timing of the storage means; Read control means for generating a read reset pulse for resetting the read address of the means; n horizontal frequency being force
By measuring the period of the vertical sync signal that is synchronously separated from the input video signal using a double clock, it is detected whether the frequency ratio of the horizontal sync frequency and the vertical sync frequency is within a specified value, and the input video signal is A skew correction device comprising standard / non-standard determination means for determining whether the signal is a standard signal or a non-standard signal. 2. A phase locked loop circuit which includes a phase comparator and a voltage controlled oscillator and oscillates in phase synchronization with a horizontal synchronizing signal which is synchronously separated from an input video signal, oscillation phase information of the voltage controlled oscillator and the phase. Phase addition means for adding the phase error information output from the comparator to generate a signal having a fixed phase relationship with the horizontal synchronization signal, and addition of the phase error information in the phase generation means for the horizontal synchronization signal. Means for further delaying, blanking generation means for decoding the output of the phase generation means to generate a blanking pulse corresponding to a horizontal blanking period, and writing of the input video signal in the horizontal blanking period. A memory means for reading and a means for adding a blanking synchronization signal to the output video signal read from the memory means. A skew correction device characterized by being provided. 3. A phase locked loop circuit which includes a phase comparator and a voltage controlled oscillator and oscillates in phase synchronization with a horizontal synchronizing signal synchronously separated from an input video signal, oscillation phase information of the voltage controlled oscillator and the phase. Phase generation means for adding the phase error information output from the comparator to generate a signal having a constant phase relationship with the horizontal synchronization signal; and addition operation of the phase error information in the phase generation means for the horizontal synchronization. Means for delaying the signal, blanking generation means for decoding the output of the phase generation means to generate a blanking pulse corresponding to a horizontal blanking period, and writing of the input video signal in the horizontal blanking period Memory means for reading and writing, and a time smaller than the horizontal blanking pulse width based on the oscillation phase information of the voltage controlled oscillator. Window pulse generating means for generating a large window pulse, and the delayed addition operation information is gated by the window pulse, and the phase comparison error and the oscillation phase information for a large skew exceeding the video blanking interval. Skew correction apparatus comprising gate means for prohibiting addition of