JPS6379276A - Signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a stable PLL output by inputting an output of a phase comparator to a voltage controlled oscillator through an LPF, frequency-dividing its output to 1/n and inputting the result to a 2nd input of the phase comparator so as to inhibit the operation and applying reset/presetting based on a 1st input signal. CONSTITUTION:A reference signal (d) is inputted to a phase comparator PC2 from a terminal 1 and its output is inputted to a VCO4 through an LPF3. The output is fed to an output terminal 11 and inputted to a 1/n frequency divider 5. The comparator PC2 compares the signal (d) with the output signal (e) of the frequency divider 5, a produced error signal oscillates the VCO4 through an LPF3 and a phase-locked signal is outputted (11). On the other hand, the signal (d) is inputted to a switch SW7 via a time adjusting circuit DL6. A discontinuous signal is inputted to the control circuit 8 from a terminal 9, its output is inputted to the comparator PC2 to inhibit the operation of the PC2 for a prescribed time, the output is also inputted to the switch SW2 to switch the reset pulse to the frequency divider 5 into a signal from the DL6 for a prescribed period thereby resetting the frequency divider 5.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing circuit used in a PLL circuit of a video tape recorder (hereinafter abbreviated as VTR) or the like.

Conventional technology In digital signal processing circuits such as TBC of VTR,
A write pulse to a memory is generally created as follows. In other words, a reference signal obtained based on a horizontal synchronization signal or a burst signal is used to generate a reset pulse that resets the address of the memory, and is further phase-locked to the reference signal.
Hz) as a voltage controlled oscillator (abbreviated as VCO) of a PLL circuit.
This is generated by the clock and is used as the write clock to the memory.

Problems to be Solved by the Invention However, when playing back a VTR, the PLL having the above configuration is
When using a circuit, for example, when a large skinny occurs due to head switching, or in sections where heads are switched such as the head switching point in cue review during variable speed playback, discontinuity of the reference signal occurs, and the It takes a certain amount of time for the PLL circuit to be disturbed at the point of discontinuity and to return to a stable point. In order to shorten this time, it is possible to increase the response speed of the PLL, but there is a limit to this because increasing it too much has the negative effect of making it less susceptible to noise. In other words, after the discontinuity point of the reference signal, a certain period of time, for example, several H periods (H - horizontal scanning period), is required for the PLL circuit to stably draw in the signal, and the output of the PLL circuit during that time, that is, the write clock The output of vCO used for such purposes was not guaranteed.

Means for Solving the Problems The present invention passes the output of the phase comparator through a low-pass filter, inputs it to a voltage controlled oscillator, outputs the output of the voltage controlled 11 oscillator, and simultaneously converts the output to a 1/n frequency divider (n is an integer). ), and by inputting the output of the 1/n frequency divider to the second input of the phase comparator, a signal that is phase-locked with the first input signal input to the first input of the phase comparator is obtained. The generated PLL circuit prohibits the operation of the phase comparator for a predetermined period according to the information of the second input signal, and resets or resets the 1/n frequency divider during the predetermined period according to the information of the second input signal. The configuration is such that presetting is performed based on information of the first input signal.

Further, the first input signal is connected to the first input of the phase comparator and the first input signal to the first input signal of the phase comparator.
input to the switch, input the output of the phase comparator to the low-pass filter, input the output of the low-pass filter to the voltage controlled oscillator, output the output of the voltage controlled oscillator, and at the same time input the output to the 1/n frequency divider (n is an integer). and input the first output of the 1/n frequency divider to the other input of the phase comparator, 1/n
The second output of the frequency divider is inputted to the other input of the switch, the output of the switch resets or presets the l/n frequency divider, and the second input signal is inputted to the control circuit. The first output signal inhibits the operation of the phase comparator for a predetermined period, and the second output signal of the control circuit changes the output of switch 1 from the second output of the 1/n frequency divider to the first output signal.
The configuration is such that the input signal can be switched to the following input signal.

Operation According to the present invention, with the above-described configuration, even if the reference signal becomes discontinuous, no disturbance is applied to the PLL loop, so that a stable vCO output can be obtained.

Embodiment Hereinafter, an embodiment of the signal processing circuit of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of the present invention.

A reference signal formed based on the horizontal open XJI signal or burst signal is input from terminal l,
(abbreviated as c) is input to PO2. The output of PO2 is input to vCO4 through a low pass filter LPF3.

The output of vCO4 is sent to output terminal 11 and 1/n
It is output to the frequency divider 5. The output of 1/n frequency divider 5 is PO2
At the same time, it is input to the other input of the 1/n frequency divider 5 as a reset pulse through the switch SW7.

On the other hand, the reference signal is sent to SW7 through the time adjustment circuit DL6.

A discontinuous signal, which is a second input signal, is input to a terminal 9 and then input to a control circuit 8. The output of the control 8 circuit 8 is sent to PO2, which prohibits the operation of the PC 2 for a predetermined period and also switches SW7.
and switches the reset/reset pulse of the 1/n frequency divider to the signal from DL6 for a predetermined period.

In the signal processing circuit, for example, the signal from the output terminal 10 is
It is used as a memory address clear pulse, etc., and the signal from the output terminal 11 is used as a write clock, etc.

Next, the operation of the present invention will be explained based on the waveform diagrams of each part shown in FIGS. 2 to 4. First, FIG. 2 shows the response of a conventional PLL circuit.

Before and after the head switching signal (al), the reference signal (bl
is discontinuous (between d and d2), and the signals d2 and 1
When the phase of the output (02 of C1) of the /n circuit is compared, an error signal such as gl is generated. When this error signal is passed through LPF 3, it becomes a signal like (f), and based on this voltage, vCO oscillates, and eventually the signal (bl The output e of the 1/n circuit 5 operates in a phase-locked manner.

Here, f indicates a reset pulse. In this conventional example, it is shown that it takes about 10 hours for the PLL circuit to reach stability.

Next, the present invention will be explained with reference to FIG. A second signal, a discontinuous signal (al), is input to the control circuit 8.

The control circuit 8 detects the change point of the discontinuous signal and generates a signal (e) that prohibits the operation of T, Take, and PO2 for a certain period from that point.
Then, a signal ffl for selecting the T2 period reset pulse f is output. As a result, conventionally a large error signal g1 was generated by comparing the signals d2 and 02, but the signal t
Since the comparison is prohibited by el, the error signal g is not output.Furthermore, since the signal f2 based on the signal d2 is added to the reset pulse fd+ and the 1/n frequency divider circuit is reset, the signal d3 and Even if the phase is compared with 08, no phase error will occur.

Next, FIG. 4 shows an example when the period of the signal (C) becomes narrower at a discontinuous point.

As in Fig. 3, the error signal does not change in the interval T1, and based on the signal d2 (f2 pulse resets the frequency divider 5, the phase difference between d and 03 is compared at the next timing). Similar to FIG. 3, this does not occur.

Here, if the comparison signal (C1) and the reset pulse f are at the same timing, by sending the signal (C1) to the switch 7, the output of the 1/n frequency divider can be reduced to one system.

In addition, when the reference input signal 1 and the reset pulse (dl) have a predetermined time difference in a stable state of the PLL loop, it is necessary to provide a time adjustment circuit 6 to correct the time difference, but there is no need for correction. In this case, the time adjustment circuit 6 may be omitted. Also, the output signal (f) of the control circuit 8 is turned on from when the discontinuous signal ta+ is input, until the reset pulse f is output once. Also, the output signals tit and (e) of the control circuit 8 may be the same signal.

Also, due to the configuration of the 1/n frequency divider, the reset pulse (d
) may be a preset pulse, and SW
For example, PC 7 can be configured with a simple AND-OR gate.
, VCO 4, 1/n frequency divider 5, etc., can also be designed using conventional techniques, so detailed explanations will be omitted.

Effects of the Invention As is clear from the above description, the present invention allows the output of the phase comparator to pass through a low-pass filter, input it to the voltage controlled oscillator, and simultaneously output the output of the voltage controlled oscillator.
/n frequency divider (n is an integer) and by inputting the output of the 1/n frequency divider to the second input of the phase comparator,
A PLL circuit that generates a signal that is phase-locked with a first input signal that is input to a first input of a phase comparator,
According to the information of the input signal, the operation of the phase comparator is prohibited for a predetermined period of time, and the reset or preset of the 1/n frequency divider is set according to the information of the first input signal during the predetermined period of time according to the information of the second input signal. This is a signal processing circuit that is characterized by the fact that the PLL loop is stable even when the reference signal is discontinuous, which occurs when switching heads, and the PLL loop does not change.
It is possible to obtain an output, and great effects can be obtained by using it in a signal processing circuit such as a VTR.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the present invention, FIG. 2 is a waveform diagram of each part of the present invention, FIG. 3 is a waveform diagram of each part of the present invention, and FIG. 4 is a waveform diagram of each part of the present invention. 2... Phase comparator, 3... Low pass filter, 4... Voltage controlled oscillator, 5...
・1/n frequency divider, 6...Delay circuit, 7...
...Switch, 8...Control circuit.

Claims (15)

[Claims] (1) Pass the output of the phase comparator through a low-pass filter, input it to a voltage controlled oscillator, output the output of the voltage controlled oscillator, and simultaneously input it to a 1/n frequency divider (n is an integer), The PLL circuit generates a signal phase-locked to a first input signal input to a first input of the phase comparator by inputting an output of a frequency divider to a second input of the phase comparator. According to the information of the second input signal, the operation of the phase comparator is prohibited for a predetermined period, and the reset or preset of the 1/n frequency divider is prohibited for the predetermined period according to the information of the second input signal. A signal processing circuit characterized in that processing is performed based on information of a first input signal. (2) The signal processing circuit according to claim (1), wherein the first input signal is a signal obtained based on a horizontal synchronization signal of a video signal. (3) The first input signal is present in the video signal. The signal processing circuit according to claim 1, wherein the signal is obtained based on or based on the added burst signal. (4) The signal processing circuit according to claim (1), wherein the second input signal is a head switching signal. (5) The signal processing circuit according to claim (1), wherein the predetermined period is approximately one horizontal scanning section. (6) For a predetermined period, after the second input signal is input,
The signal processing circuit according to claim 1, wherein the period is a period until a reset or preset pulse is input to the 1/n frequency divider. (7) Connect the first input signal to the first input of the phase comparator and
, the output of the phase comparator is input to a low-pass filter, the output of the low-pass filter is input to a voltage controlled oscillator, and at the same time the output of the voltage controlled oscillator is output, a 1/n frequency divider (n is an integer), a first output of the 1/n frequency divider is input to the other input of the phase comparator, and a second output of the 1/n frequency divider is input to the other input of the switch. the 1/n frequency divider is reset or preset by the output of the switch;
A first output signal of the control circuit inhibits the operation of the phase comparator for a predetermined period, and a second output signal of the control circuit inhibits the output of the switch 1. from the second output of the 1/n frequency divider to the first
A signal processing circuit characterized by switching to an input signal. (8) The signal processing circuit according to claim (7), wherein the first output signal and the second output signal of the 1/n frequency divider are the same signal. (9) The signal processing circuit according to claim (7), wherein the first input signal is a signal obtained based on a horizontal synchronization signal of a video signal. (10) The signal according to claim (7), wherein the first input signal is a signal obtained based on a burst signal present in or added to the video signal. processing circuit. (11) The signal processing circuit according to claim (7), wherein the second input signal is a head switching signal. (12) The signal processing circuit according to claim (7), wherein the predetermined period is approximately one horizontal scanning section. (13) The signal processing circuit according to claim (7), wherein the first input signal is time-adjusted by a time adjustment circuit and then input to the switch. (14) The predetermined period is a period from when the second input signal is input to when the reset or preset pulse is input to the 1/n frequency divider. 7) The signal processing circuit described in section 7). (15) The signal processing circuit according to claim (7), wherein the first output signal and the second input signal of the control circuit are the same signal.