JPS6214900B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a head switching signal generation circuit for a VTR, and in particular to a system for digitally performing phase servo on a rotating drum supporting a plurality of heads based on clock pulses from a clock generation circuit. The present invention relates to a head switching signal generation circuit for sequentially switching the plurality of heads in a VTR.

The switching point of the output of the head is at a fixed position in a standardized VTR.
For example, the position is 7H±2H (H is the horizontal period) from the vertical synchronization signal. Therefore, in a normal helical scan type VTR, servo is performed during recording using the rotational phase of the rotating magnetic head and the vertical synchronization signal in the video signal being recorded, and this allows a predetermined position in the recording pattern to be A vertical synchronization signal is recorded at the position. Also, during playback, the servo circuit works in the same way and the above-mentioned 7H±2H is generated.
The switching point is located within the range of . However, in conventional VTRs that record one track and one field using a two-head system, for example, a monomulti is used to determine each of the two switching points, resulting in a large number of adjustments. In particular, when phase servo is performed by a digital method, the advantage of digital servo without adjustment is diminished by the above-mentioned adjustment.

Furthermore, in the phase servo that is commonly used at present, one pulse is generated with one revolution of the rotary head drum, and phase information is obtained from this, so this pulse signal is 30 Hz. Therefore, above 1
The clock pulse is counted down based on one pulse signal, and two clock pulses are counted down during one revolution of the head drum.
Two switching points must be created. However, according to such a method, the circuit configuration becomes extremely complicated. Furthermore, if the servo circuit does not include residual errors, the switching timing can be obtained by supplying the outputs of the clock signal generation circuits to the respective decoders, but if the servo circuit has residual errors, the switching point may be This means that it will deviate from 7H±2H before the vertical synchronization signal. To prevent this, the first method is to devise a phase servo system to eliminate the residual error, and the other is to reflect this error in the head switching timing without removing the residual error in the phase servo system. The second method is considered.

It is an object of the present invention to provide a head switching signal generation circuit that utilizes the features of the digital phase servo circuit using the second method described above and ensures that the switching point is always within a predetermined range even if there is a residual error. In a VTR in which a rotating drum supporting a plurality of heads is digitally phase servoed based on clock pulses from a clock generation circuit, servo control is performed from a phase detection counter used for the phase servo. This invention relates to a head switching signal generating circuit which obtains a phase error component and generates a signal for switching the plurality of heads using a timing signal based on this error component. Therefore, the switching point for head switching can follow the residual error and fall within a predetermined range without diminishing the advantage of non-adjustment of the digital phase servo, and with a relatively simple configuration.

The present invention provides a pulse generator 1 for detecting the rotation of a rotating drum 3 supporting first and second heads 4 and 5.
7, and a gate signal with a width corresponding to the phase difference between the output PGH of this pulse generator 17 and the reference signal VDL.
The present invention is applied to a VTR equipped with a phase detection counter 35 that counts clock pulses TF6 gated by the DPEB, and a control circuit that controls the rotational phase of the drum 3 based on the cyclic phase of the phase detection counter 35.

A circuit that forms the first timing signal (first pulse of MCOP) related to the phase of the output PGH of the pulse generator 17 (OR circuit 46 and flip-flop 47 in the monomulti 29 and head switching signal forming circuit 20 of the embodiment) , gate 48, and M-ary counter 49) are provided. This first timing signal determines the switching timing for one of the two rotation heads.

Furthermore, after the clock pulse TF6 is counted by the phase detection counter 35 based on the phase difference between the output PGH of the pulse generator 17 and the first reference signal VDL, the clock pulse TF6 is counted again in synchronization with the second reference signal REPG. The phase detection counter 35 detects the above clock.
A circuit (flip-flop 45, 30, gate 33, flip-flop 47, gate 48, M-ary counter 49, etc.) are provided. This second timing signal determines the switching timing for the other of the two-rotation heads.

Then, the switching signals for the first and second heads 4 and 5 are generated by the first and second timing signals.
The RFSW is formed by a flip-flop 30.

An embodiment in which the present invention is applied to a two-head type helical scan type VTR will be described below with reference to the drawings.

FIG. 1 is a plan view schematically showing this VTR, in which a magnetic tape 1 is wound helically around the outer peripheral surface of a head drum 3 by a pair of tape guides 2 while running. The magnetic tape 1 is supported by a head drum 3, and comes into sliding contact with a pair of video magnetic heads 4, 5 facing the outer surface of the drum 3 and a fixedly arranged control head 6. As a result, as shown in FIG. 2, the surface of the magnetic tape 1 has a video track 7 that is inclined at a predetermined angle with respect to the running direction of the tape, and a video track 7 that is located at the upper end in the width direction of the tape 1. control track 8
and an audio track 9 located at the lower end of the tape 1 in the width direction. This VCR
Since this is a two-head system, two video tracks 7 are recorded in one revolution of the head drum 3, or 1/30 seconds.
Therefore, the video track 7 will be formed at 60Hz. Further, a control signal 10 is formed on the control track 8 at a frequency of 30 Hz, that is, once the head drum 3 rotates once. Furthermore, a vertical synchronizing signal 11 is recorded near the end of the video track 7. This vertical synchronizing signal 11 must be formed within a certain range, for example within a range of 7H±2H, from the switching point of the heads 4 and 5, that is, the switching point during reproduction.

FIG. 3 shows the servo loop of the head drum 3 of this VTR. Therefore, feedback control is performed. Furthermore, as shown in Fig. 1, the motor 1
A magnet 16 is attached to the head drum 3 driven by the magnet 1.
A phase pulse generator 17 is fixedly arranged opposite to 6. The output of this generator 17 is compared with a reference signal supplied from a reference signal generation circuit 18 in a phase servo circuit 19, and is configured to be input to a drive amplifier 15.

Next, a detailed circuit configuration for this phase servo and switching of the video heads 4 and 5 will be explained with reference to FIG. The circuits shown in FIG. 4 are divided by dashed lines, including a reference signal generation circuit 18, a phase servo circuit 19, and a head switching circuit.
It is composed of an RFSW signal forming circuit 20.

First, the reference signal generation circuit 18 will be described.
This circuit 18 is equipped with a crystal resonator, and includes an oscillator 21 that generates a 3.58 MHz clock pulse, a quinary counter 22 and an octal counter 23, 2 that sequentially count down the clock pulses of the oscillator 21.
4. A counter group consisting of a hexadecimal counter 25. The clock pulse CP is taken out from the quinary counter 22, and the clock pulse CP is taken out from the octal counter 23.
From here, clock pulse TF6 and this pulse 2
Clock pulse TF, which is a 4-ary output with double the frequency
5 is taken out, and a clock pulse TF12 is taken out from the hexadecimal counter 25. Clock pulse TF6 is supplied to reference signal generation counter 26. The output of this counter 26 is sent to the decoder 2
7, the timing is detected and the clock pulses 2XVD and REPG are obtained. Clock pulse 2XVD is flip-flop 2
The clock pulse XVD is divided into 1/2 by 8.
It is becoming possible to obtain

Next, regarding the phase servo circuit 19, the monomulti 29 generates a pulse signal of a constant width using the output signal PGH of the phase pulse generator 17 as a trigger.
It causes PGHDL. Signal PGHDL is adapted to set flip-flop 30. This flip-flop 30 is reset at the fall of the output signal VDL of the delay counter 31. And flipflop 3
The output signal DPEB of 0 is supplied to the AND circuit 33 via the OR circuit 32.
is opened, and the clock pulse TF6 is supplied to the phase detection counter 35 via the OR circuit 34. The phase detection counter 35 is a 512-decimal system, and when there is no residual error in the phase, it counts 256 pulses of the clock signal TF6 during the period in which the output signal DPEB of the flip-flop 30 is "1". . Note that during recording, a signal VD/2 obtained by dividing the frequency of the synchronizing signal in the video signal by 1/2 is given to the counter 31, and during playback, the output signal XVD of the flip-flop 28 is given to the counter 31, and these are used as trigger pulses. counter 3
1 counts a predetermined number of clock pulses TF6 and delays the trigger pulse for a predetermined period.

Flip-flop 36 is flip-flop 30
The latch signal is activated by the rising edge of the output signal DPEB.
Generate FFL. When the latch signal FFL becomes "1", the flip-flop 37 is inverted in synchronization with the clock pulse TF12, and since the output signal PROTE of the flip-flop 37 is supplied to the reset terminals of the flip-flops 36 and 37, the clock signal TF12 is inverted. On the next pulse, flip-flop 37 is inverted. That is, the two flip-flops 36 and 37 form a signal PROTE having a pulse width corresponding to one period of the clock pulse TF12. This signal PROTE is
It is configured to open the AND circuit 38 and supply the clock pulse CP to the phase detection counter 35. This phase detection counter 35 is 512 as described above.
The clock pulse TF12 is configured as
It is designed to count 512 pulses of the clock signal CP.

The phase detection counter 35 detects the clock pulse CP.
The most significant digit of this counter 35 when counting 256 pieces
The MSD output DPC-8 is supplied to a reset terminal of a buffer counter 40 via an AND circuit 39. This counter 40 is a 512-decimal system and counts clock pulses CP. The output signal PR-8 of the counter 40 is supplied to the reset terminal of a flip-flop 43 via an AND circuit 41 and an OR circuit 42. The other input terminal of the AND circuit 41 is connected to the output terminal of the flip-flop 37 via an inverter 44, so that the AND circuit 41 is closed only while the output signal PROTE is "1". Further, the output DPC-8 of the phase detection counter 35 is directly supplied to another input terminal of the OR circuit 42. This is the signal DPC-8 that resets the counter 40 when the output of the counter 40 is "0".
This is to reset the flip-flop 43 as well. A clock pulse TF12 is also supplied to the set terminal of the flip-flop 43, which generates a pulse width modulated signal corresponding to the phase error including the residual error of the phase servo circuit.
DPPWM will be output from this flip-flop 43. This signal DPPWM is integrated and converted to a level signal, and then the speed servo circuit (third
(see figure) is superimposed on the speed error of the output.

Next, the head switching signal forming circuit 20 will be described. This circuit includes a flip-flop 45. Flip-flop 45 is decoder 27
It is configured to be set by the output signal REPG of the counter 35 and reset by the output signal DPC-8 of the counter 35. And the output of flip-flop 45
RDDPC passes through OR circuit 46 to flip-flop 4
7 is supplied. In addition, another one of the OR circuit 46
The two input terminals have the mono multi 29 output signal.
PGHDL is supplied. In other words, the head drum 3 rotates 1/2 and the pulse generator 17 outputs an output signal.
When PGH is generated, the head drum 3 is further rotated by 1/2 rotation by the output PGHDL of the monomulti 29 which delays this, and the pulse generator 17
When the magnet 16 is not detected, the flip-flop 47 is inverted by the output of the flip-flop 45 in conjunction with the output of the counter 35 DPC-8.

The output signal of flip-flop 47 controls the opening and closing of AND circuit 48, and when AND circuit 48 opens, clock pulse TF5 is supplied to M-ary counter 49 and delayed for a predetermined period. counter 4
The output MCOP of head 9 triggers a flip-flop 50 as a timing signal for head switching, and flip-flop 50 is configured to generate a switching signal for heads 4 and 5. The number of stages of this M-ary counter 49 and the clock pulse TF5 counted by this counter 49 are adjusted so that this counter 49 generates an output 7H±2H ahead of the vertical synchronization signal when there is no residual error in the phase servo. Frequency is set.

Next, the operation of the circuit having the above configuration will be explained with reference to time charts shown in FIGS. 5 and 6. It should be noted that the signal symbols in these figures represent the waveforms at points with corresponding symbols in the circuit in FIG. 4.

First, the operation of generating switching signals for the heads 4 and 5 will be explained with reference to FIG.
detects the magnet 16 and generates a pulse signal PGH. This pulse signal PGH is mono multi 2
9 for a predetermined time delay. mono multi 2
Since the output PGHDL of 9 is supplied to the flip-flop 47 through the OR circuit 46, the flip-flop 47 is inverted and opens the gate 48.
Therefore, the clock pulse TF5 is sent to the M-ary counter 49.
is supplied, and the counter 49 counts the number of pulses. When the counter 49 counts a predetermined number of pulses, it outputs a first timing signal.
MCOP changes from "1" to "0", which causes flip-flop 50 to invert and generate head switch signal RFSW.

Therefore, the head switching signal RFSW is a pulse signal.
After PGH is generated, it is generated with a delay of a period equal to the sum of the period in which the signal PGHDL is "1" and the period in which the output MCOP of the counter 49 is "1". Since the period in which the signal PGHDL is "1" and the period in which the signal MCOP is "1" are constant values unrelated to phase detection, the head switching signal RFSW changes in accordance with the phase error. In other words, if the phase detection signal PGH is generated with a delay,
As shown in FIG. 5B, the head switching signal RFSW is output with a delay corresponding to the delay of the pulse signal PGH.
occurs. In addition, when the phase detection signal PGH is leading, the pulse signal
A head switching signal is generated after an amount corresponding to the advance of PGH. Since the pulse signal PGH represents the vertical synchronization signal to be reproduced, the switching points of heads 4 and 5 will also shift in proportion to the error in the phase of the vertical synchronization signal. Signal for switching of 5
RFSW never deviates from the range of 7H±2H with respect to the vertical synchronization signal.

The above operation is based on the output signal of the phase pulse generator 17.
In the case where the head switching signal RFSW is directly generated by PGH, the head drum 3 is provided with only one magnet 16, and one pulse is generated from the generator 17 with one rotation of the head drum 3. It's just being done. So head drum 3
Head switching signal when rotates another 1/2 turn
RFSW is the output DPC-8 of the phase detection counter 35
I am trying to obtain it using .

That is, the gate 33 is opened while the output DPEB of the flip-flop 30, which is set by the output PGHDL of the monomulti 29 and reset by the output VDL of the delay counter 31, is "1".
The clock pulse TF6 is counted by the phase detection counter 35. The set signal PGHDL of the flip-flop 30 follows the servo phase error. However, since the reset signal VDL of the flip-flop 30 is obtained from the video signal during recording and from the output 2XVD of the decoder 27 during reproduction, it is independent of phase servo errors. Therefore, the period in which the signal DPEB is "1" expands or contracts depending on the phase servo error. 512 counter 3 when there is no phase error
5 is the clock pulse TF6 as shown in FIG. 5A.
256 clock pulses TF6 are counted during this period, but if there is a phase lag, the period in which the signal DPEB is "1" becomes shorter as shown in FIG. 5B, and the counter 35 can count 256 clock pulses TF6. If this is not possible and the phase is ahead, the period in which the signal DPEB is "1" becomes longer as shown in FIG. 5C, and the counter 35 counts more than 256 clock pulses TF6.

Flip-flop 30 is reset and
When gate 33 closes, the supply of clock pulse TF6 to counter 35 is cut off. Then, just before the head drum 3 makes another 1/2 rotation, the flip-flop 45 is set by the output pulse REPG from the decoder 27, and the output RODPC of the flip-flop 45 opens the gate 33 and supplies the clock pulse TF6 to the counter 35 again. . Since flip-flop 45 is reset by the output of counter 35, gate 33 remains open until counter 35 has counted 512 clock pulses TF6. Therefore, the section in which the gate 33 is open, that is, the signal RODPC
The period when is "1" expands or contracts according to the phase error. If there is no phase error, the counter 35 counts 256 clock pulses TF6 as shown in FIG. 5A, but if there is a phase lag, the counter 35 counts 256 clock pulses TF6 as shown in FIG. 5B. 256
The counter 35 counts 256 clock pulses TF6 as shown in FIG. 5C if there is a lead in the phase. Decrease the count by the amount left over from the previous count. Therefore, the second timing signal obtained by delaying the output DPC-8 of this counter 35 by the M-ary counter 49
The head switching signal RFSW based on MCOP will also change according to the phase error. In other words, the switching of heads 4 and 5 follows the phase error, and the switching point is 7H with respect to the vertical synchronization signal.
It will not fall outside the range of ±2H.

Next, the operation of the phase servo which transfers the phase information detected by the phase detection counter 35 to the buffer counter 40 and forms a pulse with a pulse width corresponding to the phase error will be explained with reference to FIG.

When the output DPEB of flip-flop 30 changes from "1" to "0", flip-flop 36 is set. The output of this flip-flop 36
FFL is supplied to the set terminal of the RST type flip-flop 37;
Since the reset terminal of the flip-flop 37 is supplied with its own output, the flip-flop 37 generates a rectangular waveform output PROTE equal to the pulse interval of the clock pulse TF12. Therefore, gate 3 is activated only during the period when this signal PROTE is "1".
8 is opened and a clock pulse CP is supplied to the phase detection counter 35. In addition, clock pulse TF1
The counter 35 is set to count exactly 512 clock pulses CP during a period of 2 pulse intervals.

The phase information detection counter 35 counts the clock pulse TF6 immediately before that, and waits while counting the number of pulses corresponding to the phase error. For example, when the phase is ahead, as shown in the waveform of DPC-8 shown in Fig. 6, the clock pulse TF6 rises after counting 256 clock pulses TF6, and then the clock pulse TF6 rises after counting some number of clock pulses TF6, for example, n pulses. I'm looking forward to it. Therefore, this counter 35 further counts clock pulses CP, and its output DPC-8 changes from "1" to "0" when 256-n pulses CP have been counted. In other words, the counter 35 returns to MSD as early as the phase is advanced.
Generate output. This provides phase information. At this time, the signal PROTE is “1”, so
The MSD output of counter 35 is applied through gate 39 to buffer counter 40, which is reset.

The counter 40 counts the clock pulse CP, and the output DPC of the phase detection counter 35 -
After being reset by 8, the counter 4
The period of the zero output pulse PR-8 is changed in proportion to the phase error. The output signal PR-8 of the counter 40 is supplied to the reset terminal of the flip-flop 43, and since the flip-flop 43 is configured to be set by the clock pulse TF12, the output signal DPPWM of the flip-flop 43 is The pulse width is changed according to the phase error; when the phase is leading, the pulse width of the signal DPPWM becomes narrower from this point on, as shown in Figure 6, and when the phase is lagging, the pulse width of the signal DPPWM becomes narrower. Pulse width becomes wider. This pulse signal DPPWM is integrated, superimposed on the speed error, and supplied to the motor 12 that drives the head drum 3, thereby performing phase servo. Note that since the signal PROTE is obtained in conjunction with the output of the pulse generator 17, the pulse period of the signal PROTE is the same as the rotation period of the head drum 3, 30 Hz.
Therefore, the output pulse of flip-flop 43
DPPWM continues to generate pulses with the same pulse width until the head drum rotates once.

Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above embodiments, and various modifications can be made based on the technical idea of the present invention.

Further, the specific circuit configuration is not limited to that disclosed in FIG. 4, and various changes are possible.

As described above, in the present invention, since the head switching signal is obtained in a state including the residual error of the phase servo, the switching point of the head switching is set to a predetermined value with respect to the vertical synchronization signal. It will be within range. Moreover, according to the present invention, since the servo error component is obtained from the phase detection counter of the phase servo to form the head switching timing signal, there are fewer adjustment points and the configuration is relatively simple.

[Brief explanation of the drawing]

The drawings show an embodiment in which the present invention is applied to a two-head type helical scan type VTR.
The figure is a plan view of a magnetic tape with various tracks formed on its surface, Figure 3 is a block diagram of the servo system of this VTR, Figure 4 is a circuit diagram of the phase servo circuit, Figure 5A, Figure 5 B and FIG. 5C are waveform diagrams showing the operation of forming a head switching signal,
The cases where there is no phase error, the case where the phase is delayed, and the case where the phase is advanced are shown. FIG. 6 is a waveform diagram showing the operation of the phase servo. In addition, in the symbols used in the drawings, 3...head drum, 4...magnetic head, 5...magnetic head,
18... Reference signal generation circuit, 35... Phase detection counter.

Claims (1)

[Claims] 1. A pulse generator for detecting the rotation of a rotating drum supporting the first and second heads, and a gate signal having a width corresponding to the phase difference between the output of the pulse generator and a reference signal. In a VTR equipped with a phase detection counter that counts gated clock pulses and a control circuit that controls the rotational phase of the drum based on the cyclic phase of the phase detection counter, 1st
a circuit for forming a timing signal; and after counting the clock pulses in the phase detection counter based on the phase difference between the output of the pulse generator and the first reference signal, the clock pulses are counted again in synchronization with the second reference signal. a circuit that causes the phase detection counter to count the clock pulses and generates a second timing signal related to the phase detection information of the phase detection counter when a predetermined count value is reached; 1. A head switching signal generation circuit for a VTR, characterized in that switching signals for the first and second heads are formed using the timing signal No. 2.