JPH0773369B2 - Time axis error correction device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time axis error correction device for correcting a time axis fluctuation of a reproduced video signal accompanied by a time axis fluctuation of a video tape recorder (VTR) or the like.

2. Description of the Related Art In various recording / reproducing apparatuses such as VTRs, a time base fluctuation occurs in a reproduced video signal due to a relative speed fluctuation between a signal detection medium and a recording medium. As a method of correcting the reproduced video signal accompanied by such time-axis fluctuation, a time-axis error correction device (T,
B, C) are used.

As such a time axis error correction device, for example, one shown in FIG. 3 is known. In the figure, the input playback video signal with time axis fluctuation input from the input terminal 25 is
The signal is input to the analog / digital converter 28 and is also input to the horizontal sync signal separation circuit 31 to separate the horizontal sync signal. The separated horizontal sync signal is input to a start / stop oscillator 33 that oscillates a fixed clock in synchronization with the trailing edge of the horizontal sync signal and stops the oscillation at the leading edge of the next horizontal sync signal. The signal output from the start / stop oscillator 33 is used as a write clock by sampling the reproduced video signal by the analog / digital converter 28 and resetting the write by the write reset pulse generator 34 synchronized with the horizontal synchronizing signal. Write to the memory 29 at the pulse timing. The reproduced video signal written in the memory 29 is a read reset pulse from the read reset pulse generator 35 that is phase-synchronized with the output signal obtained by dividing the reference clock output from the crystal oscillator 32 in the reference synchronization signal generation circuit 36. At the timing, it is read out according to the reference clock and output through the digital-analog converter 30. The reference clock from the crystal oscillator 32 is input to the reference synchronization signal generation circuit 36 to generate a reference vertical synchronization pulse that is phase-locked with the reference clock and output to the output terminal 26.

Since the write reset pulse and the read reset pulse do not have any synchronization relationship, the reference vertical cycle pulse is returned to the VTR servo as a reference vertical synchronization signal, and writing to the memory is performed vertically. The phase synchronization is performed during the synchronization period. In addition, the sync signal replacement circuit 37 replaces the sync signal portion of the reproduced video signal output from the digital-analog converter 30 and the reference sync signal generated from the reference sync signal generator 36 to output the sync signal. Terminal 26 is time-axis corrected,
Moreover, it is possible to obtain a reproduced video signal that replaces the synchronization signal.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the above-described time-axis error correction device, the input reproduction video signal and the reproduction video signal after the time-axis correction are configured so as to maintain phase synchronization in the vertical period. Poor performance and large time axis fluctuation component in the horizontal period. Therefore, for example, when the time axis correction of the above configuration is performed using a memory for one horizontal period, the phase of the write reset pulse synchronized with the input reproduction video signal and the read reset pulse formed from the fixed reference clock gradually shifts, A so-called memory overflow state may occur in which the writing period is less than one horizontal period. To improve these, there is a method of increasing the memory capacity,
When considering a home VTR, there is a cost problem. In addition, since the VTR servo reference vertical sync signal is created from the reference clock, when the time axis error correction device is used as an adapter, the VTR main reference vertical sync signal can be switched and input externally. The need arises. Furthermore, when controlling the VTR reference vertical sync signal,
Since the drum inertia is large, it is quite difficult to control the system stably and with good response.

In view of such a point, the present invention can perform time axis correction without overflowing even in a memory of one horizontal period, and does not make any improvement to VTR, and this time axis error correction device can be used as a VTR adapter. It has a configuration that can be used.

Means for Solving the Problems A time base error correction device of the present invention is a memory for sampling and writing an input reproduction video signal, and a reference clock generator configured to synchronize with an average frequency of a horizontal synchronization signal separated from the reproduction video signal. And a signal writing means for phase-modulating the horizontal synchronization signal so that the reference clock is instantaneously phase-synchronized for each horizontal period, and writing the output to the memory at the timing of the write reset pulse synchronized with the horizontal synchronization signal as a writing clock. And a means for reading a signal from the memory at the timing of a read reset pulse that is phase-synchronized with a signal obtained by dividing the reference clock by using the reference clock as a read clock, and a vertical synchronizing signal is separated from the read playback video signal, The extracted vertical synchronizing signal is in phase with the signal obtained by dividing the reference clock. The object described above is achieved by adopting a configuration including a reference synchronization signal generator which is made to be synchronized and a reference synchronization signal generating means which is phase-locked every vertical period.

The present invention is a time-axis error correction apparatus having the above-mentioned configuration, in which a reproduced video signal is sampled using an output signal having a time-axis fluctuation component obtained by the phase modulation means as a writing clock, and is sequentially stored in a predetermined memory. By writing and reading from the memory at the reference clock, a reproduction video signal whose time axis is corrected can be obtained as an output signal. At this time, writing to the memory is started by a writing reset pulse that is phase-synchronized with a horizontal synchronizing signal separated from the reproduced video signal, and reading from the memory is started by a reading reset pulse that is a reference clock divided. As a result, the time axis correction can be performed while the input reproduction video signal at the time of writing and the reproduction video signal at the time of reading keep the lock relationship within one horizontal period.

In addition, by making this configuration, the time axis error correction device can be used as an adapter for the VTR without any modification to the VTR.

Example An example of the present invention will be described with reference to FIG. The reproduced video signal input from the input terminal 1 is input to the analog / digital converter 3 and at the same time, the horizontal sync signal separation circuit 6 separates the horizontal sync signal. The reference clock 18 is, for example, a reference clock including a voltage controlled crystal oscillator 8, a low-pass filter 9, a frequency divider 11, and a phase comparator 10 that compares the phase of the horizontal synchronization signal with the output signal of the frequency divider 11. Generated by PLL17. This reference clock 18 is
It is input to the phase modulator 7 together with the horizontal synchronizing signal to generate a write clock, which is input to the analog / digital converter 3 and the memory 4, respectively. Also the reference clock
18 is simultaneously input to the memory 4 and the digital / analog converter 5 as a read clock.

At this time, the writing of the reproduced video signal to the memory is started by the writing reset pulse that is phase-synchronized with the horizontal synchronizing signal output from the writing reset pulse generator 12, and the reading from the memory is performed from the reading reset pulse generator 13. It is started by a read reset pulse phase-synchronized with the reference horizontal cycle signal output from the frequency divider 11 output.

The output signal of the digital-analog converter 5 is separated into a vertical synchronizing signal by the vertical synchronizing signal separating circuit 15, and is input to the reference synchronizing signal generating circuit 14 as a vertical cycle reset pulse of the reference synchronizing signal generating circuit 14.

Next, the specific operation of this embodiment will be described in more detail. The reproduced video signal input from the input terminal 1 is sampled by the write clock having the time base fluctuation component created by the phase modulator 7, and is stored in the memory 4 at the timing of the write reset pulse from the write reset pulse generator 12. Input sequentially. As the phase modulator 7, for example, a phase modulation circuit as shown in FIG. 2 is used. The phase modulation circuit shown in FIG. 2 inputs the horizontal synchronizing signal extracted from the horizontal synchronizing signal separation circuit 6 of FIG. 1 to the phase detector 23 from the input terminal 19 of FIG. The reference clock from the input terminal 21 is phase-shifted by the phase shift circuit 24 into n signals having different phases by 2π / n and input to the phase detector 23. Further, the n signals output from the phase shifter 24 are input to the clock signal selector 22 and the phase detector 23 detects the signal having the phase closest to the horizontal synchronizing signal, and the clock signal is selected from the detected output signals. The write clock is selected from the device 22 and output to the output terminal 20. The write clock generated by the above phase modulation circuit is used as the write clock in FIG.

The reference clock 18 in FIG.
The reference horizontal cycle signal formed by the reference synchronization signal generation circuit 14 and the horizontal synchronization signal from the horizontal synchronization signal separation circuit 6 are phase-compared by the phase comparator 10, and the lock error range is adjusted by the low-pass filter 9. Voltage controlled crystal oscillator 8
It is obtained by the reference clock generation PLL 17 whose reference clock 18 is the signal whose frequency is controlled by. By reading the reproduction video signal at the timing of the read reset pulse from the read reset pulse generator 13 using the reference clock 18 having no time axis fluctuation component, the input reproduction video signal and the read reproduction video signal The phase relationship can be stored within one horizontal period, the memory can be stored only for one horizontal period, and the reproduced video signal whose time axis is corrected can be obtained, and the output reproduced video signal is synchronously separated by the vertical sync separation circuit 15. By inputting the output vertical synchronization signal to the vertical cycle reset terminal of the reference synchronization signal generation circuit 14, the reference synchronization signal obtained from the reference synchronization signal generation circuit 14 is in phase with the reproduced video signal read from the memory in the horizontal period. In addition to synchronizing, even in the vertical period, the sync signal of the reproduced video signal is replaced by the sync signal replacement circuit 16 as the reference sync signal. The ability. Therefore, the output terminal 2 is time-axis corrected,
It is possible to obtain a reproduced video signal that replaces the synchronization signal. All of the above configurations can be performed by signal processing after being output from the VTR, so it can be installed as an adapter without making any modifications to the VTR itself.

The time axis error correction device according to the present invention is configured as described above, and always synchronizes the phase relationship between the input reproduction video signal and the time axis corrected output reproduction video signal within one horizontal period. Therefore, the capacity of the memory can be reduced to one horizontal period. Further, the reproduced video signal read from the memory and the reference sync signal from the reference sync signal generation circuit are phase-synchronized in the horizontal period and also in the vertical period. It can be replaced with a signal. All of the above configurations
Since it can be done by signal processing after being output from the VTR, it can be installed as an adapter without making any modifications to the VTR itself.

[Brief description of drawings]

FIG. 1 is a block diagram of a time axis error correction apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram of a write clock generation circuit of the apparatus, and FIG. 3 is an example of a conventional time axis error correction apparatus. FIG. 1 ... input terminal, 2 ... output terminal, 3 ... analog digital converter, 4 ... memory, 5 ... digital / analog converter, 6 ... horizontal sync signal separation circuit, 7 ... phase modulator, 8 ... Voltage controlled crystal oscillator, 9 ... Low pass filter, 10 ... Phase comparator, 11 ... Divider, 12 ... Write reset pulse generator, 13 ... Read reset pulse generator, 14 ... Reference Sync signal generation circuit, 15 ... Vertical sync signal separation circuit, 16 ... Sync signal replacement circuit, 17 ...
… Reference clock generation PLL, 18 …… Reference clock.

Claims (2)

[Claims] 1. A time axis error correction device for a reproduced video signal in a video tape recorder for FM-modulating and recording a video signal, comprising a memory for sampling and writing the reproduced video signal, and a horizontal synchronizing signal separated from the reproduced video signal. Reference clock generating means for generating a reference clock synchronized with an average frequency, phase modulating means for phase-modulating the horizontal synchronizing signal so that the reference clock is instantaneously phase-synchronized every horizontal period, and the horizontal synchronizing signal. Write reset pulse generating means for generating a write reset pulse that is phase-synchronized with and a write reset pulse from the write reset pulse generating means for sampling the reproduced video signal using a signal output from the phase modulating means as a write clock. Signal to be written to the memory at the timing Read-in reset pulse generating means for generating a read-out reset pulse in phase synchronization with a signal obtained by dividing the reference clock, and read-out reset pulse from the read-out reset pulse generating means using the reference clock as a read clock. Signal reading means for reading a reproduction video signal from the memory at a timing of, and vertical synchronization signal separating means for separating a vertical synchronization signal from the read reproduction video signal,
A reference synchronization signal generating means for generating a reference synchronization signal which is phase-synchronized with the frequency-divided signal of the reference clock and which is also phase-synchronized with the vertical synchronization signal every vertical period. And time axis error correction device. 2. The reference sync signal output from the reference sync signal generating means and the sync signal of the reproduced video signal read out from the reading means are replaced with each other. Time axis error correction device.