JPH0319632B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference signal generating device for a control loop, for example, a video tape recorder (hereinafter referred to as VTR).
It is suitable for use in a servo device (referred to as a servo device).

In general, VTRs perform recording and playback using a helical scan method using a rotating video head. Tape transport is obtained by a capstan motor, and rotation of the rotating video head for obtaining recording and playback is obtained by a rotating head motor. Here, a servo device is provided for each of the capstan motor and the rotary head motor.

Among the above-mentioned servo devices, consider, for example, a servo device for a rotary head motor. The rotating head motor can be used in VTR recording mode,
In both playback modes, it is normal to always rotate at a constant rotational frequency. This is controlled by a frequency control loop (so-called AFC loop) forming a servo device. moreover,
The above rotating head motor can be used in VTR recording mode,
Phase control is always performed in both playback modes. This phase control is performed by a so-called APC loop.

In the above AFC loop, the rotation frequency detection pulse of the rotary head motor is utilized. As the rotational frequency detection pulse, for example, a pulse obtained by a magnetic head that detects changes in the magnetic poles of a plurality of permanent magnets arranged with different polarities in the circumferential direction and rotating in association with a rotary head motor is used. In the AFC loop, the pulse interval of the rotational frequency detection pulse is measured. The measurement result of the pulse interval is finally expressed as a DC control voltage applied to the motor drive circuit, and when this voltage is at the target value, stable rotation is obtained.

Next, the APC loop will be explained. When in VTR recording mode, the APC loop monitors the phase relationship between the vertical synchronization signal of the video signal being recorded and the switching signal that indicates the switching timing of the rotating video head, and tracks diagonal tracks on the tape. The data is recorded one field at a time.

The signal whose phase is compared with the head switching signal is usually called a reference signal, and this reference signal is the same as the vertical synchronization signal (PAL/SECAM 50Hz,
This is a 1/2 frequency divided signal of NTSC 60Hz). On the other hand, this
In the APC loop, in the VTR playback mode, the frame frequency oscillator output is used as a reference signal, and the signal to be compared with this is a head switching signal.

In the VTR recording mode described above, the signal obtained by dividing the vertical synchronization signal by 1/2, that is, the reference signal, is also recorded as a control pulse on the tape via the control head. This control pulse is used as a target phase signal of the APC loop for the capstan motor during VTR playback mode. This means that the recording track formation position of the rotating video head in the recording mode is replaced by the control pulse recording position, so by feeding the tape in accordance with the phase of the playback control pulse, the rotating video head can record. When tracking on a track, the tracking phase is reproduced in the same way as when recording.

However, as mentioned above, if the 1/2 frequency divided output of the vertical synchronization signal is used as the reference signal, the phase may shift significantly or be dropped when the receiver switches stations or when there is a weak electric field. If there is, the servo operation may be disturbed, especially in playback mode. Particularly large disturbances occur when the vertical synchronization signal is missing; in this case, the phase of the control pulse is disturbed, which may disrupt the phase loop during playback and cause abnormal tape running. .

This invention was made in order to cope with the above-mentioned situation, and it creates a correction signal for the lack of a vertical synchronization signal, which is a particularly large cause of servo disturbance during playback, and when recording due to station switching, etc. The fluctuation of
It is an object of the present invention to provide a reference signal generating device for a control loop that can prevent disturbance of servo operation during reproduction.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which 11 is a digital oscillator, which is driven by a clock pulse applied from an input terminal 12. In FIG. This digital oscillator 11 generates preset signals M1, M2,
The period of the generated pulse 13 can be varied by M3.

This digital oscillator 11 includes presettable counters Q0 to Q15 and flip-flop circuits Q16 and Q1 that transfer the output of the final stage counter Q15.
7. It is composed of a NAND circuit G1, a NAND circuit G2 which provides load pulses to the counters Q0 to Q15, and flip-flop circuits Q18 and Q19. Now, when a positive pulse is input to the inverter G11, it is derived as a load pulse "1" via the NAND circuit G2 and flip-flop circuits Q18 and Q19. As a result, the currently designated constants are preset in the counters Q0 to Q15. (Buffer circuits 14, 15,
(Any one of the 16 outputs is high level) Then, the final stage counter Q15 generates a pulse with a period corresponding to the preset constant, and this is used again as a load pulse to perform an oscillation operation. The output of this digital oscillator 11 is
It is derived via a NAND circuit G1 and an inverter G10.

Next, flip-flop circuits Q22, Q23,
Q24 and NAND circuit G3, G6, inverter G
10 and the like constitute a sequencer 17. This sequencer 17 controls the flip-flop circuit Q2 depending on the presence or absence of a pulse from the NAND circuit G5.
2, Q23, Q24 are switched, and each flip-flop circuit Q22, Q23, Q
The outputs Q of 24 are outputted from buffer circuits 14 and 1, respectively.
5 and 16, and this is the previous counter Q
This is a constant designation signal for 0 to Q15.

Next, flip-flop circuits Q20, Q21,
NAND circuit G4, NAND circuit G5, and inverter G11 to which the output of this NAND circuit G5 is applied.
synchronizes the input vertical synchronizing signal V with a clock pulse and initializes the sequence operation.

Further, the NAND circuit G7, the inverter G9, and the NAND circuit G8 take out the output pulse of the oscillator 11 or the output pulse from the gate circuit G5 and apply it to the flip-flop circuit Q28.

Furthermore, flip-flop circuits Q29, Q30,
Q31 is a counter circuit 18 that detects that four or more vertical synchronization signals do not come in succession;
The outputs of the NAND circuit G5 are applied to the respective clear terminals. The flip-flop circuit Q28 is
The output pulse of the NAND circuit G8 is divided into 1/2 and outputted as a reference signal.

One embodiment of the present invention is constructed as described above, and will now be described with reference to the time chart shown in FIG. Now, flip-flop circuit Q20
Assume that a vertical synchronizing signal is input to the data input terminal D of . At this time, the output Q of flip-flop circuit Q22 is (0,1), the output Q of flip-flop circuit Q23 is (1,0), and the output Q of flip-flop circuit Q24 is (0,1). Therefore, the output of NAND circuit G3 is
The output Q of the flip-flop circuit Q25 is "1". (This timing is t ₁ of the time chart), the vertical synchronizing signal V is synchronized with the clock pulse CK and output as the vertical synchronizing pulse V _p via the NAND circuits G4 and G5. The output of NAND circuit G5 is inverter G9, and NAND circuit G
8 to the flip-flop circuit Q28, and output from its Q terminal as a reference signal.
Furthermore, the flip-flop circuit Q22 is preset by the output of the NAND circuit G5, and the flip-flop circuits Q23, Q24, Q29, Q30,
Q31 is cleared. Also, the vertical sync pulse
V _p is led via an inverter G11 to a NAND circuit G2 flip-flop circuit Q18, Q19 for generating a load pulse, and its output is supplied to an oscillator 11. At this time, the oscillator 11 is
A constant M1 is set. This means that the flip-flop circuit Q22 is preset and the output Q,=
This is because it becomes (1,0). This state is
This continues after the oscillator 11 is preset until the final oscillation output pulse (carry) is obtained. At this time, the oscillator 11 has a period T due to the constant M1.
1 is set, and this period T1 is smaller than the period of the vertical synchronizing signal, and is set to about 3/4 of the period of the vertical synchronizing signal. This period T1 is
The output Q of the flip-flop circuit Q25 is set to "0" by the preset Q output of the flip-flop circuit Q22, and the NAND circuit G4 is rendered non-conductive, so that input is prohibited. Next, when there is an oscillation output pulse from the digital oscillator 11, this causes the flip-flops Q16 and Q1 to
7. It is derived via the NAND circuit G1 and added to the NAND circuit G2. Therefore, a load pulse is outputted via flip-flop circuits Q18 and Q19. At this time, the output of the NAND circuit G1 is further passed through the inverter G10 to the flip-flop circuits Q22, Q23, Q24, Q29, Q30, Q.
31 as its clock pulse, the output Q of flip-flop circuit Q22 becomes (0, 1), and the output Q of flip-flop circuit Q23 becomes (1, 0). (Timing t ₂ ) Note that the output Q of the flip-flop circuit Q24 remains at (0, 1). Therefore, a constant M2 is preset in the digital oscillator 11 to count the clocks, but if the next vertical synchronization signal is input immediately (timing _t3 ), the same operation as before will be repeated. Become.

However, as shown at timing t ₄ in Figure 2,
If no vertical synchronization signal is input, oscillator 1
1 will continue to run on its own. At this time, since the constant M2 is specified, the NAND circuit G1,
Output pulses are obtained from the inverter G10 at a timing according to the period T2. (Timing t ₅ ) When this pulse e1 is obtained, the output Q of the flip-flop circuit Q22 becomes (0, 1)
As it is, the output Q of the flip-flop circuit Q23 becomes (0, 1), and the output Q of the flip-flop circuit Q23 becomes (0, 1).
The output Q of 24 becomes (1, 0). As a result, the oscillator 11 will be loaded with a constant M3, and the oscillator 11 will then generate a pulse with a period T3.

At this time, since the output Q of the flip-flop circuit Q24 is "1", the NAND circuit G7 can conduct the pulse obtained at the period T3. Period T
3 is set to T3<T1+T2, and is set to be the same as the period of the vertical synchronization signal. Also,
In this state, the flip-flop circuits Q29, Q30, and Q31 are driven by oscillation pulses using the output Q of the flip-flop circuit Q24 as data "1" because there is no clear pulse, and the input data is not transferred. Start. and,
When four oscillation pulses are input, a control pulse recording inhibit signal and image mute signal is output from the output terminal 20. (Fig. 2h) As described above, even if there is no vertical synchronous signal, a stable vertical synchronous pulse (Fig. 2i) can be obtained from the NAND circuit G28.

Note that if the vertical synchronizing signal is lost and the vertical synchronizing signal is input again after a certain period of time has elapsed, the operation synchronized with this signal will be obtained again, as explained with respect to timings t ₁ and t ₂ .

In Fig. 2, a indicates the vertical synchronizing pulse V _p ,
The figure b shows the output Q of the flip-flop circuit Q22,
The figure c shows the output Q of the flip-flop circuit Q23.
d in the figure is the output Q of the flip-flop circuit Q24,
The figure e is the output of the inverter G10, the figure f is the output of the NAND circuit G5, the figure g is the output of the NAND circuit G7, the figure h is the output Q of the flip-flop circuit Q31, and the figure i is the output of the NAND circuit G8. be.

As described above, according to this device, if the period from the time of loading until the pulse is output is T0, the period of the external reference signal is T1.
＜T0, T1+T2＞T3≒T0 3
A digital oscillator 11 is used which can be preset to different periods T1, T2 and T3. Next, a flip-flop circuit Q2 is used as a prohibition circuit that can control introduction or non-induction of a reference signal from the outside.
0, Q21, NAND circuits G4, G5, etc. Further, the output gate means controlled to select and derive either the output pulse from the inhibition circuit means or the output pulse from the digital oscillator 11 is connected to a NAND circuit G7, G
8. It is composed of an inverter G9 and the like.
Next, when the digital oscillator 11 is loaded by the output pulse from the inhibiting circuit means, the period T1 is set therein, and the inhibiting circuit means is controlled to set the state in which the reference signal is not introduced. The inhibition circuit means is set to the on-state by obtaining a pulse with a period T1, and the period T2 is set in the digital oscillator so that the period T2 is set.
If the reference signal is not input within this period T
a sequencer 17 for setting the period T3 in the digital oscillator using the pulses obtained in step 2, loading the digital oscillator with the pulses having the period T2, and switching the output gate means to select the pulse having the period T3;
It is equipped with

If the control signal is recorded using the reference signal generator described above, even if the vertical synchronization signal is lost due to switching stations, the servo operation during playback will operate stably and will not be disturbed. Never.

FIG. 3 is a diagram showing a servo system of a VTR using the apparatus of the present invention. In Figure 3, 3
0 is a magnetic taper, 31 is a rotating head motor, 32
is a rotating disk, and a rotating video head 33,
34 is attached to its outer periphery. Also, 35
is a capstan motor, and the capstan 36
drive the rotation. Furthermore, 37 is a control head which records a reference signal as a control pulse during a VTR recording operation, and reproduces the control pulse during a reproducing operation.

Let's start with the capstan servo system. The automatic rotation frequency control loop (AFC loop) for the capstan motor 35 is composed of a rotation detector 41 , an amplifier 42 , a frequency discriminator 43 , a synthesizer 44 , and a motor drive circuit 45 . On the other hand, the phase control APC loop for the capstan motor 35 is controlled by the rotation detector 4 in the VTR recording mode.
A frequency divider 46 that divides the output of 1, this frequency divider 46
The output of the reference oscillator 49 is applied to one input terminal via a switch 47, and the output of the reference oscillator 49 is applied to the other input terminal via a switch 50 to obtain a phase difference between the two inputs.
A low-pass filter 5 smoothes the output of
1. It is composed of a combiner 44 and the like to which the output of this low-pass filter 51 is added. Also this
In the APC loop, when the VTR is in the playback mode, the comparison signal input to the comparator 48 is switched. That is, the control pulse regenerated by the control head 37 is input to one input terminal of the comparator 48, and is connected to the switch 52 and the amplifier 5.
3. Input via switch 47. A reference signal is input to the other input terminal of the comparator 48 via a monostable multivibrator 54. The monostable multivibrator 54 obtains tracking of the rotating video head (adjustment of the trace position of the recording track and the video head). It is for. The reference signal is obtained from the reference signal generator 56 described above.

Next, the servo system of the rotary head motor 31 will be explained. For this rotating head motor 31
The AFC loop includes a rotation detector 61, an amplifier 62,
It is composed of a frequency discriminator 63, a synthesizer 64, a motor drive circuit 65, and the like.

Next, the APC loop includes a rotational phase detector 66, an amplifier 67, a monostable multivibrator circuit 68, 6
9, a flip-flop circuit 70, a comparator 71, etc., to which the head switching pulse obtained from the flip-flop circuit 70 is applied to one input terminal, and the reference signal is applied to the other input terminal. The output representing the phase comparison result of the comparator 71 is sent to the low pass filter 72.
The signal is input to the synthesizer 64 via.

Monostable multivibrator circuits 68 and 69 use a rotary phase detector 66 (a permanent magnet on a disk and a magnetic field that generates a pulse when it rotates) to obtain a head switching pulse (switching between A head and B head). The flip-flop circuit 70 is set by correcting the mechanical installation error of the head).
This is for adjusting the reset timing.

The reference signal generator of the present invention contributes to the stability of servo operation for the VTR servo system as described above.

As mentioned above, this invention creates a correction signal for the lack of a vertical synchronization signal, which is a particularly large cause of servo disturbance during playback, and compensates for fluctuations during recording due to station switching, etc. during playback. It is possible to provide a control loop reference signal generation device that can prevent servo operation from being disturbed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an embodiment of this invention, Fig. 2 is a time chart shown to explain the operation of the circuit shown in Fig. 1, and Fig. 3 is a diagram showing a servo system using this invention. It is. 11...Digital oscillator, 17...Sequencer,
Q20-Q24...Flip-flop circuit, G4,
G5, G7, G8...NAND circuit, G11...Inverter.

Claims (1)

[Claims] 1. The period from the time of loading to the output of the oscillation output pulse is the period of the external reference signal.
If T0, T1＜T0, T1＋T2＞T3, T3≒
A digital oscillator that can be preset to three types of periods T1, T2, and T3 that are related to T0, and can control whether or not to introduce the reference signal, and in the introduced state, output pulses that are synchronized to the reference signal are provided. and an output for deriving an output pulse from the inhibiting circuit means or selectively deriving an oscillation output pulse from the digital oscillator based on a control signal. gate means, an output pulse from the inhibition circuit means and an oscillation output pulse of the digital oscillator are input, and when the digital oscillator is loaded by the output pulse from the inhibition circuit means, the digital oscillator is loaded with the period T1. and controlling the prohibition circuit means to a state in which the reference signal is not introduced, and when an oscillation output pulse of the period T1 is obtained from the digital oscillator, the prohibition circuit means is controlled to a state in which the reference signal is introduced. At the same time, the digital oscillator is preset to a value that obtains the period T2, and when an output pulse from the inhibiting circuit means is input within the period T2, the digital oscillator is preset to a value that obtains the period T1 by this pulse. If the output pulse from the inhibiting circuit means is not input within the period T2, the period T2
Presetting a value for obtaining the period T3 in the digital oscillator using the pulse obtained in
A control loop reference signal generating device comprising: a sequencer that applies the control signal to the output gate means to control the digital oscillator output to a selectively derived state.