JPS5857656A - Switching device of control loop - Google Patents

Abstract

PURPOSE:To have coincidence in a stable and continuous way between the phase of a processing signal obtained before switching and the phase of the next processing signal, by feeding the divided output of a revolution detecting pulse to a reference signal generator. CONSTITUTION:A control pulse is recorded with a 1/2 frequency of a vertical synchronizing signal. This is due to the fact that the output of a synchronism separating circuit 65 which extracts a synchronising signal out of a video signal is divided by a 1/2 frequency divider 67 via a switch SW6 and then applied to a terminal R of a switch SW5 via an amplifier 73. The SW6 is set at the terminal R in the recording mode and then switched to a terminal P at the side of a reference oscillator 66 which has a free oscillation with a frequency equal to the vertical synchronizing signal in the reproduction mode. The switching of the SW5 is controlled by a flip-flop circuit 68, and the switch timing of the SW5 is synchronous with the pulse of the amplifier 68.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control loop switching device, and is effective for preventing a servo device of a video tape recorder (hereinafter referred to as VTR) from being disturbed during editing work, for example.

In general, VTRs perform recording and playback using a helical scan method using a rotating video head. Tape feeding is obtained by using a capstan motor,
The rotation of the rotating video head to obtain recording and playback is obtained by a rotating Rad motor. Here is the capstan motor.

A servo device is provided for each rotary rotor motor.

Each servo device of this type is provided with an automatic frequency control (AFC) loop and an automatic phase adjustment (APC) loop.
When editing using TRf, the editing state may be searched for in the playback state and then switched to the recording state. This means making continuous recordings. At this time, the APC loop is switched in the servo device, but since the phases of the reference signal and comparison signal during playback and the reference signal and comparison signal during recording are not constant and continuous, the control operation is disturbed. Sometimes. This means that multiple signals are disturbed in the connected eyes.

For example, consider the servo system of a capstan motor. For the ↓ sea urchin capstan motor 11 shown in Fig. 1, a rotation detector 12 consisting of a permanent magnet and a magnetic head,
An AFC loop is provided that includes an amplifier 13 that applies the output pulse of the rotation detector 12 to a frequency discriminator 14, and a capstan motor drive circuit 16 into which the output of the frequency discriminator 14 is input via a synthesizer 15. . Also,
The APC loop includes a frequency divider 17 that divides the entire frequency of the output pulse from the amplifier 13, a switch 18 that is switched according to the recording/reproduction mode, and a phase comparator 19 that compares the phase of the pulse derived from this switch 18 with a reference bone. A low-pass filter 20 and the like converts the output of the phase comparator 19 into direct current and applies it to the motor drive circuit 16 via the synthesizer 15.

Here, when the VTR is in recording mode, switch 1
8 derives the frequency divided output from the frequency divider 17. Therefore, in the comparator 19, a phase comparison is performed between the frequency-divided output from the frequency divider 17 and the reference signal (equivalent to a signal frequency-divided into the vertical synchronization signal sound of the recorded video signal). Rotation that follows the signal is obtained. On the other hand, when the VTR is in a playback operation state, the switch 18 derives a playback control pulse from the tape 21. Therefore, in the comparator 19, a phase comparison is made between the reproduction control pulse and a reference signal of a constant frequency, and the tape is fed so that the phase relationship between the reproduction control pulse and the reference signal is always constant.

Therefore, when switching from the VTR' (j playback operating state to the recording operating state), the phases of both signals input to the comparator 19 are not necessarily connected continuously in a constant relationship to the phases of both signals during playback. First, at this time, the servo system will be disturbed.

This invention was made with attention to the above point, and even if the operation mode is switched in the servo loop as described above, the phase of the next processed signal is not changed to the phase of the processed signal before switching. The overall objective is to provide a control loop switching device that can be synchronized stably and continuously.

Embodiments of the present invention will be described below with reference to the drawings. 〇 Figure 2 shows a servo system of a VTR, where 30 is a magnetic tape, 31 is a rotary disk motor, and 32 is a rotating disk. Video heads A and B are attached. Also, 33 is a capstan motor, which can rotate the capstan 34. Furthermore, 35 is a control head, which records all reference signals during VTR recording operation. This is used as a control pulse, and the entire control pulse is regenerated during regeneration operation.

First, the servo system for the rotation rad motor 31 will be explained. The AFC loop for the rotating rotor motor 3 includes a rotation detector 36, an amplifier 37 that amplifies the output pulse of the rotation detector 36, a frequency discriminator 38 that discriminates all frequencies output from the amplifier 37, a synthesis circuit 39, and a motor drive circuit. 40, etc., the zero-order APC loop includes a rotational phase detector 4, an amplifier 42, monostable multivibrator circuits 43 and 44, a flip-flop circuit 45, and a head switching pulse obtained from the flip-flop circuit 45. is applied to one input terminal, and a reference signal is applied to the other input terminal. The output of the phase comparison result of the comparator 46 is input to the synthesizer 39 via a low-pass filter 47. To obtain the monostable multi-pulsing pulse (for switching between A head and B head), a rotary phase detector 4-t is used.
The mechanical attachment (permanent magnet on the disk and magnetic head that generates all pulses when it rotates) is for correcting errors and fully adjusting the set and reset timing of the flip-flop circuit 45.

Next, the entire servo system for the capstan motor 33 will be explained. The AFC loop for the capstan motor 33 is
It is formed by a loop of a rotation detector 51, an amplifier 52, a frequency discriminator 53, a synthesizer 54, and a motor drive circuit 55.

On the other hand, the APC loop for the capstan motor 33 is formed as follows.

(2) The output of the frequency divider 56 which divides the output sound of the rotation detector 5 during recording operation of the VTR is applied to one input terminal of the comparator 57 via the switch sw3'l. The output of the reference signal generator 60 is connected to the other input terminal of the comparator 57 via the switch SW 4
It is input via f. And this comparator 57
The output that collects the phase comparison result is passed through the low-pass filter 5.
The voltage is converted into a DC voltage at B, and is input to the motor drive circuit 55 via the synthesizer 54.

■ Control head 35 that reproduces all control pulses during VTR playback operation
The output of 0 is input to one side of the comparator 57 via the amplifier 6, Schmitt circuit 62, and switch 5W3f
The other input terminal of this comparator 57 receives the reference signal that has passed through the dragging position adjustment circuit 63.
It is added via ゜SW4'ff. The dragging position adjustment circuit 63 uses a mono multivibrator, and is designed to match the relative phase relationship between the control pulse during recording and the -rad switching pulse (for switching between head and B heads) during playback. belongs to. This is to compensate for errors in the mechanical arrangement of the control head and rotary hood in each VTR.

Note that the control pulse is recorded at a frequency of 1 of the vertical synchronization signal. This means that the output of the synchronization separation path 65, which extracts all synchronization signals from the video signal to be recorded, This is because the signal is frequency-divided by the frequency divider 67 and then applied to the terminal R of the switch SW5 via the amplifier 73. The switch 8W6 is set to the terminal R during the recording operation, and is switched to the terminal P on the side of the reference oscillator 66 which freely oscillates at the same frequency as the vertical synchronization signal during the reproduction operation. The switching is controlled by the flip-flop circuit 68, and the switching timing is switched in synchronization with the pulse on the amplifier 68 side.

As mentioned above, in the capstan servo system, the APC loop is used to switch the thread path to A, which handles different types of signals during recording and reproducing operations of the VTR. Regarding the switches SWI to SW6, the states of the switches shown in FIG. 2 indicate the reproducing operation state of the VTR, and the side including the terminal P is selected. On the other hand, during the recording operation of the VTR, the third. 4th. fifth switches SW3, SW4;

SW5. SW6 is switched to the side including the terminal R. Here, the first. The second switches SW'l and SW2 are set to V
Used when TR is in edit standby state.

In other words, when in the editing standby state, the first switch SWI
is switched to the terminal E side, so the reference signal generator 60
receives the frequency-divided output from the frequency divider 56, and becomes phase synchronized with this frequency-divided output. ′! ! In addition, since the second switch SW2 is also switched to the terminal E side, in this case, a pulse that has the frequency of 1 of the vertical synchronization signal is outputted through the entire inverter 64, so its inverted output is derived. Become.

(2) When editing a VTR If all editing is to be performed using a VTR, the VTR is put into playback mode, the location where a new video signal is to be recorded, that is, the editing start point is searched for, and the next necessary new video signal is recorded.

In this case, the first VTR on the recording side is in a reproduction operation state and in an editing standby state. On the other hand, the second VTR is set, for example, to a still image reproduction state. 1st VTR
When the image becomes the joining image, that is, the knitting starting point, the first VTR is moved from the editing standby state to the recording operation state, and at the same time, the second VTR is brought into the normal playback state.

Therefore, each of the first to fifth stages in the first VTR
The table below shows the states of the selected terminals when editing SWI to SW5.

Here, the switching of each switch at the time of the above-mentioned playback 9mm special and recording start is obtained by the output of the flip-flop circuit 69, which receives an external operation signal.

Data input terminal 71 of flip-flop circuit 69.70
．． 72, 1111I LL OII at the time of recording.

It becomes l Q II during playback, and 110 II # IIT when waiting for editing.

According to the above system, when in the edit standby state, the output of the frequency divider 56 is input to the reference signal generator 60, and the output of the reference signal generator 60 is approximately synchronized with the rotational phase of the capstan motor 510. Become. Also, at this time, the vertical synchronization signal of the video signal to be recorded next and the reproduction control pulse are also compared in phase, so if the two signals are in a phase synchronized relationship (0) and then switched to recording operation, Since the output of the reference signal generator 60 and the output of the divider 56 are input to the comparator 57, the phase difference between both inputs matches the target value, and there is no servo disturbance. This is a pre-regeneration control pulse and
This is because control is performed so that one frequency of the vertical synchronization signal to be recorded is phase-synchronized.

As mentioned above, according to the present device, the first. The feature is that the second switch S"wVl, SW2, reference signal generator 60, etc. are provided, and the specific circuits related to these are as follows.
It is constructed as shown in FIG. The same parts as in FIG. 2 will be described with the same reference numerals.

In FIG. 3, 75 is a presettable down counter, which includes shift registers QO-Q15. A clock pulse is introduced via an inverter, and a carrier signal is derived from the final stage shift register Q15. This carrier signal is introduced into a carrier signal output circuit 76. This carry output circuit 76 is composed of flip-flop circuits Q1B, Q19, a NAND circuit G2, and the like.

The flip-flop circuit Q20°G21 is a circuit that adjusts the switching timing of the first switch SW1 when a switching signal is input from the flip-flop circuit 70 during editing standby. Also, the flip-flop circuit Q22°Q23
This circuit also determines the timing when outputting the output of the carry output circuit 76 to the outside. Furthermore, the output from the carry output circuit 76 is led out to the outside (specifically, the comparator 57) via the aforementioned flip-flop circuit Q22°Q23 and the fourth switch 5W4f, and is also output to the load of the presettable down counter 75. Also used as a pulse. The thread path used as a load pulse is a NAND circuit G2 and a mono multivibrator circuit 77.
, first switch SW1, flip-flop circuit Q24
, load pulse generation circuit 78 (solid flop circuit Q
25. Q26, NAND circuit G3, inverter 04, etc.).

” The operation of the circuit configuration described in item 1 will be explained for each operation mode of VT and It.
110II is added. This causes the third switch SW3 and the fourth switch SW 4 Ll:.

Select terminal R side. On the other hand, at this time, the first. The second switches 8W1 and SW2 are on the terminal RP side. When the above settings are reached, 0 presettable down counter 75 is constant 1+Mz
is preset, a clock is counted, and a carry (CRY) is outputted via the carry output circuit 76 and the fourth switch 8W4f. Also, a NAND circuit G2, a mono multivibrator circuit 77, a first switch SW1
, a load pulse is generated via the load pulse generation circuit 78, and a constant is thereby set in the counter 75 again.

In addition to this, a carry is obtained at a constant period, and the signal output from the fourth switch SW4 is used as a reference signal (Ref-1) by the comparator 57 (shown in FIG. 2). become. Furthermore, the signal applied to the other input terminal of the comparator 57 is now the output C-PG from the frequency divider 56 (shown in Figure W2), which has passed through the third switch SWJ. The mono-multivibrator circuit 77 mentioned above is for finely adjusting the frequency of the output Ref-1, and is used for adjusting the tape feeding speed due to errors in the capstan shaft diameter, etc., but it may be omitted if the error is small.

■ VTR playback operation status During playback operation of VTE, the flip-flop circuit 69
．． The output of 70 becomes l O# 410I+. At this time, each switch SWI, SW2 . SW3.

SW4 selects all sidetones including terminal P. Therefore, the tracking signal TRK input to the second switch SW2 is used as the signal Ref-1 input to one side of the converter 57.
pcon/(The signal input to the other side of the regulator 57 is:
The playback control knob (xP-CTL) passed through the third switch SW3 is input. Therefore, at this time, the tape is run so that the rotational phase of the rotary head and the phase of the control pulse are in a constant relationship. can get.

The carry of the presettable down counter 75 at this time is not led out to the outside and becomes irrelevant.

In FIG. 4, the signal waveforms of each part are shown. In the reproduction operation state indicated by "-", the period is indicated by period (PLAY), as can be seen from the VTR mode shown in FIG. 4 (4).

4(a) and 4(b) are designation signals from the outside; FIG. 4(a) is an input to the flip-flop circuit 70, and FIG. 4(b) is an input to the flip-flop circuit 69. FIGS. 4(c) and 4(d) show the input side of the inverter 64.

The signal on the output side, FIG. 4(e), is the tracking signal T RK% output from the tracking position adjustment circuit 63.
i 4 Figure (f) c, Regeneration control pulse P-PG
, FIG. 4(g) shows the output C-P obtained from the frequency divider 56.
G, FIG. 4(h) is the output CRY obtained from the shift register Q15 of the counter 75, FIG. 4(1) is the output AMM-0 obtained from the mono multivibrator 77,
(j) and (k) of the same figure show the flip-flop circuit 70.
．． Signal [F] output from 69.

■It is. Furthermore, FIG.
D is an editing standby state, and period RFC is a recording operation state.

In addition, Fig. 4 (→, (n) shows the types of signals whose phases are compared in the comparator 57 in each mode. ◎ Edit standby state of VTR When the VTR enters edit standby state, Fig. 4 (4) period E
As shown by D, the output of the flip-flop circuit 10.69 becomes "0". As a result, the first switch SW1 is connected to the terminal E side, the second switch SW2 is connected to the terminal E side, and the third switch SW2 is connected to the terminal E side. Fourth switch SW3. SW4 also selects sidetone for all terminal E units. Therefore, as one input signal Ref-1 of the comparator 57, the second . 4th switch sw
2. The signal EP (shown in FIG. 4(d)) passing through the SWJ is used, and the other input is the reproduction control pulse P-CTL. , the output C-PC from the frequency divider 56 is inputted via the first switch 5W1f. Bird pulses and constant settings for the counters are synchronized by clock pulses. Therefore, the oscillation loop including this counter 75 has an oscillation output (carry) that is phase-synchronized with the capstan motor.
You will get . On the other hand, the capstan motor 33 is
The phase will be locked to the playback control pulse P-CTL currently being played and the old frequency output FP of the vertical synchronization signal of the video signal that is about to be recorded and edited. ○Switch to the constant 'iM2 of the presettable down counter 75. The purpose of this is to provide a margin to facilitate phase locking to the output of the splitter 56.The O constant M1 is set during the recording operation and when obtaining the ideal reference signal frequency. Further, in the edit standby state, the entire output of the frequency divider 67 is introduced via the inverter 64 as shown in FIG. 4(C).

As can be seen from the relationships in (d), (e), and (f), the phase difference is such that it does not cause a large change in the phase difference between the track key yl' (IT number TRK and the reproduction control pulse P-CTT). This is to make all settings.

Therefore, if the VTrti recording operation is switched from this state, the servo operation will not be disturbed because the synchronization signal of the recording signal is phase-locked to the tape running (playback control pulse).

■ That is, when the VTR is switched from the editing standby state to the recording mode, each switch SWI, SW2, SW3, SW
4 are the switches SW3 and SW3, respectively, as explained in ■.
SW4 is terminal R side, switch SWI, SW2 is terminal R-
This is the P side.

FIG. 5 shows an enlarged view of the period 80 in FIG. 4, and FIGS. 5(a) and 5(b) show the flip-flop circuit 70.
．． Inputs to the inverter 640, FIGS. 5(c) and 5(d) are signals EP and EP on the input side and output side of the inverter 640, and FIG. 5(, ) is the tracking signal TRK. Further, FIG. 5(f) shows the reproduction control pulse P-CT T
,,(g) of the same figure shows the output C-PG of the frequency divider 56.

The figure (11) is the output of the register Q15, and the figure (+) is the output AMM-0° of the mono multivibrator circuit 72.
Figures (j) and (k) show a flip-flop circuit 7o.

69 output [F], ■.

FIG. 6 further shows an enlarged view of period 8 in FIG. 5, and (a) and (b) show the input side of the inverter 64,
The signals EP and FP on the output side, (c) in the same figure are the reproduction control pulses P-CTL, (d) in the same figure are the output C-PG of the i frequency divider 56, (,) are the clock pulses, Figures (f) and (g) are the outputs of the flip-flop circuits Q15 and Q23, and figures (h) and (1) are the outputs (2) and (1) of the flip-flop circuits 10.69 and 23, respectively. Also, Figure 6 (
j) is a diagram showing the switching of the constant preset of the counter 75, Fig. 6(k), (A is the signal on the input side and output side of the mono multivibrator 77, (→ is the first switch) The state change of SW1, (n) in the same figure is the output of the third switch s W J, and (o) in the same figure is the change in the state of the fourth switch f-
It shows the output of 8W4.

As described above, according to the present invention, when the operation mode is switched, the phase of the next processed signal can be continuously and stably matched to the phase of the processed signal before switching, thereby preventing disturbances in control operation. It is possible to provide a control loop switching device that can prevent the above.

[Brief explanation of the drawing]

Fig. 1 is a system diagram of a capstan servo device of a VTR, Fig. 2 is a configuration explanatory diagram showing one embodiment of the present invention, and Fig. 3
The figure is a circuit diagram showing all the specific circuits of the main parts of this invention,
FIGS. 4(a) to (n), FIGS. 5(a) to (k), and FIGS. 6(a) to (o) are timing charts showing the operation timing of the circuit of this invention, respectively. - Capstan motor, 34... Capstan, 35"° control head s 1-Do rotation detector, 52... Amplifier, 53... Frequency discriminator, 54...
...Synthesizer, 55...Motor drive circuit, 56.minute8n, sy...Comparator, 58...Robuss filter, 60...Reference signal generator, 63...Tracking position adjustment circuit, 64...Inverter, S
W J~SW5...1st~5th switch, 69°7
0-°° flip-flop circuit, 75...Brisella path, 7゛8...9...Load pulse generation circuit.

Claims (1)

[Claims] (1.) The output of the comparator is taken out as a phase control voltage through a low-pass filter, and is synthesized with the frequency control voltage of the automatic frequency control loop in the synthesizer to drive the capstan motor. A servo means of the video tape recorder is inputted to the servo means of the video tape recorder, and a tracking adjustment circuit that controls the entire phase of the playback control P/L/X and the rotary head when the video tape recorder is in the playback operation state as a comparison input of the comparator. and when the video tape recorder is in an editing standby state, the reproduction control pulse and the i-divided vertical synchronization signal of the video signal to be recorded are used as comparison inputs of the comparator. and a means for inputting a frequency-divided output of a rotation detection pulse obtained from a rotation detector of the capstan motor to a reference signal generator when the video tape recorder is in an editing standby state. means for switching the output pulses of the reference signal generator so as to be phase synchronized with the input branch output, and as a comparison input of the comparator when the video tape recorder is switched to a recording operating state;
A control loop switching device characterized by comprising means for inputting the frequency-divided output of the rotation detection pulse and all the output pulses of the reference signal generator. (2) As the reference signal generator, a presettable down counter is used to obtain a carry output by counting clock pulses based on input of load pulses;
When the video tape recorder is in a recording state, the counter is preset to a first constant so that it is automatically loaded by the carry output, and when the video tape recorder is in an editing standby state, 2. The control loop switching device according to claim 1, wherein a second constant is preset in said counter and loaded by a frequency-divided output of said rotation detection pulse.