JPS5853053A - Reference signal generator - Google Patents

Abstract

PURPOSE:To eliminate the adjustment of a buffer frequency, to eliminate the effect of temperature and to attain circuit integration, by digitizing the circuit with a counter counting clock signals and a preset circuit. CONSTITUTION:When a vertical synchronizing signal (a) is inputted to a preset pulse generating circuit 12, a preset pulse (e) with one clock width synchronized to set an RS flip-flop 11, allowing to set an (n)-bit binary counter 8 via a preset circuit 9 to a preset value. An output pulse C of a count value detecting circuit 10 resets the RS flip-flop 11. While the count value of the binary counter 8 is within a prescribed range, when the signal (a) is inputted, the preset pulse (e) is outputted and the counter 8 is again reset to the preset value and the RS flip-flop 11 is set.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference signal generator for a magnetic recording/reproducing device (VTR), in which a reference signal is synchronized in phase with a vertical synchronizing signal during recording, and synchronized with the output of a fixed oscillator during playback. It is configured to generate a reference signal.

FIG. 1 is a block diagram showing the configuration of a conventional reference signal generator used in a VTR. During recording (RICC), the vertical synchronization signal (V ,5syna,),
During reproduction (PB), the output obtained by dividing the oscillation frequency of the crystal oscillator 2 by the frequency dividing circuit 3 is switched by the changeover switch 5 and guided to the output terminal 6 to be used as a reference signal.

The reference signal during reproduction is obtained from the crystal oscillator 2 and is therefore stable; however, during recording, V, 5ync is missing (v, 5yna in a weak electric field).

■ It is not necessarily stable due to reasons such as ○ where v, , and 5 sync are disturbed due to external noise.

Therefore, if v,5ync is simply frequency-divided and used as a reference signal for the servo circuit during recording, the operation of the servo circuit will become unstable, making it impossible to perform stable recording on the VTR. The astable multi 1 is used as a countermeasure against this problem, and a specific circuit example thereof is shown in FIG.

In FIG. 2, Ql is a trigger transistor for locking the astable multi with V and GNC, R1 is the base resistance of the transistor Q1, and Q2 and Q3 are the first and second transistors forming the astable multi. The second transistors, R2 and R3, are the collector resistances of transistors Q2゜Q3, respectively, %Ql,
R4 and VR are 0FF (Q2
These are capacitors, resistors, and volumes that determine the 0ff) period, and these 02. Rs are each transistor 82
A capacitor that determines the 0FF (ON of Q3) period.

When the resistance is 0, that is, the transistor Q3 is in the OFF state, the capacitor C1 is connected to the power supply → V R-+R4 → C1 → Q
When the base potential of the J transistor Q3 becomes V1113 (011), the transistor Q3 is turned ON. Capacitor C2 is already connected to power supply → R3 → C2 → Q2 → G
NI), and transistor Q3 is on.
Then, the base of transistor Q2 is negatively biased and becomes %
Turn off Q2. When transistor Q3 is in the ON state, capacitor C2 is charged through the path of power supply → R5 → C2 → Q3 → GNI), and the base potential of transistor Q2 becomes vsx2 (
ox), 92 turns ON. On the other hand, capacitor C1 has already been charged through the path of power supply→R2→C1→Q3→GND, and when transistor Q2 is turned on, the base of 93 is negatively biased and transistor Q3 is turned off. Thereafter, capacitors C1 and C2 are similarly charged and discharged by transistors Q2. Q3 continues to oscillate by repeatedly turning on and off. The oscillation frequency at this time is τ during the period when transistor Q3 is OFF.
1 and transistor Q 2 OFF F (7) Period τ2L
D'/(z1+r2)llZtfxru. Therefore, VR
By adjusting τ1, it is possible to adjust the oscillation frequency.

Here, the astable multi can be locked by v, 5 sync only when transistor Q2 is OFF, so: ■ The frequency of the astable multi is set lower than the frequency of V, 5 sync, and ■ The influence of external noise is reduced. Therefore, τ1〉τ2
τ1, which is approximately 80% of the reference signal period of the servo circuit.
It is necessary to set it to .

In the case of NTf30 method, V, sync frequency is eoH
z, and generally in a servo circuit, the bar is set to 301 (30 > 1/(τ, 10τ2) since z is the reference frequency. Here, V, 5yna is 6oliz or 3
Either 0Hz may be used.

By using the astable multiplier as described above, a buffer function can be provided and the above-mentioned problems can be solved, but this conventional reference signal generating device has the following drawbacks.

■ It is necessary to adjust the oscillation frequency of the astable multi.

■The 5 oscillation frequencies change because capacitors, resistors, volumes, and transistors have temperature characteristics.

■ Requires a capacitor, resistor, and volume, making it unsuitable for integrated circuits.

The present invention provides a reference signal generating device that can solve the drawbacks of the conventional example.

FIG. 3 shows an embodiment of the reference signal generator according to the present invention, in which 8 is an n-bit binary counter, 9 is an n-bit preset value generation and preset circuit, 10 is a count value detection circuit, and 11 is an R8 flip-flop. , 12 is a preset pulse generation circuit.

FIG. 4 is an analog representation of the counting operation of the n-bit binary counter 8, and the counted values NOR and NOP are the preset values of the preset value generation and preset circuit 9 during recording and playback. is switched by different signals applied to the terminal 16 during recording and when [1] is being generated. The count values N1 and N2 are determined by the count value detection circuit 1.
It is the count value detected by o, and 'OR + 'OP + N
The relationship between 1 and N2 is given by the following equation.

7-9 NOR-NOP-ΔN・・・・・・・・・・・・・・・
(2) Here, f is the frame frequency of the vertical synchronization signal, folL is the clock frequency, and ΔN is a value that determines the buffer frequency.

FIG. 6 is an operational waveform diagram during recording, and b is an analog representation of the counting operation of the n-bit binary counter 8. A is a vertical synchronizing signal inputted to the terminal 13, and the sync is disconnected in some places. The operation of FIG. 3 will be explained with reference to FIG. When the vertical synchronization signal a is input to the preset pulse generation circuit 12, a preset pulse e of one clock width synchronized with the vertical synchronization signal a is output, and the R
8 flip-flop 11 is set, and n-bit binary counter 8 is set to preset value NOH via preset circuit 9. Immediately after that, the clock pulse g input to the terminal 14 starts counting, and when the count value is N1, the count value detection circuit 1o generates a pulse C to reset the R8 flip-flop 11 and generate the preset pulse. The circuit 12 is placed in a state in which it receives the vertical synchronization signal. That is, while the count value of the n-bit binary counter 8 is between NOR and N1, input of the vertical synchronizing signal is prohibited to take measures against noise.

Then, the count value of the n-bit binary counter 8 changes from N1 to N2.
If the vertical synchronizing signal a is input during this period, the preset pulse e is output, the n-bit binary counter 8 is set to the preset value NOH again, and the RS flip-flop 1
1 is set and the same operation is repeated thereafter. In addition, if the vertical synchronizing signal a is dropped for some reason, the n-bit binary counter 8 counts up to the count value N2, and the output pulse d of the count value detection circuit 1o generated at the count value N2 is converted to the preset pulse e. The n-bit binary counter 8 is set to the preset value NOH. Moreover, the FIS flip-flop 4 is also set, and the above-described operation is repeated.

In this way, if the vertical synchronization signal a is dropped, it can be backed up with the output pulse d of the count value detection circuit 10 to provide a buffer function, and the vertical synchronization signal a returns to the n-bit binary counter 8. If the count value falls within the period from N1 to N2, the presetting operation using the vertical synchronizing signal a becomes possible again.

As a result of the above, the signals e and f are synchronized with v and 5ync, and can be used as reference signals for the servo circuit. Figure 6 is an operating waveform diagram during playback, and the counting operation of the bldn bit binary counter 10 is expressed as an analog signal. It is something that has not yet appeared. During reproduction, input of the vertical synchronizing signal a is prohibited in the preset pulse generation circuit 12 by a signal indicating the reproduction time applied to the terminal 15, and the output pulse d of the count value detection circuit 1o is used as the preset pulse e to generate the bit binary counter 8. is set to the preset value HOP. Immediately after that, counting is started and the same operation is repeated after d, counting up to hN2, thereby obtaining a reference signal for the servo circuit during reproduction.

As explained above, in the present invention, all configuration type 1゜ elements are digitized, so there is no need to adjust the buffer frequency as in the conventional case, and the drawback that the buffer frequency changes due to temperature changes can also be eliminated. , does not require a volume or the like, and is suitable for integration into integrated circuits.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional reference signal generating device, Fig. 2 is a specific circuit diagram of an astable multiplier used in the conventional reference signal generating device, and Fig. 3 is a diagram of a reference signal generating device according to the present invention. A block diagram showing one embodiment; FIG. 4 is an analog representation of the counting operation of the n-bit binary counter in FIG. 3; FIG. 6 is an operational waveform of the reference signal generator of the present invention during recording. 6 are operational waveform diagrams during reproduction. 8...n-bit binary counter, 9...
Preset circuit, 1o... Count value detection circuit, 1
1...FI8 flip-flop circuit, 12...
...Priceratonocurse generation circuit, 13...
- Vertical synchronization signal input terminal, 14... Clock signal input terminal, 15... Record/playback signal input terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person 1st
Figure 4 Figure 2 fCK' Figure 5 Figure 6 f\

Claims (2)

[Claims] (1) Counter means for sequentially counting clock signals; and in response to application of a control signal, a preset value of the counter means is set to a first predetermined value NOR during recording and a second predetermined value larger than the preset value during reproduction. a count value detection circuit that generates a detection output when the count value of the counter means reaches a predetermined value; and a count value detection circuit that generates a detection output when the count value of the counter means reaches a predetermined value. and means for applying the detection output to the presetting means as the control signal during reproduction, the reference signal generating device using a signal phase-synchronized with the control signal as the reference signal. (2) After the counter means is preset by the control signal, the presetting operation of the preset means is prohibited until the count value of the counter means reaches a predetermined count value that is less than or equal to the predetermined value.2, -2 A reference signal generating device according to claim 1, which is configured to