JPS648541B2 - - Google Patents

Description

Detailed Description of the Invention The present invention uses a stable frequency such as the output of a crystal oscillator as a speed reference to improve rotational speed stability, and furthermore inserts a low-frequency compensation circuit into the speed control loop to reduce the load. This relates to a motor speed control device that improves stability and achieves almost the same characteristics as when phase control is applied, even though it is essentially a single-loop control circuit with only a speed control loop. be.

Conventional motors used in audio equipment such as record players use speed control motors that use voltage as the speed standard, but this method is sufficiently resistant to changes in ambient temperature and aging of components. It is difficult to create a stable reference voltage, and there are also problems in that speed deviation occurs with respect to a steady load.

To solve this problem, high-end machines add a phase control loop to the speed control loop to improve stability against steady loads, but this method consists of two control loops: the speed control loop and the phase control loop. Since the operations of the two control loops influence each other, adjustment becomes difficult and the configuration becomes complex.Furthermore, the operating point shifts due to changes in ambient temperature or aging of components, resulting in a loss of synchronization range. There are various problems such as a decrease in

The present invention provides a motor speed control device that can solve the above-mentioned conventional problems. below,
The present invention will be explained based on illustrated embodiments. FIG. 1 is a main part block diagram showing one embodiment of the present invention. In the figure, 1 is a speed-controlled motor such as a brushless DC motor, 2 is a frequency generator that generates a signal with a frequency proportional to the number of rotations of the motor 1, and 3 is for shaping the output waveform of the frequency generator 2. This is a waveform shaping circuit. 4 is a reference frequency signal generation circuit for generating a stable frequency like the output of a crystal oscillator. 5 uses the fall of the output signal of the waveform shaping circuit 3 as a trigger signal, and is set to "1" while counting N output pulses (N is an integer) of the reference frequency signal generation circuit 4, which is a clock signal. A first constant pulse width generation circuit consisting of an N-ary counter that maintains the level and becomes "O" level after completing N counts; 6 is the falling edge of the output signal of the constant pulse width generation circuit 5; is used as a trigger signal, and remains at "1" level while counting M clock signals (output pulses of reference frequency signal generation circuit 4) (M is an integer), and becomes "0" level after counting M clock signals. This is a second constant pulse width generation circuit composed of an M-adic counter such that . 7 is the first constant pulse width generating circuit 5
and a pulse synthesis circuit for synthesizing the output pulses of the second constant pulse width generation circuit 6 and converting the output pulses into a pulse width corresponding to the speed error of the motor 1; 8 smoothing the pulse-like output of the pulse synthesis circuit 7; 9 is a low-frequency compensation circuit for amplifying the low frequency components (including DC) of the output of the filter circuit 8; 10 is for power amplifying the output of the low-frequency compensation circuit; This is a motor drive circuit. Note that the first constant pulse width generation circuit 5 and the second
The constant pulse width generation circuit 6 and the pulse synthesis circuit 7 constitute a speed error detection circuit 11.

The motor 1, frequency generator 2, waveform shaping circuit 3, speed error detection circuit 11, filter circuit 8, low frequency compensation circuit 9 and motor drive circuit 10 described above
and constitute a speed control loop.

FIG. 2 is a diagram showing a specific configuration example of the speed error detection circuit 11. In the figure, 21 is an N-ary counter having a clock input terminal CK, an output terminal, and a clear terminal CL, and 22 is a signal input to point B. 23 is a reset/set flip-flop (hereinafter abbreviated as RS flip-flop) circuit that performs reset and set operations using a "0" level trigger signal.

Initially, the RS flip-flop circuit 23 is “0”
Assuming that the Q terminal is at “0” level in the state, B
When a signal is input to the point, the signal is differentiated by the differentiating circuit 22, and the output sets the RS flip-flop circuit 23 to the "1" state, thereby bringing the Q terminal to the "1" level. Q terminal is N-ary counter 2
Since it is connected to the CL terminal of 1, the N-ary counter 21 is cleared (reset) and the CK
Start counting the clock pulses input to the terminal (point A), and at the moment when N clock pulses have been counted, the terminal changes from the "1" level.
0" level, and resets the RS flip-flop circuit 23, changing its internal state to "0".
state, and then keep the Q terminal at the "0" level until a new signal is input to point B. That is, using the input signal to point B as a trigger, the clock pulse period τ
and the time determined by the product Nτ of the number of counts N.
1” level first constant pulse width generation circuit 5
Configure.

The contents of the second constant pulse width generation circuit 6 are the same as the first constant pulse width generation circuit 5 except that the count number N is changed to M.

24 and 25 are OR circuit and AND circuit, 26, 27
are PNP transistor 30 and NPN transistor 3
A resistor 28 and 29 are used to supply current to the base of transistor 1, and resistors 28 and 29 are used to prevent leakage current from each transistor.

The above OR circuit 24, AND circuit 25, resistor 26,
27, 28, 29 and transistors 30, 31
The pulse synthesis circuit 7 is configured such that the G point is in the following three states. That is, when both points C and F in the figure are at the "1" level, the transistor 30 is turned off and the transistor 31 is turned on, resulting in a current sink mode, and both points C and F are at the "0" level. level, the transistor 30 is on and the transistor 31 is off, which is the current blowout mode, and when the levels at point C and point F do not match, the transistor 30,
It has a three-state state in which both of 31 are turned off, resulting in a so-called high impedance mode.

Figures 3, 4, and 5 show time charts during operation of this embodiment. Figure 3 shows when the motor is too fast, Figure 4 shows when the motor is too slow, shows the case where the motor is rotating steadily. Symbols B, C, F, and G in those drawings correspond to the symbols in FIGS. 1 and 2.

In the case of FIG. 3, it is assumed that the output frequency of the frequency generator 2 (frequency at point B) is ₁ . The period τ of the clock pulse at point A and the count number N of the N-ary counter and the M-ary counter that constitute the first constant pulse width generation circuit 5 and the second constant pulse width generation circuit 6
and M are constant, and are set to satisfy the following relationship: Nτ + Mτ = 1/o (1) (where o is the output frequency of frequency generator 2 when motor 1 is in steady rotation) τ ₁ = (N + M) τ-1/ ₁ = 1/o-1/ ₁ ...
...For the period of the value of (2), both point C and point F are at the "1" level, so point G enters the current sink mode and sucks current from the filter circuit 8.
The output frequency of the frequency generator 2 is lowered by lowering the output voltage of the frequency generator 2 and slowing down the rotational speed of the motor 1 via the low frequency compensation circuit 9 and the motor drive circuit 10.

If the motor in Figure 4 is too slow, and the output frequency of frequency generator 2 is ₂ , then τ ₂ = _1/2 − (N+M) τ = 1/ ₂ − 1/o...
...Since both point C and point F are at the "0" level during the period of the value of (3), point G is in current blowout mode,
Current flows into the filter circuit 8 to increase the output voltage of the filter circuit 8, passes through the low frequency compensation circuit 9 and the motor drive circuit 10, increases the rotation speed of the motor 1, and attempts to raise the output frequency of the frequency generator 2. .

When the motor 1 shown in FIG. 5 is rotating at a steady speed, there is no period during which both points C and F are at the same level, so both transistors 30 and 31 continue to be off, resulting in a high impedance state. , there is no current flowing in or out at point G, and the filter circuit 8
The output voltage of is kept constant. As a result, the rotation speed of the motor 1 is also kept constant.

As is clear from the above explanation, in a constant speed state, if the output frequency of the frequency generator 2 is _G , it can be seen that the relationship 1/ _G = (N + M) τ (4) always holds true.

Figure 6 shows how to adjust the rotation speed of motor 1.
3 is a diagram showing an example of the configuration of a variable pulse width generation circuit 41 to be replaced with the first constant pulse width generation circuit 5 described above. FIG. In the figure, 22 and 23 are the differential circuit and the RS flip-flop circuit described above. 42
is a preset counter consisting of various gate circuits of a programmable counter with a preset input terminal, and when it finishes counting the value set in binary at the preset input terminal, "" is output from the terminal.
It is configured to output a 0" level output.4
3 is a setting circuit for presetting the preset counter 42, which is connected to a plurality of switches 4.
4 and a plurality of resistors 45 for providing a "1" level.

The preset input terminals of the preset counter 42 correspond to digits 2 ⁰ , 2 ^{1 ,} .

If this configuration is adopted, as explained in the time charts of Figs. 3 to 5, the speed will always be controlled and stabilized in the state shown in Fig. 5, that is, the relationship of equation (4) above will hold. It works like this, so
Operate the switch 44 to set the preset counter 42.
When the count number N of is changed, the frequency generator 2
The output frequency _G , that is, the rotation speed of the motor 1 can be changed.

In the above explanation, the case where N of the first constant pulse width generation circuit 5 is made variable has been explained, but even if M of the second constant pulse width generation circuit 6 is made variable, both N and M may be changed. Even if it is made variable, the same function can be provided.

FIG. 7 shows an example of the configuration of an active filter consisting of an operational amplifier 51, resistors 52 and 53, a capacitor 54, and a reference power supply 55, which operates as the low-frequency compensation circuit 9. As shown in the frequency characteristic shown in FIG. 8, this operates such that the gain increases as the frequency range decreases, and by incorporating it into the speed control loop, the amount of feedback increases as the frequency decreases.

9 and 10 are graphs showing examples of motor control characteristics, and A and B in FIG. 9 are torque disturbance frequency-speed fluctuation characteristics without and with the low-frequency compensation circuit 9, respectively. C and D in FIG. 10 are graphs showing the load torque-speed change characteristics with and without the low-frequency compensation circuit 9, respectively.

This is because the amount of feedback in the control system increases as the frequency range decreases, and in the DC region it becomes practically infinite (determined by the bare gain of the operational amplifier 51).
As shown by D in Figure 0, within the control range, the speed change is almost zero no matter what the load torque is, and the characteristics are almost the same as when phase control is applied.

As is clear from the above description, the present invention has a number of excellent features as follows.

(1) Even though it is a single-loop control circuit with only a simple speed control loop, it is possible to have almost the same load characteristics as when phase control is applied, and as a result of the above, Unlike when phase control is applied, the operating points of the speed control loop and phase control loop do not interfere with each other.
This also eliminates fluctuations in the circuit's operating point due to changes in ambient temperature or aging of components.

(2) Since speed error detection is performed digitally, no detection errors other than bit errors occur, and by using a stable frequency signal such as the output of a crystal oscillator as a clock pulse, the rotational speed of the motor can be determined. The stability and accuracy can be comparable to that of a crystal oscillator.

(3) The output terminal of the speed error detection circuit (output of the pulse synthesis circuit) has three states: current sink mode, current blowout mode, and high impedance mode. At constant speed, it becomes stable in high impedance mode. There is no current flowing in or out, so ripples and the like do not occur, and even if the time constant of the filter circuit 8 is made small, smooth control can be achieved.

(4) Even if you change the count number of the counter that makes up the speed error detection circuit in order to adjust the rotation speed, the output terminal of the speed error detection circuit automatically enters the high impedance mode and becomes stable, so the operating point cannot be adjusted. There is no need for

(5) Since the speed error detection circuit can be configured entirely with digital circuits, it is suitable for IC implementation such as IIL or C-MOS, and does not require external capacitors, etc. unlike speed error detection circuits using conventional sampling methods. As a result, costs can be reduced.

[Brief explanation of drawings]

FIG. 1 is a main block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a speed error detection circuit that can be used in the present invention, and FIGS.
The figure is a time chart during operation of the speed error detection circuit, Figure 6 is a diagram showing a configuration example of a variable pulse width generation circuit that can be used in the present invention, and Figures 7 and 8 are examples of a low frequency compensation circuit. The figure shown, its frequency characteristic diagram, and FIGS. 9 and 10 are characteristic diagrams for explaining an example of the characteristic improvement effect according to the present invention. 1... Motor, 2... Frequency generator, 3... Waveform shaping circuit, 4... Reference frequency signal generation circuit,
5, 6... Constant pulse width generation circuit, 7... Pulse synthesis circuit, 8... Filter circuit, 9... Low frequency compensation circuit, 10... Motor drive circuit, 11... Speed error detection circuit.

Claims (1)

[Scope of Claims] 1. A motor, a frequency signal generating means for generating a frequency signal proportional to the number of rotations of the motor, a waveform shaping means for shaping an output signal waveform of the frequency signal generating means, and a clock pulse generating means. From the rising or falling point of the output signal of the reference frequency signal generating means and the waveform shaping means, the clock pulses generated by the reference frequency signal generating means are
a first constant pulse width generating means configured to maintain a first level while counting N pulses (N is an integer) and change to a second level after counting N pulses;
The first level is maintained while counting M clock pulses (M is an integer) generated by the same reference frequency signal generating means as described above from the rising or falling point of the output signal of the first constant pulse width generating means. a second constant pulse width generating means configured to hold the pulse width at a second level after counting M pulses; and an output signal of the first constant pulse width generating means and the second constant pulse width generating means. When the two input signals are both at the first level, the output signal is in the first state, and when both the input signals are at the second level, the output signal is in the second state. pulse synthesizing means for generating an output signal of a state and, when the two input signals are at different levels, an output signal of a third state; filter means for smoothing the output signal of the pulse synthesizing means; low-frequency compensating means composed of a low-pass filter for amplifying low-frequency components including direct current in the output signal of the filter means; and amplifying the output signal of the low-pass compensating means and supplying power to the motor. 1. A motor speed control device comprising a motor drive means for controlling the speed of a motor. 2. In claim 1, it is provided that the first and second constant pulse width generating means have a clock pulse count input terminal, a count output terminal, and a reset input terminal, and generate clock pulses corresponding to the respective count numbers. A counter for counting, a differentiating circuit for detecting the rising or falling edge of a trigger signal input from the outside, and two signals, an output signal of the counter and an output signal of the differentiating circuit, as input signals, and the output thereof. 1. A motor speed control device comprising a reset/set flip-flop circuit connected such that a signal resets said counter. 3. In the statement of claim 1 or 2, the count number of at least one of the counters constituting the first constant pulse width generating means and the second constant pulse width generating means is programmable. A speed control device for a motor, comprising a programmable counter, and the programmable counter can be controlled by external settings. 4. In any one of claims 1, 2, or 3, the three states of the output signal of the pulse synthesis means are "0" level, "1" level, and "high impedance" level. , and the third
The output signal of the state is set to a "high impedance" level, and the output signal of the first state and the output signal of the second state are set to different logic levels from each other except for the "high impedance" level among the three levels. A speed control device for a motor.