JPS6160623B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code distortion adding device that adds code distortion to a data signal or the like by changing the pulse width.

Generally, the received signal received through the transmission line is distorted compared to the original transmitted signal. In a receiving circuit that receives a signal containing such code distortion and reproduces the original transmission signal, an allowable distortion is often defined as a limit to prevent erroneous reproduction. To measure this allowable distortion, a distortion adding device is required that can add arbitrary distortion to the signal given to the receiving circuit. A conventional strain applying device of this type is shown in FIG. When a received signal to which distortion as shown in FIG. 2A is to be applied is applied to the input terminal 1, it is integrated in the integrating circuit 2, resulting in a triangular wave as shown in FIG. 2B. The reference voltage V _IN /2 (FIG. 2D) of the reference voltage generation circuit 4 is set in proportion to the distortion value set by the distortion setting switch circuit 3. This set reference voltage VW/2 and the output triangular wave signal of the integrating circuit 2 are applied to the comparison/discrimination circuit 5, and the magnitude of the signal voltage of the triangular wave signal is compared and discriminated with respect to the reference voltage VW/2, as shown in FIG. A discrimination signal as shown in is outputted to the output terminal 6.

At this time, if the signal voltage of the received signal applied to input terminal 1 is V _IN volts, and the reference voltage is 1/2 of the received signal voltage, the discrimination signal at output terminal 6 is equal to the signal applied to input terminal 1. The signal will be the same and no distortion will be added. Next, when this reference voltage is made larger than 1/2, the discrimination signal at output terminal 6 has a longer zero level range as shown in Figure 2 F, and the waveform is more negatively distorted than the received signal applied to input terminal 1. becomes. Conversely, if the reference voltage is made smaller than 1/2, the output terminal 6
The discrimination signal has a waveform that is more positively distorted than the received signal A, as shown in FIG. 2G. As described above, by changing the reference voltage applied to the comparison/discrimination circuit 5, the input terminal 1
Positive or negative distortion is added to the received signal.

In the configuration shown in FIG. 1, the integration circuit 2, comparison/discrimination circuit 5, reference voltage generation circuit 4, etc. are constituted by analog circuits, so there is a drawback that there are many adjustment points for variations in the characteristics of the components.
Further, the reference voltage generating circuit 4 is important in determining the distortion rate, and as the accuracy of the distortion rate is increased by increasing the accuracy to 10% increments, 5% increments, 1% distortion, etc., the range of voltage change becomes smaller. Therefore, the reference voltage generation circuit 4 has 1/2 of the input voltage.
The circuit must be configured to allow changes of 0, 1/100, and 1/200, which makes the circuit complicated, and
As mentioned above, since it is an analog circuit, there are many adjustment points and it is complicated. Moreover, since the comparison/discrimination circuit 5 only discriminates the magnitude of the input triangular wave signal with respect to the reference voltage, the reference voltage must be single, and distortion of only either positive or negative
The drawback was that only blocking bias distortion (regular distortion) could be added.

The purpose of this invention is that conventional analog circuits require adjustment points to compensate for variations in the characteristics of components, etc., and that the circuit becomes complex and large in order to reduce the increments of distortion and increase accuracy. Eliminates the drawback of being able to add only positive or negative bias distortion, makes it possible to easily reduce the distortion rate increments without requiring any adjustment points, and adds irregular distortion in addition to bias distortion. It is an object of the present invention to provide a strain adding device that can be miniaturized.

According to this invention, a change point of a received data code signal such as an NRZ code is detected by a change point detection circuit,
The up-down counter is preset by the detection output, and the R-S flip-flop is also set. The first and second gate circuits are controlled by the outputs of the R-S flip-flop with opposite polarities, and the clock signals that have passed through the first and second gate circuits are sent to the up-down counter as an up clock and a down clock, respectively. Supplied. R-S by up-down counter output
When the flip-flop is inverted and the count contents of the up-down counter match the set value of the distortion setting switch circuit, an output is generated from this switch circuit, and by this output, the received code signal is sampled and held in the first sampling circuit, and its The sampling output is sampled and held by the second sampling circuit based on the output of the switch circuit. The mutually corresponding outputs of the output terminals of the first and second sampling circuits are logically ANDed, and one of the logical products is taken out as a distorted output.

FIG. 3 shows an embodiment of the code distortion adding device according to the present invention, and the input terminal 1 is connected to a receiving signal change point detection circuit 7 and a flip-flop circuit 8. The detection signal of the change point detection circuit 7 is sent to an R-S flip-flop circuit 9 and an up-down counter 11.
supplied to Clock signal input terminal 12 is connected to gate circuits 13-15. Gate circuit 13
and 14 are also connected to the output side of the R-S flip-flop circuit 9, and the clock signal applied to the up-down counter 11 is controlled by this output. The output of the up-down counter 11 is connected to the distortion setting switch circuit 3.
The output of is applied to the gate circuit 15. The output clock signal of gate circuit 15 is applied to the clock input terminals of flip-flop circuits 8 and 16.
The output sides of flip-flop circuits 8 and 16 are connected to gate circuits 17 and 18, respectively. Switching circuit 19
switches the output of the gate circuit 17 or 18 and outputs it to the output terminal 6.

The operation of the strain adding device constructed as above will be explained with reference to the time chart of FIG. 4. When a received signal with equal element length, that is, no sign distortion, as shown in FIG. 4A is applied to the input terminal 1, the changing point detection circuit 7 detects both the rising and falling changing points of the received signal. , a detection signal as shown in FIG. 4B is output. This change point detection signal is applied to the set input of the R-S flip-flop circuit 9.
is set. R as shown in Figure 4 D and E
Since the output terminal Q of the -S flip-flop circuit 9 is in the 1 state and the output terminal is in the 0 state, the gate circuit 13 is closed, and conversely, the gate circuit 14 is opened. The detection signal of the change point detection circuit 7 is sent to the up/down counter 11
This counter 11 is set to an initial value. A clock signal from clock signal input terminal 12 that is N times the received signal at terminal 1 (Figure 4C)
When adding , the R-S flip-flop circuit 9 is set and the output terminal Q is in the 1 state, so
A clock as shown in FIG. 4G is applied to the down clock input D of the up-down counter 11, and the up-down counter 11 is counted down by one from the initial value. When this counter 11 counts down and reaches the count "0", a reset signal is applied to the R-S flip-flop circuit 9,
The R-S flip-flop circuit 9 is inverted. Output terminal Q of the inverted flip-flop circuit 9
Since is in 0 state and is in 1 state, the down clock that has been applied to up-down counter 11 through gate circuit 14 is blocked, but conversely, since the output terminal becomes 1 state, up-down counter 11 is applied through gate circuit 13 An upclock is added as shown in FIG. 4F. By this up-clock, the up-down counter 11 is incremented by one from count "0" as shown in FIG. 4H.

The output of the up-down counter 11 is also applied to the distortion setting switch circuit 3. This distortion setting switch circuit 3 is set with a reference value corresponding to the distortion rate of the distortion desired to be added, and when the counted output H of the up-down counter 11 that is input matches this reference value, as long as the count output H matches this reference value, Pulses are output as shown in FIG. 4I. This output signal pulse is applied to the gate circuit 15, gated with the clock signal from the terminal 12, and after the half wave of the clock signal is selected (FIG. 4J), it is applied to the clock input cl of the flip-flops 8 and 16. It will be done. In flip-flop 8, the received signal from input terminal 1 is sent to gate circuit 1.
When the output of the up-down counter reaches the set value of the circuit 3 during down-counting, the output goes into the 1 state and has a waveform as shown in FIG. 4K. Next, the sampled received signal is sampled again by the clock signal from the gate circuit 15 in the flip-flop 16, thereby obtaining a waveform delayed by one cycle of the output pulse of the gate circuit 15, as shown in FIG. 4L. Both positive outputs and both inverted outputs of the received signals sampled by the flip-flop circuits 8 and 16 are applied to an AND gate 17 and an OR gate 18, respectively. The AND gate 17 to which the positive outputs of both flip-flop circuits 8 and 16 are added outputs a negatively distorted signal as shown in FIG. A positively distorted signal like this is output. This distorted signal with both positive and negative polarities is added to the switching circuit 19, and a switching signal as shown in FIG. At the terminal 6, it is possible to obtain a received signal with only positive distortion added, a received signal with only negative distortion added, or a received signal with positive and negative distortion added randomly, as shown in Figure 4P. can.

It is then applied to a distortion adding device, and if the signal is already distorted, the distortion is added. Generally, the allowable distortion of a receiving circuit is 50% or less. Therefore, when distortion is added to a signal, unless the added distortion is 50% or less, the receiving circuit cannot correctly reproduce the original transmitted signal. The operation when a signal as shown in FIG. 5A in which each element length is not necessarily equal, that is, a signal with sign distortion is applied to the input terminal 1 in FIG. 3 will be explained using the time chart in FIG. 5. In FIG. 5, waveforms corresponding to those in FIG. 4 are given the same reference numerals. The input signal in FIG. 5A is composed of a normal portion a, a shortened portion b, an elongated portion c, and a portion d twice the normal length. Since the normal operation is the same as that shown in FIG. 4, the explanation will be omitted here. When the received signal becomes shorter, the changing point of the falling edge of the received signal is detected by the changing point detection circuit 7, and the up/down counter 11 is set to the initial value. Also, the R-S flip-flop circuit 9 is set, and a down clock is applied from the gate circuit 14 to the up/down counter 11. Therefore, this counter is counted down sequentially until the fifth
When the count reaches “0” as shown in Figure H, R-S
A reset signal is applied to the flip-flop circuit 9, the R-S flip-flop circuit 9 is reset, the down clock from the gate circuit 14 is blocked, and the up clock from the gate circuit 13 is applied to the up/down counter 11, which sequentially counts up. However, since the received signal is short, a change point in the received signal is detected before the up-down counter 11 reaches a full count, and the up-down counter 11 is set to the initial value by the detected signal. The output of the up-down counter 11 is applied to the distortion setting switch circuit 3, and when it matches the set distortion value,
While they match, a pulse is output (Figure 5),
After the clock and gate are removed by the gate circuit 15, the signal is applied to the flip-flops 8 and 16 to sample the input signal. Both the positive and negative outputs of the flip-flops 8 and 16 are applied to the gate circuits 17 and 18, and a signal with both positive and negative polarity distortion is taken out. At this time, if the received signal is shortened by nearly 50%, the distortion value is set so that the total distortion when the distortion is added by the distortion adding device becomes 50% or less.

Next, if it becomes longer like part c in Figure 5A,
The up-down counter 11 counts up and when the count is completed, the full count output is R-
It is applied as a set signal to the S flip-flop circuit 9, the R-S flip-flop circuit 9 is set, the up clock from the gate circuit 13 is blocked, and the down clock from the gate circuit 14 is applied to the up/down counter 11 to count down again. If a change point is detected in the received signal at that time, the up-down counter 11 returns to its initial value and continues counting down. At this time, if the received signal becomes nearly 50% longer, the distortion value is set so that the sum of distortions when added by the distortion adding device becomes 50% or less.

As described above, whether the input signal is distorted and becomes shorter or longer, as long as the added distortion is kept below 50%, the sampling pulses applied to flip-flops 8 and 16 will always be 2 It will be added twice. In addition, when the length is twice as long as in part d of FIG. 5A, the normal operation is repeated twice.

Since the clock signal applied to the clock terminal 12 is N times the received signal, the distortion step width that can be added is 2/N. Therefore, this clock signal is set to 20 times and 200 times the received signal, and the up-down counter 1
By simply making it possible to count from 1 to 10 to 100, the step width of the added distortion can be easily reduced without any adjustment.

Conventional distortion adding devices require many adjustment points because they are comprised of analog circuits, but the distortion adding device of the present invention does not require any adjustment points since it is comprised entirely of digital circuits.

In addition, in order to increase the accuracy by reducing the step width of the added distortion, the variation range of conventional reference voltage generation circuits became minute, making the circuit complex and requiring many adjustment points, which hindered the miniaturization of the circuit. In the device of the invention, by increasing the speed of the clock signal applied to the clock input terminal 12 and increasing the count value of the up-down counter 11, the distortion step size can be easily reduced without requiring any adjustment parts, thereby making the circuit more compact. things become possible.

In conventional distortion adding devices, only a single reference voltage is applied to the comparison/discrimination circuit, so only bias distortion of either positive or negative polarity can be added to the received signal.
In this invention, the received signal is sampled by flip-flops 8 and 16 according to the counting state of the up-down counter 11 set by the distortion setting switch circuit 3, and then the AND gate 17 and the OR gate 1 are sampled.
8, a signal with both positive and negative polarity distortion is obtained.By switching this with the switching circuit 19, in addition to bias distortion (regular distortion) with either positive or negative polarity, random A received signal to which positive and negative distortion is added (irregularly) is obtained. Therefore, the drawback of being able to add bias distortion of only a single polarity is eliminated.

As explained above, the present invention is constructed entirely of digital circuits, and therefore does not require any adjustment points. Also, when reducing the step size of the added distortion, increase the speed of the clock signal and increase the speed of the up-down counter 1.
This can be easily achieved simply by increasing the count value of 1, so the circuit can be made smaller. Conventionally, there was a drawback that only unipolar bias distortion could be added, but in addition to unipolar bias distortion, random distortion can also be added.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing a conventional strain adding device.
Fig. 2 is a time chart showing the circuit operation of Fig. 1, Fig. 3 is a block diagram showing an example of the distortion adding device according to the present invention, and Fig. 4 shows a received signal equal to the length of each element and without sign distortion being input. FIG. 5 is a time chart showing the circuit operation of FIG. 3 in the case where the lengths of each element of the input signal are not necessarily equal and there is sign distortion. 1: Input terminal, 2: Output terminal, 3: Distortion setting switch circuit, 7: Change point detection circuit, 9: R-S flip-flop, 11: Up-down counter, 1
2: Clock signal input terminal, 13 to 15: Gate circuit, 17: AND gate, 18: OR gate,
8, 16: D-type flip-flop circuit, 19: switching circuit.

Claims (1)

[Claims] 1. A changing point detection circuit that detects a changing point of a received code signal, an R-S flip-flop circuit controlled by the detection output thereof, and an output of the R-S flip-flop circuit with mutually opposite polarity. first and second gate circuits each controlled and supplied with a clock signal; and the outputs of the first and second gate circuits are supplied as an up clock and a down clock, respectively, and are preset by the change point detection circuit. an up-down counter that supplies the output as an inverted control signal to the R-S flip-flop circuit, and a distortion setting switch that outputs an output when the count of the up-down counter equals a set value and can change the set value. a first sampling circuit that samples the received code signal using the output of the distortion setting switch circuit; a second sampling circuit that samples the sampling output of the first sampling circuit using the output of the distortion setting switch circuit; First,
An AND gate that takes the logical product of the outputs of the second sampling circuit, and an OR gate that takes the logical sum of the signals obtained by inverting the outputs of the first and second sampling circuits, and the output of the AND gate or the OR gate is controlled by a switching signal. and a switching circuit for selecting one of the outputs of the code distortion adding device.