JPS60164966A - Information reproducing device - Google Patents

Abstract

PURPOSE:To reduce the number of externally attached circuit parts and to reduce temperature drift and secular change by constituting the device to generate a strobe pulse synchronizing with a reproduced digital signal to ward the direction opposite to the direction of fluctuation of a threshold value due to a glitch generated by a D/A converter. CONSTITUTION:A strobe pulse generating device 15 generates strobe pulse synchronizing with a reproduced digital signal. A strobe pulse is formed after a fixed time from rising edge of the reproduced digital signal. As leading edge of the reproduced digital signal is formed when the reproduced signal crosses a threshold value from negative to positive, if the fixed time is shorter than minimum inversion intervals of the reproduced digital signal, the strobe pulse is generated only when the level of the reproduced signal is higher than the threshold value, and the output of a D/A converter 16 changes synchronizing with this. Accordingly, even if the threshold value is changed by a glitch in the negative direction of the D/A converter 16, no hazard is generated in the reproduced digital signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an information reproducing apparatus for reading information from an information recording carrier on which a digital signal is recorded, and in particular, to an information reproducing apparatus for reading information from an information recording carrier on which a digital signal is recorded, and in particular to an information reproducing apparatus for reading information from an information recording carrier on which a digital signal is recorded. The present invention relates to an information reproducing apparatus having a duty ratio control means that allows correct information to be read even in different cases.

Structure of a conventional example and its problems FIG. 1 shows a block diagram of a duty ratio control means in a conventional information reproducing device, in which 1 is a comparator, 2 is a low-pass filter, 3 is a differential amplifier, and 4 is a block diagram of a duty ratio control means in a conventional information reproducing device. is the reference voltage generator.

The operation will be explained below with reference to the drawings.

Generally, when irregular information is appropriately digitally modulated, the probability of occurrence of logic 0 and logic 1 is approximately 60%.

In addition, even in the case of information in which Q or 1 continues, if it is digitally modulated so that the probability of appearance of logic Q and logic 1 is 50% each, in most cases, the modulated signal will contain logic 0 and logic 1. appear with equal probability. Examples of such digital modulation methods include FM, PF, and MF.
M. etc. are known. Examples of information that can be considered irregular include digitized music signals. There is also a digital modulation method in which the probability of appearance of logic O and logic 1 is equal for any information, regardless of regularity or irregularity. In this way, logic 0 and logic 1 appear with equal probability, in which case the cumulative time of logic 0 and logic 1
The integrated times should be approximately equal. Therefore, if the comparator 1 performs waveform shaping using an appropriate threshold value for the reproduced signal HFf, a reproduced digital signal similar to the original digital signal can be obtained, and the DC component of this reproduced digital signal is approximately equal to the voltage of logic O and the voltage of logic 1. It becomes an intermediate voltage. However, if the threshold value shifts, the voltage of the DC component of the reproduced digital signal shifts. Therefore, the above intermediate voltage is generated by the reference voltage generator 4.
The error in the threshold value of the comparator 1 is detected by comparing the low frequency component extracted from the output signal of the comparator 1 with the voltage generated by the reference voltage generator 4 through the low-pass filter 2. can do. Therefore, by amplifying this error with the differential amplifier 3 and feeding it back to the threshold of the comparator 1, it is possible to control the comparator 1 to correctly shape the waveform. However, in such a configuration, since the low-pass filter 2 includes elements such as a capacitor,
When an integrated circuit is used, there are disadvantages in that external circuit components are required, and there are also disadvantages in that temperature drift and changes over time are likely to occur.

Purpose of the Invention The present invention eliminates the above-mentioned drawbacks by controlling the duty ratio digitally, and makes it possible to accurately and stably read information even from a reproduced signal with a changed duty ratio. be.

Structure of the Invention The information reproducing apparatus of the present invention comprises a waveform shaping means capable of waveform shaping a reproduced signal read from an information recording carrier on which the digital signal is recorded to obtain a reproduced digital signal, and a threshold value of the reproduced signal; a strobe pulse generating means that generates a strobe pulse in response to a signal; a clock generator that generates a clock at a cycle sufficiently shorter than the length of the element waveform of the digital signal; A first counting means controlled by a signal, a second counting means that performs forward counting or backward counting according to the counted number of the first counting means, and a counting number of the second counting means as described above. A latch means for holding in response to a strobe pulse, and a digital/analog conversion means (for converting the output of this latch means into an analog voltage)
(hereinafter referred to as D/A conversion means), and this D/A conversion means.
The output signal of the D/A conversion means is fed back to the threshold value of the waveform shaping means, and the pulse generation means is configured to feed back the output signal of the D/A conversion means to the threshold value of the waveform shaping means, and furthermore, the slobe knock pulse generation means operates in a direction opposite to the direction in which the threshold value fluctuates due to the glitch generated by the D/A conversion means. The device is configured to generate a strobe pulse in synchronization with the rising edge or falling edge of the reproduced digital signal generated when the reproduced signal crosses the threshold value in the direction of the reproduction signal. Information can be read accurately even if the duty ratio of the sensor deviates, there is almost no temperature drift or change over time, and when an integrated circuit is used, the number of external circuit components is extremely small.

DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 shows a block diagram of a duty ratio control means according to an embodiment of the present invention. In Figure 2, 1
0 is a waveform shaping means, 11 is a clock generator, 12 is a first
13 is a second counting means, 14 is a latch means, 16 is a strobe pulse generating means, 16 is a D
/A converter. FIG. 3 is a signal waveform diagram of each part of the above embodiment, and (a) to (f) in the figure correspond to each point a + f in FIG. 2.

The operation of the duty ratio control means of this embodiment configured as shown in FIG. 2 will be explained with reference to the signal waveform diagram of FIG. 3. Reproduction signal H as shown in Figure 3 (turtle)
When F is waveform-shaped by the waveform-shaping means 10 with a threshold value of S, a reproduced digital signal as shown in FIG. 3(b) is obtained. If the level of this threshold value S is not appropriate, the average length of the logic 0 and logic 1 length of the reproduced digital signal will be different. Therefore, the clock generator 11 generates a clock φ1 having a cycle sufficiently shorter than the cycle of the element waveform of the recorded digital signal as shown in FIG. By counting, a shift in the duty ratio can be detected by comparing the count number when the logic is 0 and the count number when the logic is 1. If a shift in the duty ratio is detected instantaneously in this way, the second counting means 13 performs forward counting or backward counting in response to this, and the count value becomes as shown in FIG. 3(d). Change. If a closed loop is configured such that this count value is D/A converted by the D/A converter 16 and fed back to the threshold value of the waveform shaping means 10, the duty ratio can be controlled to be correct.

However, D/A converters generally generate glitches when the input signal changes, and require a certain amount of time for the output signal to settle. The launch means 14 and the strobe pulse generation means 15 are for eliminating the influence of such glitches.

Next, its operation will be explained. It is relatively easy to configure a D/A converter so that the above-mentioned glitch always occurs in a constant direction. For example, a D/A converter that outputs only positive voltage usually generates a glitch in the negative direction. do.

In this embodiment, it is assumed that the D/A converter 16 always generates glitches in the negative direction. The strobe pulse generating means 15 generates a strobe pulse in synchronization with the reproduced digital signal, and in this embodiment, the strobe pulse is generated after a certain period of time from the rising edge of the reproduced digital signal. As is clear from FIGS. 3(a) and 3(b), the rising edge of the reproduced digital signal is generated when the reproduced signal crosses the threshold from negative to positive. If the strobe pulse is shorter than the minimum inversion interval of /A
The output of converter 16 changes synchronously.

Therefore, even if the threshold value fluctuates due to a glitch in the negative direction of the D/A converter 16, it is possible to prevent a hazard from occurring in the reproduced digital signal. Conversely, if the D/A converter 16 always generates a glitch in the positive direction, if the strobe pulse is generated a certain period of time after the falling edge of the reproduced digital signal, the reproduced digital signal can prevent hazards from occurring.

Next, the present invention will be explained in more detail with reference to specific circuit examples.

FIG. 4 shows a circuit diagram of the first counting means 12 and the second counting means 130 in an embodiment of the present invention, where 20 is a first reversible counter, 21 is a second reversible counter, and 22 is an OR Gate, 23 is NAND gate, 24
is an AND gate, and 26 and 26 are inverters.

The operation will be explained below. In the following description, a logic 0 is a low potential and will be referred to as a level L, and a logic 1 is a high potential and will be referred to as a level H. The first reversible counter 2o and the second reversible counter 21 switch between forward counting and backward counting.
When the reproduced digital signal is at level H, the clock φ1 is counted forward, and when the reproduced digital signal is at level L, it is counted backward in the same way.

Now, if the duty ratio of the reproduced digital signal is large and the time at level H is longer than the time at level L, the first reversible counter 2o will increase the count number on average and output a carry signal. Occurs at terminal C. This carry signal C is input to the input terminal RC of the second reversible counter 21 as a ripple clock. In the case of the present example, this carry signal C is normally generated in the state of forward counting, so the second reversible counter 21 also counts this ripple clock and increases the count number. This second reversible counter 21
The above-described shift in duty ratio can be improved by D/A converting the output signals qi, q+, and Qk and using this as a threshold value. Further, when the digit signal C from the first reversible counter 2o is output, this carry signal C is delayed by the inverters 26 and 26 and is applied to the input terminal 1, so that the first reversible counter 20 Qa+QblQOIQd+Qe.

Qf, Qg and l: and Qh are respectively Or Or O+
0.

Preset to 0.0.0 and 1. As a result, due to the high frequency components of the reproduced digital signal, the output signal Qi
, Qj and Qk can be prevented from chattering.

Also, an OR gate 22, a NAND gate 23 and an
The D gate 24 acts as a limiter for the second reversible counter 21 and prevents the second reversible counter 21 from carrying up and counting backwards from 0, thereby increasing the duty ratio of the reproduced digital signal. It is possible to prevent the count value of the second reversible counter 21 from circulating and the control to become unstable even when there is a deviation.

FIG. 6 shows a circuit diagram of the first counting means in another embodiment of the present invention, in which 3o is a D flip-flop;
31 is an XOR gate, 32 and 33 are NAND gates, 34 is an AND gate, and 36 is an inverter. In this embodiment, when the reproduced digital signal (X) is inverted, the two input signals of the IOR gate 31 become equal, and the output becomes level L. This allows AND gate 3
The output of the AND gate 32 of the RS flip-flop consisting of the RS flip-flops 2 and 33 becomes H level. Hereinafter, this state will be referred to as the seven-node state of the RS flip-flop, and the reverse will be referred to as the reset state. When the RS flip-flop is set in this way, one input of the AND gate 34 becomes level H, so the output of the AND gate 34 changes in accordance with the carry signal from the other input, the reversible counter. . Therefore, the second reversible counter counts this as a ripple clock. Furthermore, if this carry signal C is a pulse in the positive direction, the RS flip-flop is reset by this, and the carry signal C continues until the RS flip-flop is reset by the state reversal of the reproduced digital signal. The ripple clock is no longer transmitted to the second reversible counter. By doing so, even when a dropout occurs in the reproduced signal and there is no long open state reversal, it is possible to prevent the delay time control means from swinging too much and making the control unstable.

FIG. 6 shows a specific circuit diagram of the waveform shaping means, strobe pulse generation means, latch means, and D/A converter in the embodiment of the present invention, where 40 is an inverter, 41
is an AND gate, and 42 is a D flip-frog.

The operation will be described below with reference to the same figure.

In the same figure, inverter 40, two resistors R1, resistor RO
and capacitor C constitute waveform shaping means. After the DC component of the reproduced signal (HF) is removed by a capacitor C, a DC bias is applied by a resistor H, and the signal is input to an inverter 4o. Furthermore, since the output of the D/A converter 16 is also applied as a bias via the resistor Rc, the D/A converter 16
By changing the input signal to the A converter 16, the DC bias can be changed. Also inverter 4o
has a predetermined threshold value, so by changing the DC bias in this way, the threshold value of the waveform shaping means 10 can be substantially changed. On the other hand, AND gate 41 and D flip-flops 42 and 43 constitute strobe pulse generating means. If the D flip-flops 42 and 43 are driven by the clock signal φ2, the clock signal φ that appears next to the rising edge of the reproduced digital signal
D flip-flop 42 by the rising edge of 2
The output Q of is at level H. At this time, if the output Q of the D flip-flop 43 is also held at a high level and the signal changes, the D/A converter 16 generally generates a glitch and then settles to a predetermined analog value. If the n/A converter 16 outputs only positive voltage and generates only glitches in the negative direction, the glitch simply shifts the threshold of the waveform shaping means 10 in the negative direction. Since the signal is at a level higher than the threshold, the effect of the glitch does not appear on the reproduced digital signal. Therefore, there is no need for an analog switch or a low-pass filter to remove the glitch.

Note that the waveform shaping means, first counting means, and strobe pulse generating means in the present invention are not limited to the above embodiments, and may have any configuration as long as they have similar functions. do not have. For example, the waveform shaping means can use a comparator, and the first counting means includes two counters: one that counts the clock φ1 when the reproduced digital signal is at level H, and the other that counts the clock φ1 when the reproduced digital signal is at level L.
It is also possible to use two counters, reset them to 0, and then compare the counts within a certain period of time.Also, the strobe pulse generation means can also be configured by other logic circuits, and the reproduced digital signal can be directly generated. The D flip-flops 42 and 43 can be omitted if a reproduced digital signal delayed from another source can be obtained instead of using a strobe pulse immediately after the rising edge of the reproduced digital signal with almost no delay. Although a hazard may occur near the rising edge of the reproduced digital signal, it hardly affects the reading of information, so the D flip-flops 42 and 43 in FIG. 6 can be omitted.

Effects of the Invention As is clear from the above description, the present invention provides waveform shaping means for obtaining a reproduced digital signal by shaping the waveform of a reproduced signal read from an information recording carrier on which the digital signal is recorded, and having a variable threshold value. , a strobe pulse generating means that generates a strobe pulse in response to the reproduced digital signal, a clock generator that generates a clock at a cycle sufficiently shorter than the length of the element waveform of the digital signal, and a clock generator that counts the clock and operates the clock. is controlled by the reproduction digital signal, a second counting means that performs forward counting or backward counting according to the count number of the first counter 714 stage, and this second counting means. a latch means for holding the count number of according to the strobe pulse, and a D/A converter means for converting the output of the latch means into an analog voltage, and converts the output signal of the D/A converter into an analog voltage. Further, the strobe pulse generating means generates a strobe pulse when the reproduced signal crosses the threshold in a direction opposite to the direction in which the threshold changes due to a glitch generated by the D/A converting means. Since the strobe pulse is generated in synchronization with the rising or falling edge of the reproduced digital signal, all processing can be done digitally, and when integrated circuits are used for this purpose, The advantage is that the number of external circuit components can be reduced, and temperature drift and changes over time can also be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a duty ratio control means in a conventional information reproducing apparatus, FIG. 2 is a block diagram of a duty ratio control means in an embodiment of the present invention, and FIG. 3 shows signals of each part in the above embodiment. A waveform diagram, FIG. 4 is a specific schematic diagram of the first counting means and second counting means in the above embodiment, and FIG. 5 shows another example of the first counting means that can be used in the present invention. FIG. 6 is a specific circuit diagram of a waveform shaping means, a strobe pulse generating means, a latch, and a D/A converter in an embodiment of the present invention. 10... waveform shaping means, 11... riO
Tsuku generation lobe pulse generation means, 20.21...
・Reversible counter, 22...OR gate, 23.
32.33...NAND gate, 24,34.
41...AND gate, 25, 26, 36.4
0...Inverter, 31==-X OR gate, 30.42. 43==・D flip-flop. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 30 Day 4 Figure 5

Claims (1)

[Claims] Waveform shaping means for obtaining a reproduced digital signal by waveform shaping a reproduced signal read from an information recording carrier on which the digital signal is recorded, and a waveform shaping means having a variable threshold value, and a strobe according to the reproduced digital signal. a strobe pulse generating means for generating pulses; a clock generator for generating a clock at a cycle sufficiently shorter than the length of the element waveform of the digital signal; and a clock generator that counts the clock and whose operation is controlled by the reproduced digital signal. a first counting means; a second counting means for forward counting or backward counting according to the count number of the first counting means; and a second counting means for counting forward or backward counting according to the count number of the first counting means; It has latch means for holding, and digital/analog conversion means for converting the output of the launch means into an analog voltage,
7 Jōguchi 6 −+ + The output signal of the digital/analog converting means is fed back to the threshold of the waveform shaping means, and the strobe pulse generating means is configured to feed back the output signal of the digital/analog converting means in the opposite direction to the direction in which the threshold changes due to the glitch generated by the digital/analog converting means. An information reproducing apparatus characterized in that a strobe pulse is generated in synchronization with a rising edge or a falling edge of a reproduced digital signal generated when the reproduced signal crosses the threshold value in the direction.