JP2638337B2 - Error counter circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal error counter circuit.

[0002]

2. Description of the Related Art A conventional error counter circuit will be described with reference to FIGS. FIG. 3 is a circuit diagram of an error counter circuit that detects m (m is a plurality of) error pulses E, and FIG. 4 is a diagram showing a timing chart of the circuit of FIG.

The error counter circuit includes an OR gate 32 for ORing an error pulse E and a clock signal F, and m flip-flop circuits (F / F) 31 connected in cascade.
a, 31b, 31c, ..., 31m (31m is the m-th F
/ F) (hereinafter F / F31a-3)
1 m is generally referred to as F / F 31). F
/ F31 is a synchronous D flip-flop circuit having a set terminal S, a clock terminal C, a data input terminal D, and an output terminal Q.

The error counter circuit is a circuit that counts m error pulses E during a time T. It is assumed that the time T is sufficiently longer than the generation time of the m error pulses E. First, at time t1, F / Fs 31a to 31
m are all set by the TIME pulse G input to the reset terminal S, and the signals b, c, d,... output from the output terminals Q, and the counter output H are at the “H” level.

Next, at time t2, the clock signal F
Is input to one input terminal of the OR gate 32. Note that the clock signal F is always input to the other input terminal of the OR gate 32. The OR gate 32 outputs the toggle a by taking the OR gate of the error pulse E and the clock signal F. The toggle a is input to all the clock terminals C of the F / F 31. When an error pulse E for the first time since the F / F 31 is set is input at time t2, the F / F 31a
Reads the "L" level always input to the data input terminal D by the toggle a, and outputs the "L" level as the signal b from the output terminal Q. At this time, the remaining F /
The output terminals Q of F31b to 31m hold the "H" level because the data input terminals D are at the "H" level.

The data input terminals D of the F / Fs 31b to 31m are connected to the output terminal Q of the preceding F / F 31. That is, the data input terminal D of the F / F 31b is connected to the F / F
31a, the signal b from the output terminal Q is input, and the F / F3
The data input terminal D of 1c is connected to the output terminal Q of F / F 31b.
, The signal d from the output terminal Q of the F / F 31c is input to the data input terminal D of the F / F 31d, and the F / F 31 is input to the data input terminal D of the F / F 31m.
The signal (m-1) from the output terminal Q of (m-1) is input.

Subsequently, at time t3, the error pulse E
Is input, the F / F 31b shifts the “L” level signal b input from the F / F 31a and outputs an “L” level signal c from the output terminal Q. At time t4 when the “L” level error pulse E is continuously input, the toggle “a” is output, and the F / F 31c shifts the signal “c” to output the “L” level signal “d” from the output terminal Q. Is done. Thus, the cascade-connected F / F 31 is
Each time the error pulse E is input to the OR gate 32,
The “L” level signal is shifted to the subsequent stage F / F 31.

When m error pulses E are input at time t5 within the time T after the input of the TIME pulse G, the F / F 31m, which is the m-th stage F / F, outputs "L" from the output terminal Q. A level counter output H is output, and it is detected that m error pulses E have been input to the error counter circuit.

At time t6 after a lapse of T time from the TIME pulse G previously input at time t1, the next TIME pulse G is input, all the F / Fs 31 are set, and m error pulses E are counted again. Ready.

[0010]

In this conventional error counter circuit, a toggle of a half time slot of a clock signal is generated by an OR gate of an error pulse and a clock signal, so that a spike is easily generated in the toggle. However, there is a drawback that there is a high possibility of malfunction due to spikes.

Further, when the clock signal has a high frequency, an OR gate operating at a high speed is required, and there is a disadvantage that power consumption is increased.

[0012]

An error counter circuit according to the present invention comprises m error pulses held by m (m is a plurality of) cascade-connected error pulse holding circuits which are reset every predetermined measurement time. Wherein the first stage of the error pulse holding circuit is reset with a control signal inputted every measurement time as a reset signal, and the first stage of the error pulse inputted after the reset is reset. A circuit which changes the level of the output signal by being set by the first and the input of the clock signal; and the second and subsequent stages of the error pulse holding circuit,
Reset and release of the reset are performed using the logical product of the control signal and the output signal of the previous-stage error pulse holding circuit as a reset signal, and the error pulse and the clock signal input after the release of the reset are set by the clock signal. This is a circuit that changes the level of the output signal.

In a preferred embodiment, each of the error pulse holding circuits has a reset terminal for inputting the reset signal, a clock terminal for inputting the clock signal, a data input terminal, an output terminal, and an inverted output terminal. A flip-flop circuit having one input terminal for inputting the error pulse, another input terminal connected to the inverted output terminal, and a NAND gate having an output terminal connected to the data input terminal. The error pulse holding circuits of the second and subsequent stages further include an AND gate which takes the logical product of the control signal and the output signal of the preceding error pulse holding circuit and uses the logical product as the reset signal.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of an error counting circuit according to the present invention. FIG. 2 is a diagram showing a timing chart of the embodiment of FIG.

This error counter circuit counts m error pulses G during a certain time T as in the conventional example. The error counter circuit includes m cascade-connected error pulse holding circuits 1a, 1a,
1b, 1c,..., 1m (hereinafter, error pulse holding circuit 1
a, 1b, 1c,..., 1m are generally referred to as an error pulse holding circuit 1).

Each of the error pulse holding circuits 1 has F /
F11 and a NAND gate 12 (hereinafter, the F / F11 belonging to the error pulse holding circuit 1a is the F / F11
a, the NAND gate 12 is represented by the same suffix as the error pulse holding circuit, such as the NAND gate 12a). The F / F 11 is a synchronous D flip-flop circuit having a reset terminal R, a clock terminal C, a data input terminal D, an output terminal Q1, and an inverted output terminal Q2. One input terminal of the NAND gate 12 is connected to F /
F11 is connected to the inverted output terminal Q2, and the output terminal is F /
It is connected to the data input terminal D of F11. F / F1
The clock signal F is input to the clock terminal C of N.
An error pulse E is input to the other input terminal of the AND gate 12.
Is entered.

The reset terminal R of the F / F 11a belonging to the first-stage error pulse holding circuit 1a is reset by a TIME pulse E. The reset terminals R of the F / Fs 11b to 11m belonging to the second and subsequent error pulse holding circuits 1b to 1m are connected to the AND gate 2b which receives the signal output from the output terminal Q1 of the preceding F / F1 and the TIME pulse G as inputs.
2c,..., ２2 m (hereinafter, AND gates 2b, 2c,
, 2m is generally referred to as an AND gate 2). The inverted output terminal Q2 of the F / F 1m belonging to the error pulse holding circuit 1m
Outputs the counter output H.

First, at time t1, when a TIME pulse E is input, each error pulse holding circuit F / F11
Directly to all reset terminals R or AND gate 2
, The F / F 11 is reset, and the signal output from the output terminal Q1 is set to the "L" level. That is, the output terminal Q of the F / F 11a
1 and the output terminal Q1 of the signal f, F / F11b
K, the signal r output from the output terminal Q1 of the F / F11c, and the signal (m-1) output from the output terminal Q1 of the F / F11 (m-1) have the "L" level. Then, the counter output H output from the inverted output terminal Q2 of the F / F 11m is set to the “H” level. As described above, when the first TIME pulse E is input, F / F1
(1) Since the signals output from all the output terminals Q1 are at the "L" level, the F / Fs 1b to 1m are inhibited until the signal output from the output terminal Q1 of the preceding F / F11 changes to the "H" level ( Reset). Further, while the error pulse E is at the “H” level after the TIME pulse G is input, the F / F input through the NAND gate 12a is used.
The input signal to the data input terminal D of F11 is at "L" level. Therefore, during this period, the input signal e to the data input terminal D of the F / F 11a is at "L" level,
The signal f output from the output terminal Q1 and the signal g output from the inverted output terminal Q2 are maintained in the reset state.

At the time t2, when the error pulse E goes to the "L" level for the first time, in the error pulse holding circuit 1a, the signal e output from the NAND gate 12a changes to the "H" level, and the F / F 11a outputs the signal e. Is toggled at the rising edge of the clock F after the level change of F / F1
The signal f output from the output terminal Q1 of FIG.
The signal g output from the inverted output terminal Q2 changes to "L" level. When the signal g goes low, the signal f goes high.
The F / F 11a is fixed to the level, and the F / F 11a is in a state equivalent to the state where the set state is maintained regardless of the state of the error pulse E thereafter.

When the signal f output from the error pulse holding circuit 1a goes high, the signal j output from the AND gate 2b goes high, and the F / F 11b belonging to the error pulse holding circuit 1b is reset. It is released. At this time, the signal h output from the NAND gate 12b outputs an "H" level signal of a half clock signal period,
11b is not toggled, so the signal k output from the output terminal Q1 and the signal p output from the AND gate 2c
Does not change and remains at the “L” level.

At time t3, when the next error pulse E is input, the reset of the F / F 11b is released, so that the signal r input from the NAND gate 12b to the data input terminal D becomes "H" level. F / F11b
Can maintain the same state as the set state at the next toggle.
Here, the error pulse holding circuit 1b and the AND gate 2b
It can be seen that the complete error pulse holding circuit of the second stage is constituted by the pair. Simultaneously with the signal r attaining the "H" level, the signal p output from the AND gate 2c attains the "H" level, and the reset of the F / F 11c is released.

At time t4, if the reset of the F / F 11c is released also when an error pulse E having a continuous "L" level is generated, the signal n input to the data input terminal D of the F / F 11c becomes "T". H ”level, F /
The signal r output from the output terminal Q1 of F11c becomes "H" level at the next rising edge of the toggle.

As described above, the time t within the time T
5 receives the m-th error pulse E, the counter output H output from the inverted output terminal Q2 of the F / F 12m belonging to the error pulse holding circuit 1m becomes "L" level, and the m error pulses E are output. The pulse E is counted and held. As a result, it is detected that m error pulses E have been input to the error counter circuit.

When the time T has elapsed from the time t1, the next TI
The ME pulse G is input, all the F / Fs 11 are reset, and the error pulse E can be counted again.

[0025]

As described above, the error count circuit according to the present invention uses the clock signal as it is as the toggle of the F / F, so that no malfunction occurs due to spikes generated by processing the clock signal. Has an effect.

Further, A used in the error counting circuit
As the ND gate or the NAND gate, a device having a speed corresponding to the operation speed determined by the toggle of the F / F can be selected, so that there is an effect that a gate with low power consumption can be used.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart of the embodiment of FIG.

FIG. 3 is a circuit diagram of a conventional error counter circuit.

FIG. 4 is a diagram showing a timing chart of the error counter circuit of FIG. 3;

[Explanation of symbols]

1 (1a to 1m) Error pulse holding circuit 2 (2b to 2m) AND gate 11 (11a to 11m) Flip-flop circuit (F
/ F) 1212a to 12m) NAND gate 31 (31a to 31m) Flip-flop circuit (F
/ F) 32 OR gate E error pulse F clock signal G TIME pulse H count output a toggle b ~ h, j ~ k, n, p, r signal

Claims (2)

(57) [Claims] 1. An error counter circuit for detecting m error pulses by means of an error pulse holding circuit connected in cascade, wherein m (m is a plurality of) error pulses are reset every predetermined measurement time. The first stage of the pulse holding circuit is reset by using a control signal input every measurement time as a reset signal, and is set and output by the first error pulse input after the reset and the input of the clock signal. A circuit for changing a signal level, and in the second and subsequent stages of the error pulse holding circuit, resetting and canceling the reset are performed by using a logical product of the control signal and the output signal of the preceding error pulse holding circuit as a reset signal. Is performed and set and output by the error pulse and the clock signal input after the reset is released. An error pulse counting circuit, which is a circuit for changing a level of a force signal. A flip-flop circuit having a reset terminal for inputting the reset signal, a clock terminal for inputting the clock signal, a data input terminal, an output terminal, and an inverted output terminal; A NAND gate having one input terminal for inputting the error pulse, the other input terminal connected to the inverted output terminal, and an output terminal connected to the data input terminal; The pulse holding circuit is
Further, the AND of the control signal and the output signal of the error pulse holding circuit at the preceding stage is used as the reset signal.
2. The error pulse counting circuit according to claim 1, further comprising a D gate.