JP2643470B2 - Synchronous counter - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous counter, and more particularly, to a synchronous counter configured by combining a flip-flop and a logic gate.

[Conventional technology]

Since all the outputs of the synchronous counter change in synchronization with the clock pulse, the output of the synchronous counter differs depending on each stage, and is very useful in terms of the configuration of the digital circuit, as compared with an asynchronous counter in which the delay increases in later stages.

For example, taking a four-stage synchronous counter as an example, a circuit as shown in FIG. 4 is known as a basic first example of the circuit.

This circuit is composed of JK flip-flops 11, 12, 13, and 14, two-input AND gates 21, and three-input AND gates 31, and J terminals, K, of the third and fourth stages of JK flip-flops 13, 14.
Terminals are 2-input NAD gate 21 and 3-input NAD gate respectively.
The preceding JK flip-flop 11,1 calculated by 31
2, the logical product of the output signals of 11 to 13 is input, the J terminal and the K terminal of the first-stage JK flip-flop 11 are fixed to the high level of the power supply voltage V _CC , and the second-stage JK flip-flop 12 The output of the first-stage JK flip-flop 11 is directly input to the J terminal and the K terminal. Also, each JK flip-flop 11-14
The clock pulse CK of the circuit is commonly applied to the CLK terminal.

 Next, the operation of this circuit will be described below.

The outputs of the JK flip-flops 11 to 14 are inverted when the levels of the J terminal and the K terminal are high, and maintain the previous output state when the levels are low. Also, in a counter, a stage is inverted when all stages preceding it are at a high level, so that a counter can be constructed by applying the logical product of all the previous stages to the J and K terminals. Also, since the outputs of the JK flip-flops 11 to 14 change in synchronization with the clock pulse CK, the circuit described above operates as a synchronous counter. Generally, the circuit of the Nth stage is JK
A flip-flop and an (N-1) input AND gate for inputting the logical product of the outputs of the JK flip-flops of the first to (N-1) th stages to the J terminal and the K terminal.

Also, as in the second conventional example shown in FIG.
The operation of the logical product of the inputs to the terminals can be constituted by cascade-connected two-input AND gates 21 and 22, and this circuit operates on the same principle as the first conventional example.

[Problems to be solved by the invention]

In the first conventional example described above, at the Nth stage,
The logical product from the first stage to the (N-1) th stage is calculated (N-
1) Since an input AND gate is required, increasing the number of stages increases the fanout in the previous stage. In particular, the fanout of the first stage is (N + 1) when the J terminal, K terminal and the fan out of the AND gate are equal. However, if the carry signal waveform to the subsequent stage becomes dull or delayed, and the master-slave type is assumed as the flip-flop, if this delay becomes larger than 1/2 of the clock cycle, the carry signal will not be transmitted to the subsequent stage normally and the counter will not be transmitted. Therefore, there is a disadvantage that the clock frequency at the limit becomes lower as the number of stages of the counter increases.

Further, in the second conventional example, the fan-out of each stage can be suppressed to a maximum of 3 even if the number of stages is increased.
Since the gates are connected in cascade, a delay of N times the transmission delay time of one two-input AND gate occurs between the change in the level of the clock signal and the change in the level of the carry signal in the Nth stage. This delay time is expressed as [ts + (N−2) tpd], where ts is the setup time of the JK flip-flop and tpd is the transmission delay time of the AND gate.
If it is larger than 1/2, there is a disadvantage that it cannot operate normally.

As described above, in the conventional example, when a multi-stage synchronous counter is configured, there is a problem that an operable clock frequency is reduced.

An object of the present invention is to solve the above-mentioned problems and to provide a multi-stage synchronous counter capable of operating at higher speed.

[Means for solving the problem]

The synchronous counter according to the present invention includes a first-stage flip-flop that inputs a signal of a predetermined level to an input terminal and performs a binary counting operation according to a clock pulse, and the first-stage flip-flop input to an input terminal according to a clock pulse. A second-stage flip-flop for inverting the level of the output data in accordance with the first level of the acquired data, inputting the signal of the predetermined level to an input terminal, and following the clock pulse A third-stage binary counter flip-flop that performs a binary counting operation, and a third-stage AND that calculates the logical product of the output data of the binary counter flip-flop and the output data of the second-stage flip-flop A gate, and fetching output data of the AND gate according to the clock pulse, according to a first level of the fetched data. A third-stage flip-flop for inverting the level of force data; and an n-th stage (n is an integer of 4 or more, hereinafter the same) for inputting a signal of the predetermined level to an input terminal and performing a binary count operation in accordance with the clock pulse. ) And (n−1) th logical product data of the binary counter flip-flop and the output data of the flip-flops of the second to (n−2) th stages and the (n−1) th logical product data. 1) a first AND gate of the n-th stage which takes a logical product of the output data of the flip-flops of the stage and outputs it as the logical product data of the n-th stage; and the logical product data of the n-th stage and the n-th stage An n-th stage second AND gate for performing an AND operation with the output data of the binary counter flip-flop; and taking in the output data of the n-th stage second AND gate in accordance with the clock pulse. The first level of Depending on and a flip-flop of the first n stages of inverting the level of the output data.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing one embodiment of the present invention.

This embodiment shows a four-stage synchronous counter, and the input terminal J
The first-stage JK flip-flop 11 that inputs the power supply voltage V _CC to the terminal and the K terminal and performs a binary count operation according to the clock pulse CK, and the J-terminal and the K terminal of the input terminal when the clock pulse CK goes high. When the output data OUT1 of the input first-stage JK flip-flop 11 is taken and the clock pulse CK goes low, the second-stage JK inverts the level of the output data OUT2 according to the high level of the taken data. The third step of inputting the power supply voltage V _CC to the flip-flop 12 and the J and K terminals and performing a binary counting operation in accordance with the clock pulse CK.
JK flip-flop 15 for the binary counter of the stage and this 2
When the clock pulse CK goes high and the third-stage two-input AND gate 21 that performs the logical product of the output data of the JK flip-flop 15 for the binary counter and the output data OUT2 of the second JK flip-flop 12 A third-stage JK flip-flop 13 for inverting the level of output data OUT3 according to the high level of the fetched data when the output clock of the two-input AND gate 21 takes the fetch clock pulse CK goes low.
The n-th stage in which the power supply voltage V _CC is input to the terminal and the K terminal and a binary count operation is performed in accordance with the clock pulse CK (n is an integer of 4 or more; however, in this embodiment, n is only 4; the same applies hereinafter).
And the logic of the output data OUT2 of the JK flip-flop 16 for the binary counter and the JK flip-flop 12 from the second stage to the (n-2) th stage (only n = 4, so only the second stage) The logical product data of the (n-1) th stage, which is the product, and the (n-
1) A first two-input AND gate 22 of the n-th stage which takes a logical product of the output data of the flip-flops of the stage and outputs it as logical product data of the n-th stage, and the logical product data of the n-th stage and the n-th logical product The second 2-input AND gate 2 of the n-th stage for performing a logical AND operation with the output data of the JK flip-flop 16 for the binary counter of the stage
3 and the second 2 when the clock pulse CK goes high.
Captures output data of input AND gate 23 and clock pulse C
When K goes low, the n-th stage JK inverts the level of output data OUTn according to the high level of the captured data.
The flip-flop 14 is provided.

In order to configure a synchronous counter having five or more stages, the circuit blocks shown in FIG. 2 may be connected in series at the stage subsequent to the fourth stage in the embodiment shown in FIG.

The third stage in FIG. 1 is a special case of the circuit block of FIG. 2 and the fourth stage is substantially identical to the circuit block of FIG. Since they are the same, the circuit block in FIG. 2 will be described.

The JK flip-flop used in the following is a master-slave type. Input data is read at the rising edge when the clock pulse CK goes high, and the clock pulse CK
The description will be made on the assumption that the output data level changes when the J terminal and the K terminal are at the high level at the fall when the signal goes low.

This circuit block is composed of JK flip-flops 14 and 16
It is composed of input AND gates 22 and 23.

Since the J terminal and the K terminal of the JK flip-flop 16 are connected to the high-level power supply voltage V _CC , the clock pulse C
The output is inverted at the falling edge of K and operates as a binary counter. The output is connected to one input terminal of a two-input AND gate 23.

The output data OUT2 from the second stage to the (n-2) th stage
AND (OUT) (n-1) is connected to one input terminal of the two-input AND gate 22 as AND data (OUT-1) of the (n-1) th stage. Column output data OU
T (n-1) is connected to the other input terminal. The output of the two-input AND gate 22 is connected to the other input terminal of the two-input AND gate 23, and from the second stage to the (n-1) th
The logical product of the output data OUT2 to OUT (n-1) up to the stage, that is, the logical product data AND OUTn of the nth stage is output to the next stage. Further, a clock pulse CK is connected to CLK terminals of the JK flip-flops 14 and 16.

This circuit block operation will be described with reference to the time charts of FIGS. 3 (a) and 3 (b).

Here, FIG. 3A shows a case where the logical product data AND OUT (n-1) of the (n-1) th stage is inputted almost at the same time as the falling edge of the clock pulse CK. The case where the clock pulse CK arrives slightly later than one clock cycle from the falling edge is shown. The logical product data AN
DOUT (n-1) is output from the second stage of the synchronous counter to the (n-
2) Since the logical product of the outputs of the stages is used, the logical value is constant for at least two clock cycles.

In FIG. 3 (a), the logical product data AND OUT (n-1)
The output (OUTn) of the JK flip-flop 14 is inverted at the falling edge of the clock pulse CK immediately after the output data OUT (n-1) goes high and the output of the JK flip-flop 16 goes high.

JK flip-flop 16 is the first stage of this synchronous counter.
Since the same operation as the JK flip-flop 11, the above operation corresponds to the occurrence of a carry at the next clock when all the output data up to the previous stage has become high level, and it is operating normally as a synchronous counter. Recognize.

Further, as shown in FIG. 3 (b), even if the logical product data AND OUT (n-1) changes by one clock cycle from the fall of the clock pulse CK to be changed due to the influence of the preceding stage, the JK flip-flop 14 does not change. Is determined by the rising edge of the clock pulse CK that reads the input data, that is, by the delay of 1.5 clock cycles,
Can be inverted, and can operate normally as a synchronous counter.

Next, the AND gate 2 of the data of the embodiment shown in FIG.
Considering the delay caused by 1 to 23, tpd is the maximum (N-2) tpd as the transmission delay time of the two-input AND gate, which is the same as that of the second conventional example, but a delay of 1.5 clock cycles is allowed. It is possible to operate at a clock frequency three times that of the second conventional example.

Also, the number of fan outs in each stage is only two 2-input AND gates, and there is no increase in fan-out due to the increase in the number of stages as in the first conventional example, and high-speed operation is possible.

Although the embodiment of the present invention has been described above, the flip-flop used for this synchronous counter is not limited to the JK flip-flop, and the present invention can be applied as long as the output is inverted by a carry signal from the preceding stage. Similar effects can be obtained. Also, if the AND gate is also logically equivalent, another OR
It is also possible to adopt a circuit configuration using a gate NAND gate, a NOR gate, or the like.

〔The invention's effect〕

As described above, according to the present invention, the circuit block of each stage after the third stage is provided with a binary counter flip-flop that performs a binary counting operation by a clock pulse and a logical product of output data from the second stage to the previous stage. And a flip-flop that receives the logical product of the output data of the binary counter flip-flop and the output data of the binary counter flip-flop and inverts the output data in response to the first level of the input data by a clock pulse, thereby providing a fan-out. Since there is no increase and the operation margin for the delay time of the carry signal can be made approximately three times that of the conventional case, the clock frequency can be increased and the speed can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG.
3A and 3B are circuit diagrams of the circuit blocks of each stage when the embodiment shown in the figure is further multiplied, and FIGS. 3A and 3B are for explaining the operation of the circuit block shown in FIG. 4 and FIG. 5 are circuit diagrams showing first and second examples of a conventional synchronous counter, respectively. 11-16: JK flip-flop, 21-23: 2-input AND
Gate, 31 ... A 3-input AND gate.

Claims (1)

(57) [Claims] A first-stage flip-flop for inputting a signal of a predetermined level to an input terminal and performing a binary counting operation in accordance with a clock pulse; and a first-stage flip-flop input to an input terminal in accordance with the clock pulse And a second-stage flip-flop for inverting the level of the output data in accordance with the first level of the captured data, and inputting the signal of the predetermined level to an input terminal and receiving the signal in accordance with the clock pulse. A third-stage binary counter flip-flop performing a binary count operation, and a third-stage AN that calculates the logical product of the output data of the binary counter flip-flop and the output data of the second-stage flip-flop.
A D-gate, a third-stage flip-flop for taking in output data of the AND gate in accordance with the clock pulse and inverting the level of output data in accordance with a first level of the taken-in data; An n-th stage (n is an integer of 4 or more, the same applies hereinafter) binary counter flip-flops that input a level signal and perform a binary counting operation in accordance with the clock pulse;
2) The logical product of the logical product of the output data of the flip-flops up to the (n-1) th stage and the output data of the flip-flop of the (n-1) th stage, which is the logical product of the output data of the flip-flops up to the stage, is calculated. A first AND gate of an n-th stage for outputting as AND data; and an n-th stage of an AND gate for performing an AND operation on the AND data of the n-th stage and the output data of the flip-flop for the n-th stage binary counter A second AND gate and an n-th stage for taking in output data of the n-th stage second AND gate in accordance with the clock pulse and inverting the level of the output data in accordance with a first level of the taken-in data; And a flip-flop.