JPH08212794A - Shift register - Google Patents

Abstract

PURPOSE: To improve such a situation that, when shift registers are connected in a multistage cascade manner, the speed of a clock cannot be made faster when a serial data output from a previous-state shift register to be input to a next-stage shift register to which a common clock signal is input, is delayed due to the delay of an inverter for buffer. CONSTITUTION: Up to the (n-1)st stage of (n) bits of shift registers which shift data at the rise of a clock signal CLK are constituted of ordinary D-type flip- flops 2, and the n-th stage is constituted of a master slave D-type flip-flop 3. Then, at a serial data output terminal QN, a master output MQ from the flip-flop 3 is taken out via a two-stage inverter 1. The master output MQ is output at the rise of an n-th clock signal CLK, it is made faster as compared with a conventional case in which a data output Qn from the last-stage D-type flip-flop used in the serial data output terminal QM is output at the fall of the n-th clock signal, and the delay of the inverter 1 is compensated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for a data transfer of an image display device or a device for converting serial data into parallel data, which is particularly used for a device requiring a high speed operation, and is composed of a semiconductor integrated circuit or the like. Regarding registers. In the drawings, the same reference numerals indicate the same or corresponding parts.

[0002]

2. Description of the Related Art First, a typical structure and operation of a conventional shift register of this type will be briefly described with reference to FIGS. FIG. 7 shows a shift register having a configuration in which D-type flip-flops 2 are cascade-connected in n stages. In this shift register built in a semiconductor integrated circuit, normally, input data (signal) passes from its input terminal D through a plurality of stages of an inverter 1 as an input buffer, and an input terminal D of a D-type flip-flop 2 of the first stage. The clock signal is input to the clock terminal CLK of the D-type flip-flop 2 of each stage (that is, n pieces) from the clock input terminal CLK of the shift register through the plurality of stages of the inverter 1 as an input buffer. Further, the serial output of the shift register is output from the output terminal Q (= Qn) of the D-type flip-flop 2 of the nth stage via the inverter 1 as an output buffer through a plurality of stages of the serial data output terminal QN of the shift register.

For example, in a shift register used in a scanning side driving device of a liquid crystal display device, a parallel data output terminal of the shift register drawn from each output terminal Q of the D-type flip-flops 2 from the first stage to the n-th stage. Q1-Q
A high voltage output circuit, which receives the output of n, is built in one chip. Generally, the number of scanning lines is several hundred, and the number of outputs of one scanning side driving device is not enough, so that a plurality of scanning side driving devices are connected in series.

Specifically, the serial data output terminal QN of the shift register of the first-stage driving device is connected to the data input terminal D of the next-stage driving device to form shift registers corresponding to the number of scanning lines. FIG. 8 shows the timing of the input and output signals of the shift register of FIG. For convenience of explanation, the terminal name is also used as the signal name of the terminal below. In this example, the data shift is configured to operate at the trailing falling edge of the clock signal CLK. The input data D of the shift register is sequentially shifted at the falling edge of the clock signal CLK, and the parallel data outputs Q1 to Qn of the shift register are output to the respective D-type flip-flops 2.
The output is delayed by the output delay time td1 from the falling edge of the clock input CLK. Since the serial data output QN of the shift register is obtained from the output terminal Qn of the final stage D flip-flop 2 via the output buffer 1, the output from the falling edge of the clock input CLK of the final stage D flip-flop is output. The delay becomes as large as td2.

When n-bit shift registers are connected in multiple stages, the serial data output QN of the first-stage shift register becomes the data input D of the second-stage shift register, and the (n + 1) th clock signal CLK falls. Are taken in and shifted in sequence.

[0006]

However, when it is used in an application where the data transfer frequency is high, the output delay time td of the serial data output QN of the first stage shift register is increased.
When 2 exceeds the cycle T1 of the clock signal CLK, the shift register in the second stage cannot properly take in the data.

It is therefore an object of the present invention to solve this problem and provide a shift register which can reduce the delay time of serial data output at low cost.

[0008]

In order to solve the above-mentioned problems, the shift register according to claim 1 shifts data by each edge input (falling edge or the like) at the rear end of a common clock (CLK). A flip-flop (2) connected in cascade in n stages, wherein the output data of the (n-1) th D flip-flop is shifted for each edge input at the front end of the clock at the nth stage. Then, a serial data output means for outputting to the serial data output terminal (QN) of this shift register is provided.

According to a second aspect of the present invention, in the shift register according to the first aspect, the serial data output means is a master / slave D-type flip-flop (3) together with the D-type flip-flop of the nth stage. And outputs the output data of the master section to the serial data output terminal.

According to a third aspect of the present invention, in the shift register according to the first aspect, the serial data output means is provided separately from the n-th stage D-type flip-flop (n-1). The output data of the D-type flip-flop of the second stage is input, and the common clock is inverted with an additional D-type flip-flop (2A) that outputs data to the serial data output terminal at the trailing edge input of the clock. Then, the inverter (1A) which is used as a clock input of the separately provided D-type flip-flop is provided.

A shift register according to a fourth aspect is the shift register according to any one of the first to third aspects, in which the output data of the D-type flip-flop of the nth stage and the output data of the serial data output means are provided. It is assumed that a means (AND-NOR circuit 4 or the like) for selectively outputting any one of the above is output to the serial data output terminal according to a selection signal (SEL).

A shift register according to a fifth aspect is the shift register according to any one of the first to fourth aspects, wherein at least the data input terminal of the D-type flip-flop in the first stage or the data output terminal of the serial data output means. Is provided with a buffer element (inverter 1 or the like).

Further, in the shift register according to claim 6, the shift register according to any one of claims 1 to 5 is:
It is configured by a semiconductor integrated circuit.

[0014]

The final stage of the shift register composed of n-stage D-type flip-flops is composed of master / slave D-type flip-flops, and the serial data output QN of the shift register.
Is taken out from the master output of the final stage master / slave D-type flip-flop, and the data taken in is output at the rising edge of the front end of the clock signal, or n of the shift register consisting of n-stage D-type flip-flops is output. A configuration in which the output of the D-type flip-flop of the (n-1) th stage is input to the stage and a D-type flip-flop that operates by an inverted signal of the clock signal is added, and the serial data output QN of the shift register is taken out from the output. Then, the added D-type flip-flop operates so as to fetch and output data at the rising edge of the clock signal.

[0015]

1 shows the structure of a shift register as a first embodiment of the present invention. In FIG. 1, the n-th D-type flip-flop 2 at the final stage is a D-type flip-flop 3 with an MQ output as a master / slave D-type flip-flop in FIG. 7, and the serial data output terminal QN of this shift register is From the master output terminal MQ of the D-type flip-flop 3 with the MQ output of the final stage, the two-stage inverter 1
It is different in that it is configured to be taken out through.

In FIG. 1, the data input terminal D of the shift register is input to the input terminal D of the first-stage D-type flip-flop 2 via the two stages of the inverter 1 as an input buffer, and the clock input terminal CLK of the shift register is input. It is commonly input to the clock input terminals CLK of n D-type flip-flops 2 and 3 of all stages through the inverter 1 as an input buffer via two stages.

FIG. 4 shows a D-type flip-flop 3 with an MQ output.
The circuit example of is shown. FIG. 5 is a timing chart of input / output signals of the flip-flop 3. There are several possible configurations of the D-type flip-flop 3 with MQ output, but in this example,
As shown in FIG. 4, a clocked inverter 5 and an inverter 1 are used as a master / slave type. The circuit of FIG. 4 is shown in FIG.
As shown in, in addition to the output terminal Q as a normal D-type flip-flop that outputs data at the falling edge of the input clock signal CLK, the input data is passed through in the H level section of the input clock signal CLK and the L level section is passed through. Has an output terminal MQ for holding the input data, that is, for outputting the data fetched at the rising edge of the input clock signal CLK, and this output terminal MQ takes out the output of the master section of the master / slave D-type flip-flop. There is.

FIG. 3 is a timing diagram showing the operation of the shift register of FIG. The parallel data outputs of the shift register of FIG. 1 are Q1 to Qn, and the clock signal CLK
It is output after a delay time of td1 from the falling edge of. The delay time td1 is extremely small due to the delay inside the shift register and does not greatly affect the frequency characteristics of the shift register, but since the serial data output QN of the shift register passes through the output buffer 1, the delay time td1 is equal to td2. Delay time becomes large. However, in the present invention, since the master output MQ is output at the rising edge of the nth clock signal CLK, the (n + 1) th clock signal (that is, the shift of the next stage) of the serial data output QN that has passed through the output buffer 1. Clock signal CL which the D-type flip-flop 2 at the first stage of the register should take in data CL
Reduce the output delay time as seen from the fall of K,
It will be improved. That is, the multi-stage connection operation of the shift register circuit is possible even in the clock cycle T1 that is shorter than the delay time td2.

When the frequency of the fast clock signal CLK is limited, the configuration shown in FIG. 1 may be used. However, at the slow clock frequency, the shift register in the second stage cannot receive the correct data. As shown in FIG. 2, AND- as a switch that can select whether to take the serial data output QN of the shift register from the output terminal MQ of the D-type flip-flop 3 with MQ output or from its normal data output terminal Q. The NOR circuit 4 is shown in FIG.
It may be added to the output section of the D-type flip-flop 3 with MQ output.

In FIG. 6, a D-type flip-flop 2A which operates by an inverted signal of the clock signal CLK is added to the n-th stage of the shift register composed of n-stage D-type flip-flops, and serial data of the shift register is output from its output terminal Q. An example of the configuration of an n-bit shift register configured to take out the output QN will be shown. In the figure, the signal inverted by the inverter 1A from the path of the clock signal CLK is input to the clock signal input terminal CLK, and the output signal Q (= Qn-1) of the (n-1) th stage D-type flip-flop 2 is output. A D-type flip-flop 2A for inputting to the data input terminal D is added,
Inverter 1 as an output buffer from its output terminal Q
Is connected to the serial data output terminal QN of the shift register via two stages. In this case, the D-type flip-flop 2
Since A takes in the output signal Qn-1 of the (n-1) th stage D-type flip-flop 2 as an inverted signal of the clock signal CLK, that is, at the nth rising edge of the clock signal CLK shown in FIG. Similar to the circuit configuration of No. 1, the delay time of the output QN of the shift register seen from the fall of the clock signal CLK is shortened, and the frequency characteristic when the shift registers are connected in multiple stages can be improved.

[0021]

According to the present invention, the output data of the D-type flip-flop of the preceding stage is output to the final stage of the shift register that shifts data at the trailing edge of the common clock signal at the trailing edge of the common clock signal. A master / slave D-type shift register as a means for inputting and shifting and outputting to the serial data output terminal of the shift register, or another D-type flip-flop for inverting a common clock signal and using it as a clock signal for itself is provided. Since a new shift register is configured as described above, the delay time of the data given to the D-type flip-flop of the first stage of the shift register of the next stage can be reduced.

Therefore, when the shift register according to the present invention is used to construct a drive device for an image display device, high frequency operation is possible when the drive device is connected in multiple stages. Also, in the manufacturing of the semiconductor device of the driving device,
Since it is not necessary to increase the operation speed of the shift register circuit portion by fine processing, the manufacturing cost is relatively low, and the manufacturing method that does not have a high circuit operation speed can be used.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a shift register as a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a shift register as a second embodiment of the present invention.

3 is a timing diagram of input / output signals of the shift register of FIG.

4 is an internal circuit diagram of the D-type flip-flop with MQ output shown in FIG. 1;

5 is a timing diagram of input / output signals of the flip-flop of FIG.

FIG. 6 is a circuit diagram of a shift register as a third embodiment of the present invention.

FIG. 7 is a conventional circuit diagram corresponding to FIG.

8 is a timing diagram of input / output signals of the shift register of FIG.

[Explanation of symbols]

 1, 1A Inverter 2, 2A D-type flip-flop 3 MQ-type D-type flip-flop 4 AND-NOR circuit 5 Clocked inverter SEL selection signal

Claims (6)

[Claims] 1. A shift register comprising n stages of cascaded D-type flip-flops for shifting data for each trailing edge input of a common clock, wherein each leading edge input of the clock is at the nth stage. To (n-
1) A shift register characterized by comprising serial data output means for shifting output data of the D-type flip-flop at the stage and outputting it to the serial data output terminal of this shift register. 2. The shift register according to claim 1, wherein the serial data output means constitutes a master / slave D-type flip-flop together with the n-th stage D-type flip-flop, and outputs the output data of the master section. A shift register for outputting to the serial data output terminal. 3. The shift register according to claim 1, wherein the serial data output means is provided separately from the n-th stage D-type flip-flop, and the (n-1) -th stage D-type flip-flop is provided. Of the separate D-type flip-flop for inputting the output data of the above and outputting the data to the serial data output terminal at the edge input of the rear end of the clock, and for inverting the common clock A shift register comprising an inverter for clock input. 4. The shift register according to claim 1, wherein either the output data of the D-type flip-flop of the nth stage or the output data of the serial data output means is selected. A shift register comprising means for selectively outputting to the serial data output terminal according to the above. 5. The shift register according to claim 1, wherein a buffer element is provided at least at a data input terminal of the D-type flip-flop in the first stage or a data output terminal of the serial data output means. Shift register characterized by. 6. A shift register according to any one of claims 1 to 5, wherein the shift register comprises a semiconductor integrated circuit.