JP2504949B2 - Shift register - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a shift register provided in an internal circuit of an LCD driver for driving an LCD display device or the like.

(Prior Art) Conventionally, as a technique in such a field, for example, there has been a technique as shown in FIG. 2 and FIG. Hereinafter, the configuration will be described.

FIG. 2 is a connection diagram in which a plurality of (n) -bit output shift registers of the related art are cascade-connected in n stages.

In general, when n shift registers 1-1 to 1-n are cascade-connected, the carry signal Ca output terminal of the first-stage shift register 1-1 is the second-stage shift register 1- 2 serial data D input terminals, and in the same manner, sequentially connected to the n-th shift register 1-n.

The shift registers 1-1 to 1-n of the respective stages respectively have an input terminal for serial data D, an input terminal for inputting a shift clock pulse φ, and an n-bit output signal 01-
It has an output terminal for outputting 0n and an output terminal for the carry signal Ca.

In the above configuration, the first stage shift register 1-1
Serial data D added to the shift register 1-1 at the leading edge of the clock pulse φ,
The serial data D read at the first clock is output signal 0n at the final stage of the shift register 1-1 at the nth clock.
Is output as In the first-stage shift register 1-1, the carry signal Ca is output at a timing such that the second-stage shift register 1-2 can take in data at the (n + 1) th clock. Then, the second stage seat register 1
-2 shifts the carry signal Ca of the first stage at the leading edge of the clock pulse φ similarly to the first stage. Thereafter, the same operation is sequentially performed up to the nth stage.

FIG. 3 is a circuit diagram of the n-bit shift register in FIG. This shift register includes a shift register body 2 and a clock pulse generation circuit 3.

The shift register body 2 includes an input buffer 10 for inputting serial data D and an n-stage serial master (main) clocked inverter 11 for sequentially shifting the serial data D1 input from the input buffer 10 to D2 to Dn. -1 to 11-n
And slave (slave) clocked inverters 12-1 to 12-
n and slave clocked inverters 12-1 to 12 of each stage
Output buffer 13-1 that outputs output signals 01 to 0n from the -2
~ 13-n and the final stage slave clocked inverter 12
Carry output buffer 14 that outputs carry signal Ca from -n
And it is comprised.

The clock pulse generation circuit 3 is a circuit for generating a master clock pulse φ1 and a slave clock pulse φ2 of two phases having opposite phases and different duties from the clock pulse φ for shifting the serial data D1. It is composed of a 2-input NAND (logical product NOT) gate 23, a 2-input NOR (logical NOT) gate 24, and an inverter 25. The master clock pulse φ1 is for each master clocked inverter 11-1 to 11-n, and the slave clock pulse φ2 is for each slave clocked inverter.
For 12-1 to 12-n, the normal inverting operation is performed at the H level, and the output side is set to the high impedance state at the L level, so that the inverters 11-1 to 11-
It has a function of causing n, 12-1 to 12-n to perform a data read operation.

Next, the operation of FIG. 3 will be described with reference to the timing chart of FIG. In FIG. 4, a time difference (so-called gap) is provided between the master clock pulse φ1 and the slave clock pulse φ2 so that the data does not run through, that is, racing does not occur. . This gap is
It is the amount of time added with the delay time of.

First, when the master clock pulse φ1 goes high, the first-stage master clocked inverter 11-1 fetches the serial data D1. When the master clock pulse φ1 becomes L level, the master clocked inverter 11-1
Output side becomes high impedance and serial data
Hold D1. Next, the slag clock pulse φ2 becomes L
When rising from the level to the H level, the slave clocked inverter 12-1 at the first stage takes in the serial data D1 and outputs the H level output signal 01 from the output buffer 13-1. After that, the same operation is repeated n times to sequentially output the output signal 0n up to n bits. Last stage output signal 0n
Is output from the output buffer 13-n, and at the same time, a carry signal Ca having the same waveform as the output signal 0n is output from the carry output buffer.
It is output from 14.

Here, the carry signal Ca is delayed by the time t1 when viewed from the rising edge of the clock pulse φ. This carry signal delay time t1 has a value obtained by adding the following delay times t2 and t3.

Delay time t2 = delay addition time of inverters 20, 21, 22 + delay time of 2-input NOR gate 24 delay time t3 = final stage slave clocked inverter 12-
Delay time of n + delay time of carry output buffer 14 (Problems to be solved by the invention) However, the shift register having the above configuration has the following problems.

Since the carry signal Ca is used as a data input signal of the shift register of the next stage, if the carry signal Ca is delayed by one cycle or more of the clock pulse φ, the shift register of the next stage cannot properly receive the data. , Cause a malfunction. Further, when a high-speed shift register capable of following the high-speed clock pulse φ of the output signals 01 to 0n is cascade-connected in plural stages, if the carry signal Ca of the shift register of each stage has a delay of, for example, 240 to 260 ns, Since the shift register of each stage can operate with a clock pulse φ of about 4 MHz, the maximum operating speed of each shift register is limited. Moreover,
If the carry signal Ca is delayed by more than one cycle of the clock pulse φ as described above, the shift register itself cannot be connected in cascade.

SUMMARY OF THE INVENTION The present invention provides a shift register that solves the problems of the above-mentioned prior art, such as malfunction due to delay of carry signal output and difficulty in high-speed operation.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides, in a shift register, for example, an input terminal to which serial data (D) is input, and a first clock signal (φ). , A clock generation circuit connected to the clock terminal, and n data holding circuits (51-1, 52-1 to 51-n, n connected in series from the input terminal). 52-
n) and the n data holding circuits (51-1, 52-1 to 51).
-N, 52-n) and n data output terminals respectively connected to the output side, and the n data holding circuits (51-1, 52-
1-51-n, 52-n), and a carry signal generating circuit (42) connected to the n-th data holding circuit (51-n, 52-n) from the input terminal.

Here, the clock generation circuit is based on the first clock signal (φ) and is delayed by a first period with respect to the first clock signal (φ).
A third clock signal (φ2) delayed by a second period longer than the first period with respect to the first clock signal (φ), and a third clock signal (φ2) It is a circuit for generating a fourth clock signal (φ1) having a substantially opposite phase. n data holding circuits (51-1, 52-1 to 51)
-N, 52-n) temporarily holds the serial data (D) input in response to the fourth clock signal (φ1) and responds to the third clock signal (φ2). And a circuit for outputting the held serial data (D). The carry signal generation circuit (42) responds to the third clock signal (φ2) by the serial data (D) held by the nth data holding circuit (51-n, 52-n). Before being output, the second clock signal (φ
3) is a circuit for generating a carry signal (Ca) based on the serial data (D) in response to 3).

(Operation) According to the present invention, since the shift register is configured as described above, the clock generation circuit causes the second clock signal (φ3) obtained by delaying the first clock signal (φ), and further the second clock signal (φ3). The third clock signal (φ2) delayed from the clock signal (φ3) is generated, and the third clock signal (φ2) is generated.
Generates a fourth clock signal (φ1) having a phase substantially opposite to that of the clock signal (φ2) and supplies the second clock signal (φ3) to the carry signal generation circuit (42).
The third clock signal (φ2) and the fourth clock signal (φ1) are supplied to n data holding circuits (51-1, 52-1 to 51-1).
-N, 52-n). Then, in the n data holding circuits (51-1, 52-1 to 51-n, 52-n), the input is made in response to the fourth clock signal (φ1) and the third clock signal (φ2). Serial data (D) input from the terminal is sequentially shifted.

Then, the serial data (D) held in the n-th data holding circuit (51-n, 52-n) is sent to the input side of the carry signal generating circuit (42). The carry signal generating circuit (42) outputs the second clock signal (φ3) before the serial data is output from the nth data holding circuit (51-n, 52-n) to the nth data output terminal. In response to the n
A carry signal (Ca) with a short delay time is generated and output from the serial data (D) held in the th data holding circuit (51-n, 52-n). Therefore, the above problem can be eliminated.

(Embodiment) FIG. 1 is a circuit diagram of an n-bit shift register showing an embodiment of the present invention. This shift register includes a shift register body 40 having a plurality of data holding circuits, a clock pulse generation circuit 41 having a clock generation circuit, and a carry signal generation circuit 42.

The shift register body 40 has an input buffer 50 for inputting the serial data D, and the serial data D1 input from the input buffer 50 is sequentially shifted to D2 to Dn on the output side of the input buffer 50. The serially connected master clocked inverters 51-1 to 51-n and the slave clocked inverters 52-1 to 52-n are connected. Each stage of the master clocked inverter and slave clocked inverter constitutes a data holding circuit of each stage. Slave clocked inverters 52-1 to 52- in each stage
Output buffers 53-1 to 53-n for outputting output signals 01 to 0n are respectively connected to the output side of n.

The clock pulse generation circuit 41 is a circuit that generates a master clock pulse φ1 and a slave clock pulse φ2 of two phases having opposite phases and different duties from the clock pulse φ for shifting the serial data D1. It is composed of a gate circuit. That is, the clock pulse generation circuit 41 has a first-stage gate circuit for inputting the clock pulse φ, for example, the inverter 60, and the inverter 60 is connected in series to the inverters 61, 62 and N.
One input side of the AND gate 63 is connected, and the output side of the inverter 62 is connected to one input side of the 2-input NOR gate 64. The other input side of each of the NAND gate 63 and the NOR gate 64 is connected to the output side of the inverter 60. An inverter 65 that outputs a master clock pulse φ1 is connected to the output side of the NAND gate 63, and the output side of the inverter 65 is a control input terminal of each master clocked inverter 51-1 to 51-n in the shift register body 40. It is connected to the. NOR gate 64 is slave clock pulse φ
2 is a gate that outputs 2 and its output side is each slave clocked inverter 52-1 to 52- in the shift register body 40.
n control input terminals. The master clocked inverters 51-1 to 51-n and the slave clocked inverters 52-1 to 52-n have their control input terminals at the H level for a normal inverting operation, and at the L level for the output side to be in a high impedance state. Switch.

An inverter 66 for generating a slave clock pulse φ3 is connected to the output side of the first-stage inverter 60 in the clock pulse generation circuit 41, and the slave clock pulse φ3 is supplied to the carry signal generation circuit 42.
The slave clock pulse φ3 is a clock pulse φ
→ Inverter 60 → Inverter 66 is generated by the route, and slave clock pulse φ2 is generated by the route of clock pulse φ → Inverter 60 → Inverters 61, 62 → NOR gate 64, so that pulse φ2 is delayed from pulse φ3. ing.

The carry signal generation circuit 42 is a circuit that generates a carry signal Ca and gives it as a shift register data input signal for the next stage, and is connected to the output side of the final stage master clocked inverter 51-n in the shift register body 40. Slave slave clocked inverter 70. The slave clocked inverter 70 has its control input terminal connected to the inverter 66 in the clock pulse generation circuit 41, and the output side of the inverter 70 connected to the output buffer 71 for outputting the carry signal Ca.

A feature of this embodiment is that an inverter 66 is provided in the clock pulse generation circuit 41 and a carry signal generation circuit 42 is newly provided.

Next, the operation of FIG. 1 will be described with reference to the timing chart of FIG.

The shift operation of the serial data D1 in the shift register body 40 is performed by the master clock pulse φ1 as in the conventional case.
And the slave clock pulse φ2 causes the master clocked inverters 51-1 to 51-n and the slave clocked inverters 52-1 to 52-n in each stage to output the serial data D1.
While shifting to D2 to Dn, the serial data D2 to Dn are output in the form of output signals 01 to 0n through the output buffers 53-1 to 53-n.

Here, the slave clock pulse φ3 in phase with the input clock pulse φ is output from the clock pulse generation circuit 41, and the slave clocked inverter 70 in the carry signal generation circuit 42 causes the slave clocked inverter 70 in the final stage master clock by this slave clock pulse φ3. It takes in the output of the inverter 51-n and outputs the carry signal Ca through the output buffer 71. Therefore, although the carry signal Ca is delayed by the time t11 with respect to the clock pulse φ, it is output at a timing earlier than the final stage output signal 0n. This carry signal delay time
t11 is a value obtained by adding the following times t12 and t13.

Time t12 = delay addition time of inverters 60, 66 time t13 = delay time of slave clocked inverter 70 + delay time of output buffer 71 Therefore, rather than the conventional slave clock pulse φ2
Since there is no delay time of the inverter 62 and a delay time of the 2-input NOR gate 64, the carry signal Ca is output earlier. Comparing the carry signal delay time t11 of the present embodiment with the conventional delay time t1, for example, the conventional t1 is 240 to 260 ns, whereas the t11 of the present embodiment is 120 ns or less. t1 ＝
It can operate with a clock pulse φ of about 4 MHz in 240 to 260 ns, but can operate with a clock pulse φ of about 6 MHz at t11 = 120 ns or less.

 The advantages of this embodiment can be summarized as follows.

Slave clocked inverter 70 for carry signal generation
Is provided and the earliest clock pulse φ3 from the clock pulse φ is set as the data fetch timing of the slave clocked inverter 70, so that the output delay time of the carry signal Ca can be greatly shortened. Therefore, when the shift registers are cascade-connected in plural stages, the output delay of the carry signal Ca is not limited by the maximum operating speed of the shift registers of each stage, and the maximum operating speed of the shift register of one stage can be obtained.

In the above embodiment, the shift register body 40,
Clock pulse generation circuit 41 and carry signal generation circuit 42
Each of the internal circuit configurations can be modified in various ways other than those shown.

(Effects of the Invention) As described in detail above, according to the present invention, a carry signal generating circuit for outputting a carry signal is provided, and this carry signal generating circuit is the second one which is the earliest when viewed from the first clock signal. Since the carry signal is output by using the clock signal to output the carry signal, the output delay time of the carry signal can be significantly reduced. Therefore, when such shift registers are connected in cascade in a plurality of stages, they can be operated at high speed with high accuracy.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a shift register showing an embodiment of the present invention, FIG. 2 is a cascade connection diagram of a conventional shift register, FIG. 3 is a circuit diagram of a conventional shift register, and FIG. 4 is FIG. 5 is a timing chart of FIG. 1, and FIG. 5 is a timing chart of FIG. 40 ... Shift register body, 41 ... Clock pulse generation circuit, 42 ... Carry signal generation circuit, 51-1 to 51-n ...
Master clocked inverter, 52-1 to 52-n, 70 ... Slave clocked inverter, 60 ... Inverter (first stage gate circuit), Ca ... Carry signal, D, D1 to Dn ... Serial data, 01 to 0n ...... Output signal, φ …… Clock pulse, φ1 …… Master clock pulse, φ2, φ3 …… Slave clock pulse.

Claims (1)

(57) [Claims] 1. An input terminal to which serial data is input, a clock terminal to which a first clock signal is input, and a clock terminal connected to the clock terminal and based on the first clock signal, the first clock signal. To the first clock signal, a second clock signal delayed by a first period, a third clock signal delayed from the first clock signal by a second period longer than the first period, and a third clock signal A clock generating circuit for generating a fourth clock signal having a phase substantially opposite to that of the clock signal, and n pieces of the clock generating circuits connected in series from the input terminal and input in response to the fourth clock signal. N data holding circuits that temporarily hold the serial data and output the held serial data in response to the third clock signal, and are connected to the output sides of the n data holding circuits, respectively. Connected to the n-th data holding circuit from the input terminal of the n data holding circuits, and the serial data held by the n-th data holding circuit is the third data output circuit. Shift signal generating circuit for generating a carry signal based on the serial data in response to the second clock signal before being output in response to the second clock signal. .