JPH0795016A - Flip flop circuit and scanning circuit - Google Patents

Abstract

PURPOSE:To obtain the flip-flop circuit in which a problem of racing caused by a clock skew is not generated even in the case a shift register is formed by connecting it in a multistage. CONSTITUTION:This circuit is provided with a first flip-flop circuit 1 for fetching input data in accordance with a clock signal, and maintaining a state for outputting the fetched data for one period. Also, this circuit is provided with a delaying means 2 for fetching the output data of a first flip-flop circuit 1, and delaying the fetched data by a half period and outputting the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit, and more particularly to a flip-flop circuit suitable for use in a scan circuit provided for detecting the state of data in an integrated circuit, and such a flip-flop circuit. It relates to a scan circuit using.

[0002]

2. Description of the Related Art A flip-flop circuit holds two stable states according to an input signal and a control signal, inversion, reset (clear), and set (preset).
It is a circuit that enables operations such as performing. Flip-flop circuits are widely used as memory elements in counting circuits, shift registers, and the like.

Flip-flop circuit In a circuit such as a shift register connected in multiple stages, the output data of the preceding stage is latched instead of the output data of the preceding stage due to the propagation delay time between the input and the output of the flip-flop circuit. A problem called racing may occur in which an incorrect operation result is output. FIG. 11 is a diagram showing a configuration example of a conventional master-slave flip-flop circuit of this type. Note that, in the drawings, the same functional parts are denoted by the same reference numerals. Reference numeral 5 is a master (master) latch and 6 is a slave (slave) latch.
The master latch 5 is composed of inverters 51 and 52 and transmission gates 53 and 54, and the slave latch 6 is composed of inverters 61, 62 and 63 and transmission gates 64 and 65. Reference numeral 31 is a circuit for generating complementary clock signals CK and xCK used internally from a clock signal CLK supplied from the outside. The input data D is transmitted to the inverter 51 when the transmission gate 53 is in a conductive (on) state, and when the transmission gate 53 is off, a loop composed of the inverters 51 and 52 and the transmission gate 54 is configured to be in a state corresponding to the input data D. Is set. When the transmission gate 64 is turned on, this data is transmitted to the inverters 61 and 62 and, at the same time, is output to the outside as an output Q via the inverter 63. When the transmission gate 65 is turned on, a loop formed by the inverters 61 and 62 and the transmission gate 65 is formed, and this state is maintained even after the transmission gate 64 is turned off. Transmission gate 53
, 54 and transmission gates 64 and 65, complementary clock signals CK and xCK are input in opposite phases,
Do the opposite.

The operation of the master-slave flip-flop circuit shown in FIG. 11 will be briefly described. When the clock signal CLK is at the “L” level, the transmission gate 53 is turned on and the transmission gate 54 is turned off, so that the input data D is set in the first latch 5. On the other hand, the second latch 6 stores and holds the previous input data because the transmission gate 64 is off and the transmission gate 65 is on, and the previous data is output to the output Q.

When the clock signal CLK is at "H" level,
Since the transmission gate 53 is turned off and the transmission gate 54 is turned on, the first
The latch 5 stores the input data D. On the other hand, at the same time, the transmission gate 64 is turned on and the transmission gate 65 is turned off, so that the second latch 6 takes in the data of the first latch 5 input via the transmission gate 64 and outputs it as Q at the same time. As a result, the output Q becomes new data.

As described above, the circuit of FIG. 11 is a circuit that transfers the input data D with a delay of up to one cycle of the clock signal CLK, and is used in a shift register or a counter circuit by utilizing such a function. . FIG. 12A is a diagram showing an example of a synchronous shift register circuit that transfers data by connecting flip-flop circuits in multiple stages so that the output of the preceding stage becomes the input of the subsequent stage. A common clock signal CLK is input to each flip-flop circuit. FIG. 11 (2) is a diagram showing the operation of the synchronous shift register circuit of (1), and it can be seen that data is sequentially transmitted to the subsequent stage in synchronization with the clock signal CLK.

In the synchronous shift register circuit shown in (1) of FIG. 11, each flip-flop circuit must be supplied with the clock signal CLK having the same phase. If clock signals CLK having different phases are supplied, a problem called racing may occur in which not the output data of the flip-flop circuit of the previous stage but the output data of the flip-flop circuit of the previous stage is transferred. FIG. 13 is a diagram for explaining the occurrence of this racing.

As shown in (1) of FIG. 13, in a shift register in which five flip-flop circuits 16-1 to 16-5 are connected, the first four flip-flop circuits 16-1 to 16-4 are used. Is supplied with the clock signal CLK1, but the final flip-flop circuit 16-5 is supplied with the clock signal CLK2 obtained by delaying the clock signal CLK1 by the delay element 17. Delay element 1
Reference numeral 7 is, for example, a plurality of stages of gate circuits or simply long wiring. Now, between the clock signals CLK1 and CLK2, FIG.
It is assumed that there is a delay as shown in (2). Due to this delay, at the time when the clock signal CLK2 input to the fifth flip-flop circuit 16-5 changes to the "H" state, the output of the fourth flip-flop circuit 16-4 has already been switched, The fifth flip-flop circuit 16-5 receives the output immediately after this switching. As a result, the fifth flip-flop circuit 1
6-5 transfers the data of the third flip-flop circuit 16-3, which is one ahead of the data to be originally transferred. The occurrence of a time difference between clock signals in a synchronous circuit is called skew.

As large-scale integrated circuits (LSIs) for logic circuits are becoming larger and larger, the importance of test circuits is increasing accordingly. This is because as the size of the logic LSI becomes larger, it becomes difficult to create a test pattern for performing deep verification of the internal logic circuit only by the diagnosis using the input / output terminals. Therefore, as one of the test methods for large-scaled LSI, there is one called a scan circuit.

To explain the simple method, the logic circuits are classified into combinational circuits (circuits in which the output is uniquely determined when the input is determined) and sequential circuits (F / F, latches, etc.), and then all the sequential circuits are classified. This is to modify the test circuit that can be shifted as if it were a shift register so that data can be set or extracted from all the sequential circuits directly from the outside.

Typical examples of the test method using the scan circuit are Japanese Patent Publication No. 25-25287 and Japanese Patent Publication No. 52287.
This is a method disclosed in Japanese Patent No. 30337, in which a sequential circuit for a scan path is provided separately from a normal circuit in an LSI, and a two-phase shift clock signal is supplied to the sequential circuit to read out latched data. A feature of this method is that data acquisition and transfer are controlled by a two-phase shift clock signal whose pulse portions do not overlap each other, and the data of the preceding stage is acquired after a certain time has elapsed after the output data was switched. Therefore, even if the clock signal has a skew, the problem of racing does not occur.

However, in order to supply the two-phase shift clock signal, it is necessary to provide two signal lines, which causes a problem that the wiring efficiency is lowered and so-called overhead becomes large. The scan circuit is just a test circuit,
It is desired to reduce the overhead as much as possible. In order to solve this problem, a method called a single clock scan method in which a scan clock signal supplied to a scan circuit is also used as a clock signal line of a normal logic circuit is becoming widespread. FIG. 14 is a diagram showing a configuration example of an LSI in which a scan circuit is formed by using a flip-flop circuit of a normal logic circuit. As the flip-flop circuit, the flip-flop circuit shown in (2) of FIG. 16 described later is used.

In FIG. 14, 300 is an LSI,
A normal logic circuit 200 is provided inside the LSI 300, and a general signal input terminal 201 and a general signal output terminal 202 are provided for inputting / outputting data between the outside of the LSI 300 and the logic circuit 200. The clock signal CLK is supplied from the clock signal terminal 203. Further, a scan circuit 208 is provided for testing the logic circuit 200. The scan circuit 208 includes a plurality of flip-flop circuits 101-1 ...
N of these flip-flop circuits 1
01-1, ..., 101-N are supplied with the clock signal CLK and the data D to be latched from the logic circuit 200, and the output Q is input to the logic circuit 200. That is, these flip-flop circuits are usually used as a part of the logic circuit 200. Flip-flop circuit 101-1, ...
The scan data SI and the mode switching signal SL are externally supplied to 101-N. During normal operation, the mode switching signal SL is set to the “H” state, and each flip-flop circuit 1
01-1, ..., 101-N are used as ordinary flip-flop circuits to which the clock signal CLK and the data D are input. To latch the data to transfer during the test,
Similarly to the normal operation, the mode switching signal SL is set to the “H” state, and then the clock signal CK is input. In order to transfer the latched data, the mode switching signal SL is set to the “L” state and then the required number of clock signals CK are input. In this way, it becomes possible to detect the state of the logic circuit 200 and read the data to the outside.

In the circuit of FIG. 14, the above-mentioned 2
Since the phase shift clock signal is not used, the overhead can be reduced, but the racing problem due to the clock skew of the clock signal CLK still remains. Further, in the circuit of FIG. 14, the flip-flop circuit used for the scan circuit is used as a synchronous circuit whose state is changed by the clock signal CLK, but when the flip-flop circuit is used in a normal logic circuit, It is not always used as an element, but may be used in an asynchronous circuit in which the output of another flip-flop circuit or the output of the gate circuit is input to the clock signal terminal. FIG. 15 is a diagram showing a configuration example of an asynchronous circuit.
The clock signal is input to the clock signal terminal of one flip-flop circuit 17-1, while the output of the flip-flop circuit 17-1 is input to the clock signal terminal of the other flip-flop circuit 17-2.

The circuit shown in FIG. 16 shows an example of a circuit that can be considered when the scan circuit is constructed by using the flip-flop circuit used in the asynchronous circuit shown in FIG.
(1) shows a circuit configuration, and (2) shows a flip-flop circuit used therein. In order to use the flip-flop circuits used in the asynchronous circuit of the normal circuit in the scan circuit, it is first necessary to externally control the clock signals of all the flip-flop circuits. To this end, as shown in (1) of FIG. 16, the clock input signal of the flip-flop circuit 18-2 at the subsequent stage is selected between the signal coming from the flip-flop circuit 18-1 at the previous stage and the clock signal CLK coming from the outside. It becomes necessary to provide the selector circuit 19 so that it can be performed. The problem is that the selector circuit 19 delays the signal.
That is, when operating as a scan circuit, the output of the previous flip-flop circuit 18-1 is the clock signal C.
It changes according to LK, and the flip-flop circuit 18 in the subsequent stage
─2 is input to the flip-flop circuit 18 in the subsequent stage
The clock signal CLK is input to the selector circuit 19
Therefore, there is a high possibility that the output data of the preceding flip-flop circuit 18-1 immediately after the delay and the change will be fetched. In other words, the selector circuit 1
This means that the output data of the previous stage is taken in due to the clock skew at 9.

A flip-flop circuit as shown in (2) of FIG. 16 is used for the scan circuit as described above. As shown in the figure, this circuit adds two transmission gates that are in the opposite state to the mode switching signal SL to the input stage of the circuit of FIG. 11, and inputs the data between the data D and the transfer data SI. This circuit is selectable according to the mode switching signal SL.

[0017]

SUMMARY OF THE INVENTION In order to prevent the malfunction due to the above clock skew, Japanese Patent Publication No. 63-276.
No. 913 discloses a scanpath circuit in which an inverter for delaying a signal is provided between flip-flop circuits, and Japanese Patent Publication No. 2-75218 discloses a flip-flop circuit at a front stage according to a clock signal of a flip-flop circuit at a rear stage. A scan path circuit is disclosed which prevents malfunction by controlling the output of the circuit. However, since these scan circuits cannot be used for ordinary logic circuits, the overhead of the scan path circuit can be reduced by using the flip-flop circuit which constitutes the asynchronous circuit by the above ordinary logic circuits also as the scan circuit. There is a problem that it cannot be used for.

As described above, when a flip-flop circuit is used to form a shift register or the like, a racing problem occurs due to clock skew. Although various measures as described above have been proposed to solve this problem, there is a demand for a flip-flop circuit that can more reliably solve the racing problem and can be used in various ways. A first object of the present invention is to realize a flip-flop circuit in which a racing problem caused by clock skew does not occur even when a shift register or the like is configured, and a second object is suitable for use in a scan circuit. The third object is to realize a scan circuit using a flip-flop circuit that forms an asynchronous circuit, and a third purpose is to realize a scan circuit with a small overhead using such a flip-flop circuit. Is.

[0019]

FIG. 1 is a principle configuration diagram of a flip-flop circuit according to the present invention. (1) shows a basic configuration and (2) shows a basic operation. As shown in the figure, a flip-flop circuit according to the present invention includes a first flip-flop circuit 1 for maintaining input data in accordance with a state of a clock signal, and a state of outputting the captured data for one cycle of the clock signal; The output data of the flip-flop circuit 1 is taken in, and the first flip-flop circuit 1 delays and outputs the taken-in data for a period from the change edge of the clock signal at which the data output starts to the change edge of the opposite phase of this change edge. And a delay means 2 for

[0020]

The time chart of (2) in FIG. 1 shows the basic operation of the flip-flop circuit of the present invention. Here, for convenience of explanation, the clock signal CLK is a signal having a duty ratio of 50%, and the first flip-flop circuit is shown. 1 is the clock signal C
The input data is taken in in synchronization with the rising edge of LK, and at the same time, the intermediate output Q0 is output, and the delay means 2 delays this intermediate output Q0 by a half cycle of the clock signal CLK to output
It shall be output as 1.

Consider a case where such a flip-flop circuit is connected in multiple stages to form a shift register.
Since each flip-flop circuit takes in the input data D at the rising edge of the clock signal CLK and outputs it with a delay of a half cycle, the output data is output from the falling edge of the clock signal CLK to the next falling edge. . The flip-flop circuit of the next stage takes in the output data of the preceding stage in synchronization with the rising edge of the clock signal CLK, but the output data is the clock signal CLK.
Since it is stable for about a half cycle before and after the rising edge of, the output data of the previous stage can be surely taken in even if there is a clock skew.

[0022]

FIG. 2 is a diagram showing the circuit configuration of a flip-flop circuit according to the first embodiment of the present invention. In FIG. 2, reference numeral 11 is a master-slave flip-flop circuit, which corresponds to the first flip-flop circuit 1 in FIG. Two
Reference numeral 1 is a delay circuit that delays the output of the master-slave flip-flop circuit 11, and corresponds to the delay unit 2 in FIG. Reference numeral 31 is a circuit for generating complementary signals CK and xCK of the clock signal used internally from the clock signal CLK. The first flip-flop circuit 11 and the clock generation circuit 31 have the same configurations as those shown in FIG. 11, and therefore their explanations are omitted here. The delay circuit 21 includes a loop in which two inverters are connected so that one output is input to the other,
It is a latch circuit composed of two transmission gates. The operation of the delay circuit 21 will be described with reference to the time chart of (2) in FIG. Clock signal CL
When K changes to the “H” state, the transmission gate 64 of the slave latch circuit 6 of the master-slave flip-flop circuit 11 becomes conductive, the output Q changes, and the delay circuit 21 passes through the two inverters 61 and 62.
Output to. At this time, since the transmission gate 73 of the delay circuit 21 is not conducting, the content stored in the latch circuit formed by the two inverters 71 and 72 does not change and the previous state is maintained. When the clock signal CLK changes to the “L” state, the transmission gate 73 becomes conductive, the data stored in the slave latch circuit 6 is applied to the delay circuit 21, and the delay circuit 2
The data stored in 1 changes, and the output Q1 also changes. When the clock signal CLK changes to the "H" state again, the output from the master-slave flip-flop circuit 11 changes, but the transmission gate 73 changes to the non-conductive state, so the output Q1 does not change. Output Q1
Changes when the clock signal CLK becomes the "L" state and the transmission gate 73 becomes conductive. Therefore, the output as shown in (2) of FIG. 1 is obtained.

In the first embodiment, the latch circuit is used as the delay circuit. However, if a master-slave flip-flop circuit having a transmission gate is used, a circuit which can prevent the racing due to the clock skew without using the latch circuit. Can be realized. This example is shown in the second embodiment. FIG. 3 is a diagram showing the configuration of the flip-flop circuit of the second embodiment, and a time chart showing its operation is shown in FIG.

The flip-flop circuit of FIG. 3 is a circuit in which the delay circuit 21 of FIG. 2 is replaced with an output circuit composed of one transmission gate 75. In other words, the delay circuit 21 shown in FIG.
It is a circuit in which only the transmission gate 73 is left, except for 1 and the transmission gate 74. However,
The output from the master-slave flip-flop circuit 11 to the output circuit 22 is output from the inverter 61.

Output Q1 of the flip-flop circuit of FIG.
Is the output Q of the master-slave flip-flop circuit 11.
The period in which data is output is only the conduction period of the transmission gate 75, and the high impedance state is set during the non-conduction period of the transmission gate 75. Therefore, the operation of the flip-flop circuit of FIG. 3 is as shown in FIG.

Consider a case where the flip-flop circuits of FIG. 3 are connected in multiple stages to form a shift register. The transmission gate 53 of the master latch circuit 5 becomes conductive when the clock signal CLK is "L", and the data state of the master latch circuit 5 is set. As shown in FIG. 4, the output of the flip-flop circuit at the previous stage is output only while the clock signal CLK is "L", and is in a high impedance state while the clock signal CLK is "H". Therefore, while the clock signal CLK is "L", the transmission gate 53 of the master latch circuit 5 becomes conductive and the data output from the previous stage is taken in.

Now, consider a case where a skew occurs in the clock signal to the subsequent flip-flop circuit. First, when the clock signal to the subsequent stage becomes faster than the previous stage, the clock signal to the subsequent stage becomes the “L” state, so that the transmission gate 53 of the master latch circuit 5 in the subsequent stage becomes conductive, and then to the previous stage. Of the clock signal becomes "L", and the output of the preceding stage becomes a state of outputting data from the high impedance state. In this state, the data state of the master latch circuit in the subsequent stage is set. Then, the clock signal to the subsequent stage becomes the “H” state,
The transmission gate 53 of the master latch circuit in the subsequent stage changes to the non-conductive state while the data is being output from the previous stage. After the transmission gate 53 becomes non-conducting, the data state of the master latch circuit 5 does not change, so that the flip-flop circuit in the subsequent stage normally takes in the data output from the flip-flop circuit in the previous stage,
Perform the transfer operation.

Next, when the clock signal to the succeeding stage becomes later than the preceding stage, the clock signal to the succeeding stage is in a state in which data is being output from the preceding stage due to the clock signal to the preceding stage being in the "L" state. Becomes the "L" state, the transmission gate 53 of the master latch circuit 5 in the subsequent stage becomes conductive, and the data state of the master latch circuit 5 in the subsequent stage is set. Then, the clock signal to the preceding stage becomes the “H” state, so that the data output from the preceding stage is in the high impedance state while the transmission gate 53 of the master latch circuit 5 in the succeeding stage is conductive. When the output is in the high-impedance state, it does not affect the other parts to be connected. Therefore, even if the transmission gate 53 is conducting, the normal data state stored in the master latch circuit 5 in the subsequent stage is not affected and remains unchanged. The state is maintained, and the stored data is further transferred to the flip-flop circuit at the next stage.

As described above, if the shift register is constructed using the flip-flop circuit of FIG. 3, the problem of racing can be avoided even if there is a clock skew.
The flip-flop circuit of FIG. 3 has the advantage that the delay circuit has fewer constituent elements than the circuit of FIG. 2 and the circuit can be miniaturized. However, the flip-flops must be directly connected via the input / output transmission gate.

Next, an embodiment in which a scan circuit is formed by using the flip-flop circuit of the present invention will be described. However, only an example using a flip-flop circuit having a delay circuit as shown in FIG. 2 will be described. However, it is also possible to use a flip-flop circuit having only a transmission gate as a delay circuit as shown in FIG.

FIG. 5 is a diagram showing the overall configuration of the third embodiment. Since the scan path circuit of FIG. 5 has an overall configuration similar to that of the circuit of FIG. 14, an explanation of the overall configuration and a scan circuit will be given. Although description of the operation is omitted, the difference is that the flip-flop circuit used and the output SO delayed by a half cycle are supplied as the scan data SI of the subsequent stage. FIG. 6 is a diagram showing a circuit configuration of a flip-flop circuit used in the third embodiment. As is clear from comparison between FIG. 6 and FIG. 2, the circuit of FIG. 6 has a configuration similar to that of FIG. 2, but the transmission gate portion of the master-slave flip-flop circuit and the clock signal generation circuit 32 portion are different. That is, the transmission gate 5
5, 56, 66 and 67 are added, and in the clock signal generation circuit 32, the scan clock signal SCK and the clock signal CK used internally from the scan clock signal SCK and the clock signal CLK supplied from the outside of the flip-flop circuit are used. Inverted signals xSC and xCK are generated.

In the third embodiment, the scan clock signal SCK is fixed to the "H" state during the normal operation, and only the clock signal CLK is input from the outside. Therefore, a normal logic circuit is provided in each flip-flop circuit. Only the clock signal CLK is supplied via. At this time, since the scan clock signal SCK is in the “H” state, in the clock signal generation circuit 32, the NOR circuit 33 simply functions as an inverter that inverts the clock signal CK, and the complementary signals CK and xCK of the clock signal CLK are generated. .

The scan operation has a latch mode and a transfer mode. In the latch mode, the scan clock signal SCK is also fixed to the “H” state, only the clock signal CLK is input from the outside, and the clock signal CLK is input.
The data of the logic circuit is latched accordingly. In the transfer mode, the clock signal CLK is fixed to the "H" state,
Only the scan clock signal SCK is supplied from the outside. Complementary signal S according to scan clock signal SCK
Although C and xSC are generated, since one input clock signal CLK of the NOR circuit 33 is fixed at "H",
The clock signals CK and xCK are fixed to “H” and “L”, respectively. Although it is stipulated that the clock signal CLK and the scan clock signal SCK never go to the "L" state at the same time, if the clock signal CLK and the scan clock signal SC go to the "L" state at the same time, the clock signal CK and the scan clock signal SC
K is in the opposite state. This prevents data collision in the loop portion as described later.

FIGS. 7 and 8 are time charts showing the operation of the flip-flop circuit in the normal operation and the scan operation in the third embodiment, respectively, and the operation of the flip-flop circuit in FIG. 6 will be referred to with reference to this. explain. Figure 7
As shown in, during normal operation, that is, when it does not operate as a scan circuit but operates as part of a normal logic circuit, the scan clock signal SCK is fixed to the “H” state, and the clock signal is externally applied. Only CLK is input. At this time, the complementary signals SC and x of the scan clock signal
Since SC is fixed to "H" and "L", respectively, transmission gates 55, 67 and 73 are non-conductive, and transmission gates 56, 66 and 74 are conductive. It can be said that the circuit in this state is the same as the flip-flop circuit in FIG. Therefore, as shown in FIG. 7, the flip-flop circuit in this state outputs the input data set when the clock signal CLK is in the "L" state at the same time when the clock signal CLK rises to the "H" state, and It operates as a normal flip-flop circuit that maintains its output state until the rising edge of the clock signal CLK.

When operating as a scan circuit which latches the data of the logic circuit and sequentially transfers the latched data to the flip-flop circuit of the next stage, there are two modes of the latch mode and the transfer mode, and the operations are different. As shown in FIG. 8, consider a case where the transfer mode is switched to the latch mode to latch the data in the logic circuit, and the mode is returned to the transfer mode again to transfer the latched data. In the transfer mode, the clock signal CLK is fixed to the "H" state, and only the scan clock signal SCK is input from the outside. At this time, since the complementary signals CK and xCK of the clock signal are fixed to "H" and "L", respectively, the transmission gates 53 and 65 are rendered non-conductive, and the transmission gates 54 and 64 are rendered conductive. The circuit in this state is a state in which the scan path data SI is input instead of the data input signal D and the scan clock signal SCK is input instead of the clock signal CLK in the flip-flop circuit of FIG. It can be said that it corresponds to a shift register function circuit by a normal flip-flop that transfers the scan path data SI according to the scan clock signal SCK. Therefore, as shown in FIG. 8, the scan path data SI is sequentially transferred in synchronization with the fall of the scan clock signal SCK.

In order to latch the data of the logic circuit, when the scan clock signal SCK changes to the "H" state, the state is maintained as it is, a negative pulse is applied as the clock signal CLK, and the "L" state is set. Lower. At this time, the signal CK is “L”, xCK is “H”, SC is “H”,
Since xSC becomes "L", the input data D is set in the master flip-flop circuit as in the normal operation, and is output as the output data Q when the clock signal CLK rises to the "H" state again. This data is stored in the master-slave flip-flop circuit.

Returning to the transfer mode again, the clock signal CL
When K is fixed to the “H” state, the scan clock signal SCK is input from the outside, and when the scan clock signal SCK becomes “L”, the transmission gate 73 becomes conductive and the data is stored in the master slave flip-flop circuit. The data is output to the delay circuit 21, and the scan path output data SO is output to the next stage.

As described above, the data in the logic circuit is latched and transferred. The clock signal CLK and the scan clock signal SCK are controlled so as not to be "L" at the same time. However, if they become "L" at the same time, the input data D and the scan path input data SI collide with each other.
Scan clock signal SC in the clock signal generation circuit 31
Prioritizing K, the scan clock signal SCK is set to "L", and then one of the complementary signals CK generated from the clock signal is not set to "L".

Next, when the scan path circuit is formed using the flip-flop circuit used as the asynchronous circuit in the ordinary logic circuit described in the section of the prior art, the first application of the flip-flop circuit of the present invention Four examples will be described. FIG. 9 is a diagram showing a circuit configuration in the fourth embodiment, which is a circuit corresponding to the circuit of (1) of FIG. Similar to the circuit (1) of FIG. 16, a selector circuit 19 including an OR gate and an AND gate is used, and the difference is that the data input to the scan input data SI of the second-stage flip-flop circuit is different. Is that the scan output data SO is not the output Q of the flip-flop circuit but is delayed by a half cycle and is output. As described above, since the scan output data SO delayed by a half cycle is input as the scan input data SI, even if a skew occurs in the common clock signal CLK, there is no fear of racing.

FIG. 10 is a diagram showing the configuration of the flip-flop circuit used in the fourth embodiment. As is apparent from comparison with (2) of FIG. 16, the circuit of FIG. 10 is a circuit in which a delay circuit is added after the circuit of (2) of FIG.
The output SO is output after being delayed by a half cycle of the clock signal with respect to the normal data output Q. Therefore, the problem of racing does not occur as described above.

[0041]

As described above, the output of the flip-flop circuit is delayed by a half cycle as in the present invention, or the output is set to a high impedance state in the flip-flop circuit using the transmission gate.
It is possible to prevent racing when data is transferred by connecting flip-flop circuits in multiple stages. In particular, by using the flip-flop circuit of the present invention for a scan circuit that also transfers data while also functioning as a flip-flop circuit used in an LSI logic circuit, reliable data transfer without racing becomes possible.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a flip-flop circuit of the present invention.

FIG. 2 is a diagram showing a circuit configuration in a first embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration in a second embodiment of the present invention.

FIG. 4 is a diagram showing a time chart showing the circuit operation in the second embodiment.

FIG. 5 is a diagram showing an overall configuration of an LSI according to a third embodiment of the present invention.

FIG. 6 is a diagram showing the configuration of an SI flip-flop circuit used in the third embodiment.

FIG. 7 is a diagram showing a time chart during normal operation in the third embodiment.

FIG. 8 is a diagram showing a time chart when a normal operation and a scan operation are mixed in the third embodiment.

FIG. 9 is a diagram showing a circuit configuration in a fourth exemplary embodiment of the present invention.

FIG. 10 is a diagram showing the configuration of an SI flip-flop circuit used in the fourth embodiment.

FIG. 11 is a diagram showing a configuration of a conventional flip-flop circuit using a transmission gate.

FIG. 12 is a diagram showing a synchronous shift register that transfers data by flip-flop circuits connected in multiple stages.

FIG. 13 is an explanatory diagram of occurrence of malfunction due to skew in flip-flop circuits connected in multiple stages.

FIG. 14 is a diagram showing an overall configuration of a conventional LSI having a scan circuit.

FIG. 15 is a diagram showing an asynchronous circuit using a flip-flop circuit.

FIG. 16 is a diagram showing a conventional example in which a flip-flop circuit used in an asynchronous circuit of a normal circuit is used as a scan circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st flip-flop circuit 2 ... delay means 5 ... main (master) latch circuit 6 ... subordinate (slave) latch circuit

Claims (13)

[Claims] 1. A first flip-flop circuit (1) which receives input data according to a state of a clock signal and maintains a state of outputting the data fetched during one period of the clock signal, and the first flip-flop circuit. The output data of (1) is fetched, and the fetched data is taken only during the period from the change edge of the clock signal at which the first flip-flop circuit (1) starts outputting data to the change edge of the opposite phase of the change edge. A flip-flop circuit comprising a delay means (2) for delaying and outputting. 2. The delay means (2) is a latch circuit that switches at a timing of a reverse phase of switching of the first flip-flop circuit (1) with respect to the clock signal. The flip-flop circuit according to. 3. The first flip-flop circuit (1)
Has a main latch circuit (5) having a transmission gate and a slave latch circuit (6) having a transmission gate, and takes in input data in one state of the clock signal, and the clock signal receives the other signal. A flip-flop circuit for outputting the fetched data for one cycle of the clock signal after switching to the above state, and the delay means (2) is a latch circuit (21) having a transmission gate. The flip-flop circuit according to claim 1. 4. Two transmission gates (53, 54) capable of switching between a passing state and a non-passing state in opposite phases.
The flip-flop circuit according to claim 3, wherein the flip-flop circuit is provided in a stage preceding the input section of the main latch circuit (5). 5. Each transmission gate of the main latch circuit (5) is a set of two transmission gates, each of which operates in response to two types of clock signals, one of which is fixed to a predetermined state when the other is output. The set of transmission gates, except the set of transmission gates of the input section, is equivalent to the fact that when one of the two types of clock signals is output, there is only one transmission gate that operates with the clock signal. The two transmission gates of the set of transmission gates of the input section are respectively connected to the input sections, and are configured to be in a non-conducting state when the input clock signal is in a predetermined state which is not an output state. The flip flow according to claim 3, characterized in that Circuit. 6. A main latch circuit (5) having a transmission gate and a slave latch circuit (6) having a transmission gate, wherein input data is fetched in a first state of the clock signal, and the clock is supplied. A first flip-flop circuit (11) for outputting the data fetched after switching to the second state of the signal for one cycle of the clock signal; and an output of the first flip-flop circuit (11), A flip-flop circuit comprising: a transmission gate (22) for passing an output of the first flip-flop circuit (11) while the clock signal is in the first state. 7. The transmission gate according to claim 6, further comprising two transmission gates provided in a front stage of the input section of the main latch circuit (5) and capable of switching between a passing state and a non-passing state in opposite phases. Flip-flop circuit. 8. The transmission gate of the main latch circuit (5) is a set of two transmission gates, each of which operates in response to two types of clock signals, one of which is fixed in a predetermined state when the other is output. The set of transmission gates, except the set of transmission gates of the input section, is equivalent to the fact that when one of the two types of clock signals is output, there is only one transmission gate that operates with the clock signal. The two transmission gates of the set of transmission gates of the input section are respectively connected to the input sections, and are configured to be in a non-conducting state when the input clock signal is in a predetermined state which is not an output state. 7. The flip-flop according to claim 6, wherein Circuit. 9. The method according to claim 1, 2, 3, or 6.
A shift register circuit, wherein the flip-flop circuits described in the above item are sequentially connected so that the output of the preceding stage is connected to the input of the following stage. 10. A scan circuit for latching data of the internal state of an integrated circuit, transferring the latched data of the internal state according to a scan clock signal, and sequentially reading the data, wherein the scan circuit according to claim 4 or 7. A scan circuit comprising a sequential circuit in which the flip-flop circuits described above are sequentially connected so that the output of the preceding stage is connected to the input of the following stage. 11. A part of a flip-flop circuit that constitutes the sequential circuit is commonly used for an ordinary circuit other than the scan circuit of the integrated circuit, and the main latch circuit (5).
The data of the normal circuit is input to one of the two transmission gates provided in the front stage of the input section of the input circuit, and the data transferred to the scan circuit is input to the other of the two transmission gates. The scan circuit according to claim 10, wherein the scan circuit is supplied through a common path. 12. A scan circuit for latching internal state data of an integrated circuit, transferring the latched internal state data in accordance with a scan clock signal, and sequentially reading the data, wherein the scan circuit is any one of claims 5 and 8. A scan circuit comprising a sequential circuit in which the flip-flop circuits described above are sequentially connected so that the output of the preceding stage is connected to the input of the following stage. 13. A part of a flip-flop circuit that constitutes the sequential circuit is commonly used for a normal circuit other than the scan circuit of the integrated circuit, and the main latch circuit (5).
The data of the normal circuit is input to one of the two transistor transmission gates provided in the preceding stage of the input section of the input circuit, and the data transferred to the scan circuit is input to the other gate, and the clocks of the scan circuit and the normal circuit are input. 13. The scan circuit according to claim 12, wherein the signal is supplied by another path.