JP3631390B2 - Synchronous circuit system and synchronous circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a synchronization circuit system and a synchronization circuit in a semiconductor integrated circuit, and more particularly to a synchronization circuit system and a synchronization circuit having a plurality of synchronization circuits for generating a clock having a plurality of phases inside the integrated circuit.
[0002]
[Prior art]
In a semiconductor integrated circuit, it is necessary to synchronize a clock inside the chip with a clock outside the chip. When a clock external to the chip is received by the input buffer and distributed inside the chip, the internal clock and the external clock may not be synchronized due to a signal delay caused by the buffer or wiring. In order to avoid this, a synchronization circuit that generates an internal clock in synchronization with an external clock is provided in the semiconductor integrated circuit.
[0003]
Among these synchronization circuits, T.W. Saeki et al. SMD (Synchronous Miller 69) used in "ISS 2.5 Digest of technical papers" published by "A 2.5ns Clock Access 250MHz 256Mb SDRAM with a Synchronous Mirror Delay" ISSCCC Digest of technical papers. A SAD (Synchronous Adjustable Delay, synchronous adjustment delay circuit) system including Traced Backward Delay is often used because of its high synchronization speed and low power consumption.
[0004]
Here, the principle of the SAD synchronous circuit disclosed in Japanese Patent Laid-Open No. 10-69326 will be described.
[0005]
FIG. 19 is a block diagram of a SAD type synchronization circuit.
[0006]
This synchronization circuit includes an input buffer 41, a delay monitor circuit 42, a forward pulse delay line 44 composed of a plurality of unit delay elements 43 connected in cascade, and a plurality of unit delay elements 45 connected in cascade. The number of state holding circuits (not shown) equal to the number of unit delay elements provided in the backward pulse delay line 46, the forward pulse delay line 44, and the backward pulse delay line 46, respectively, The control circuit 47 controls the pulse delay operation in the backward pulse delay line 46 according to the pulse delay state in the line 44, and the output buffer 48 to which the output from the backward pulse delay line 46 is input.
[0007]
In FIG. 19, a circuit including the forward pulse delay line 44, the backward pulse delay line 46, and the control circuit 47 is referred to as an SAD circuit.
[0008]
FIG. 20 is a timing chart showing an example of the operation of the synchronization circuit shown in FIG. Consider a case where an external clock CK having a period τ is input to the input buffer 41 as shown in FIG. The external clock CK is shaped and amplified by the input buffer 41 and output as a pulse CLK. Assuming that the delay time in the input buffer 41 is D1, the pulse CLK is delayed by D1 with respect to the external clock CK as shown in FIG. The pulse CLK output from the input buffer 41 is input to the delay monitor circuit 42 and the control circuit 47 of the SAD circuit SAD.
[0009]
The delay monitor circuit 42 has a delay time A (= D1 + D2) equal to the sum of the delay time D1 in the input buffer 41 and the delay time D2 in the output buffer 48. Therefore, as shown in FIG. 20, the pulse output from the delay monitor circuit 42 is input as the signal Din to the forward pulse delay line 44 with a delay of A from the pulse CLK output from the input buffer 41.
[0010]
As described above, the forward pulse delay line 44 is composed of a plurality of unit delay elements 43 connected in cascade. Then, during the period until the pulse CLK of the next cycle is input to the control circuit 47, the signal Din is sequentially delayed by the plurality of unit delay elements 43 connected in cascade. The backward pulse delay line 46 sequentially delays the next cycle pulse CLK after the next cycle pulse CLK is input to the control circuit 47, but the delay operation is controlled by the control circuit 47. Here, the control circuit 47 operates the backward pulse delay line 46 based on the forward pulse propagation state in the forward pulse delay line 44 so that the backward pulse propagation time becomes equal to the forward pulse propagation time. Control. Therefore, the pulse CLK of the next cycle is delayed by the time of (τ−A) by the backward pulse delay line 46. The output Dout from the backward pulse delay line 46 is delayed by the time D2 by the output buffer 48 and output as the internal clock CK '.
[0011]
Here, assuming that the delay time from the input of the external clock CK to the output of the internal clock CK ′ is Δtotal, Δtotal is expressed as follows.
[0012]
Δtotal = D1 + A + 2 (τ−A) + D2 (1)
Here, since D1 + D2 = A, Δtotal is 2τ, and the internal clock CK ′ is synchronized with the external clock CK from the third clock of the external clock CK.
[0013]
19, the number of unit delay elements 45 in the backward pulse delay line 46 is reduced to half the number of unit delay elements 43 in the forward pulse delay line 44, and the delay in the backward pulse delay line 46 is reduced. When the time is set to be half the delay time in the forward pulse delay line 44 and the delay time in the delay monitor circuit 42 is set to a delay time (2A) twice that in FIG. 19, the internal clock CK ' Is shifted by 180 ° with respect to the external clock CK.
[0014]
By the way, in a semiconductor integrated circuit that operates at high speed, in addition to the internal clock synchronized with the external clock, an internal clock whose phase is shifted by 90 ° or 180 ° with respect to the external clock, an internal clock that is doubled, etc. are generated. Is done. These clocks are formed by combining a plurality of synchronization circuits.
[0015]
As an example, FIG. 21 shows a configuration of a clock generation circuit that generates an internal clock Tu synchronized with an external clock and an internal clock Td whose phase is shifted by 180 ° with respect to the external clock. In this clock generation circuit, the synchronization circuit 71 generates the internal clock Tu from the external clock, and the synchronization circuit 72 generates the internal clock Td from the internal clock Tu.
[0016]
Further, when each of the synchronization circuits 71 and 72 is configured using an SAD circuit, it is as shown in FIGS.
[0017]
FIG. 22 shows the configuration of the synchronizing circuit 71 that generates the internal clock Tu. Similar to the synchronizing circuit shown in FIG. 19, the input buffer 41, the delay monitor circuit 42, the forward pulse delay line 44, and the backward pulse delay circuit. The SAD circuit SAD1 including the delay line 46 and an output buffer 48 are included.
[0018]
Here, the backward pulse delay line 46 and the forward pulse delay line 44 are delay lines having the same delay time.
[0019]
The delay monitor circuit 42 includes a buffer 81 having a circuit configuration and circuit pattern equivalent to the input buffer 41 so as to have a signal delay time equal to the sum of the signal delay times in the input buffer 41 and the output buffer 48, and an output buffer. A buffer 82 having a circuit configuration and circuit pattern equivalent to 48 is connected in series.
[0020]
FIG. 23 shows the configuration of the synchronizing circuit 72 for generating the internal clock Td. In this case, the SAD circuit SAD2 including the delay monitor circuit 42, the forward pulse delay line 44 and the backward pulse delay line 46, And an output buffer 48.
[0021]
In this case, it is shown that the backward pulse delay line 46 is a delay line having a delay time that is half the delay time of the forward pulse delay line 44.
[0022]
Furthermore, the delay monitor circuit 42 has two buffers 82 each having a circuit configuration and a circuit pattern equivalent to the output buffer 48 so as to have a signal delay time equal to the sum of the signal delay times in the two output buffers 48. Are connected in series.
[0023]
In the SAD type synchronization circuit, the internal clock is synchronized after the third clock after the supply of the external clock is started as described above. However, before synchronization can be achieved, an unsynchronized pulse is output from the synchronization circuit.
[0024]
FIG. 24 is a timing chart showing an example of the operation of the clock generation circuit shown in FIG. 21 when the SAD type synchronization circuit shown in FIGS. 22 and 23 is used as the synchronization circuit.
[0025]
As shown in FIG. 24, before the clock (C2) synchronized with the external clock is output from one synchronization circuit 71, the synchronization is achieved with respect to the external clock as indicated by C1. No clock Tu is output. Since the other synchronization circuit 72 starts the synchronization operation from the internal clock Tu of C1, the internal clock Td is output from the synchronization circuit 72 at a position indicated by C1 ′. However, the interval between C1 and C2 is not the original period τ but τ ′, and the synchronization circuit 72 starts the synchronization operation as if τ ′ is a period.
[0026]
As a result, as shown in FIG. 24, a state occurs where the clock C1 ′ generated from the clock C1 and the clock C2 ′ generated from the synchronized clock C2 are very clogged. .
[0027]
FIG. 24 shows a case where the duty is 50% as an external clock, that is, the period of “H” is the same as the period of “L”. However, when the duty is increased and the period of “H” is increased, C1 'and C2' overlap, and the timing at which the synchronization can actually be taken is delayed from the clock C3 'next to the clock C2'.
[0028]
The synchronization circuit 72 outputs an unsynchronized clock C1 ′ and an unsynchronized clock other than C1 ′ before the synchronized clock C3 ′. When the internal clock Td is input to another synchronization circuit, the synchronization operation is started from a clock that is not synchronized therewith, so that the synchronization is delayed.
[0029]
For the above reasons, in a synchronous circuit system having a plurality of synchronous circuits, there is a problem that even if an SAD type synchronous circuit having a high synchronization speed is used, clock synchronization is delayed as a whole system.
[0030]
For this reason, it is necessary to operate the synchronization circuit from a time earlier than the time when the synchronization clock is required, or to continue the operation of the synchronization circuit even when the synchronization clock is unnecessary. However, since the power is consumed when the synchronous circuit is operated, such a problem increases the standby power of the entire chip.
[0031]
[Problems to be solved by the invention]
The present invention has been made in consideration of the above-described circumstances. The purpose of the present invention is to provide a control circuit that does not output a clock until synchronization is established between two synchronization circuits. It is an object of the present invention to provide a synchronous circuit system that makes it possible to achieve high speed synchronization, thereby preventing an increase in standby power by stopping operation during an unnecessary period.
[0032]
Another object of the present invention is to make it possible to synchronize the entire system at high speed by adopting a configuration in which the clock is not output until synchronization is obtained, thereby waiting for the operation to be stopped during an unnecessary period. An object of the present invention is to provide a synchronization circuit that can prevent an increase in power.
[0033]
[Means for Solving the Problems]
In the synchronous circuit system of the present invention, the first clock is input. A first delay monitor circuit, a first forward pulse delay line, and a first backward pulse delay line, to which the first clock and an output clock from the first delay monitor circuit are input. The output clock from the first delay monitor circuit after the input of the first clock of the first cycle is delayed by a first forward pulse delay line for a predetermined time, and the next cycle of the first cycle The output from the first delay monitor circuit in which the first clock of the next second cycle is delayed by the first forward pulse delay line after the arrival of the first clock of the second cycle which is a cycle. Delayed by the first backward pulse delay line for a time corresponding to the delay time of the clock or n / m (where n and m are positive integers) respectively. Output second clock A first synchronous adjustment delay circuit. Of the first synchronization circuit and the second clock output from the first synchronization circuit, at least one pulse output first is cut off, and then the pulse output from the first synchronization circuit. A control circuit that sequentially outputs a group as a second clock and a second clock output from the control circuit are input. A second delay monitor circuit; a second forward pulse delay line; and a second backward pulse delay line; the second clock and an output clock from the second delay monitor circuit are input; The output clock from the second delay monitor circuit after the second clock of the first cycle is input is delayed for a predetermined time by the second forward pulse delay line, and the next cycle of the first cycle. The output clock from the second delay monitor circuit in which the second clock of the next second cycle is delayed by the second forward pulse delay line after the second clock of the second cycle is reached The second synchronization that outputs the third clock delayed by the second backward pulse delay line by a time corresponding to the delay time of the first time or n / m (where n and m are positive integers), respectively. Type And a delay circuit And a second synchronization circuit.
[0034]
The synchronous circuit system according to the present invention includes a first delay monitor circuit to which a first clock is input, a first forward pulse delay line, and a first backward pulse delay line. The output clock from the first delay monitor circuit is inputted, and the output clock from the first delay monitor circuit after the first clock in the first cycle is inputted is a first forward pulse delay. The first forward pulse delay of the first clock of the next second cycle is delayed after the arrival of the first clock of the second cycle, which is the next cycle of the first cycle. The first backward pulse for a time corresponding to a delay time of the output clock from the first delay monitor circuit delayed by a line or a time corresponding to n / m (where n and m are positive integers), respectively. A first synchronous adjustment delay circuit for outputting after delaying by a delay line, a first synchronization circuit for outputting a second clock corresponding to the first clock, and an input node for the first clock And the first synchronous adjustment delay circuit in the first synchronization circuit, at least the first clock input first among the first clocks is cut off, and then the above-mentioned A control circuit for sequentially outputting a first clock applied to the input node; and a second synchronization circuit for receiving a second clock output from the first synchronization circuit.
[0035]
The synchronization circuit of the present invention includes an input buffer to which a clock is input, a delay monitor circuit to which an output of the input buffer is input and having a predetermined signal delay amount, and a plurality of first unit delays connected in cascade. The delay monitor circuit is provided with a first delay line that sequentially delays the output of the delay monitor circuit by a plurality of first unit delay elements connected in cascade, and the output of the delay monitor circuit. In the period of one cycle from the output of the first cycle clock to the output of the second cycle clock, which is the next cycle of the first cycle, in the first pulse delay line. A detection circuit for detecting a first unit delay element through which an output of the delay monitor circuit has passed, and a plurality of second unit delay elements connected in cascade. The second unit delay element of the stage according to the detection result of the output circuit selects the clock of the second cycle output from the delay monitor circuit, and the selected clock is a plurality of clocks positioned in the subsequent stage. A second delay line that sequentially delays via a second unit delay element; and an output buffer to which an output of the second delay line is input, wherein the signal delay amount in the delay monitor circuit is the input A signal delay amount corresponding to the sum of the signal delay amounts in the buffer and the output buffer is set, and the output of the delay monitor circuit is input to at least the second unit delay element in the final stage of the second delay line. And the output from the second unit delay element in the preceding stage is delayed.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0037]
FIG. 1 is a block diagram of a synchronous circuit system according to a first embodiment of the present invention. The synchronous circuit system according to this embodiment includes a first synchronous circuit 11 and a second synchronous circuit 12, and a control circuit 13 provided between the synchronous circuits 11 and 12. Each of these circuits is integrated, for example, in the same chip.
[0038]
The first synchronization circuit 11 outputs the clock T1 in synchronization with the input clock. The first synchronization circuit 11 outputs at least one or more pulses that are not synchronized before synchronization is achieved. The control circuit 13 blocks pulses that are not synchronized with the input clock among pulses output from the first synchronization circuit 11, and sequentially sets a group of pulses after the synchronized pulses as a clock T2. Output. The second synchronization circuit 12 outputs a clock in synchronization with the clock T2. The output clock from the second synchronization circuit 12 is input to another synchronization circuit or the like.
[0039]
According to the synchronous circuit system of this embodiment, since only the clock synchronized with the external clock by the first synchronous circuit 11 is supplied to the second synchronous circuit 12, the synchronous clock is necessary. It is not necessary to operate from an earlier time than the above, and as a result, it is not necessary to operate the synchronous clock at an unnecessary time, and an increase in standby power of the entire chip can be avoided.
[0040]
In the embodiment of FIG. 1, a case has been described in which two synchronization circuits 11 and 12 are provided, and a control circuit 13 for interrupting an unsynchronized pulse is provided between them. When a synchronous circuit system is configured by connecting two or more synchronous circuits in series, a control circuit for cutting off a pulse that is not synchronized may be provided between the synchronous circuits.
[0041]
FIG. 2 is a block diagram of a synchronous circuit system according to a second embodiment of the present invention. In the embodiment of FIG. 1, the case where the output of the synchronization circuit 12 is directly input to another synchronization circuit or the like has been described. However, in the case where it is inconvenient if the output of the synchronization circuit 12 is directly input, FIG. As shown in FIG. 4, a control circuit 14 for interrupting pulses that are not synchronized may be provided on the output side of the synchronization circuit 12.
[0042]
FIGS. 3A and 3B are block diagrams of a synchronous circuit system according to the third embodiment of the present invention. In the embodiment shown in FIG. 1, a control circuit for interrupting pulses that are not synchronized is provided separately from the synchronization circuit, but this is included in the synchronization circuit 11 as shown in FIG. Therefore, the control circuit 13 for cutting off the pulse that is not synchronized is provided in the output section, or is included in the synchronization circuit 12 as shown in FIG. A configuration may be adopted in which a control circuit 13 for interrupting a non-existing pulse is provided at the input section.
[0043]
Contrary to the case of the synchronous circuit system according to the third embodiment, the previous control circuit is included in the synchronous circuit 12 to which the clock T2 is input, and the pulse that is not synchronized is cut off. It is good also as a structure which provided 13 in the input part.
[0044]
In the first to third embodiments, SAD synchronization circuits may be used as the first and second synchronization circuits 11 and 12, respectively. However, other types of synchronization circuits such as PLL circuits, A DLL circuit may be used.
[0045]
By the way, the control circuits 13 and 14 used in the first to third embodiments are required to have a function of interrupting pulses that are not synchronized and allowing only the synchronized pulses to pass. In addition, when the number of asynchronous pulses varies depending on the operating frequency and operating voltage, or when the number of asynchronous pulses varies depending on the circuit system, it is necessary to set the number of pulses to be cut off.
[0046]
FIG. 4 shows a specific configuration of the control circuits 13 and 14 used in the synchronous circuit in which a pulse that is not synchronized by one pulse is generated before the synchronized clock group. The control circuit in this case includes a counter 21 that counts an input clock and a switch circuit 22 that is inserted in a path between the input clock and the output clock.
[0047]
When the counter 21 counts one pulse input from the input clock path, the output of the counter 21 is controlled to close the switch circuit 22.
[0048]
Therefore, according to the control circuit having the configuration as shown in FIG. 4, pulses that are not synchronized with the external clock are not output, and the synchronized second and subsequent pulse groups are used as the clock. 12 or the like.
[0049]
FIG. 5 shows a specific configuration of the previous control circuits 13 and 14 suitable when the number of non-synchronized pulses output from the synchronization circuit varies. The control circuit in this case is different from that in FIG. 4 in that a preset type counter 23 in which the count value can be set is used instead of the counter 21 in FIG. 4, and the other points are the same as in FIG. It is.
[0050]
In this case, when the counter 23 counts a preset number of pulses input from the path of the input clock, the switch circuit 22 is controlled to be closed by the output of the counter 23.
[0051]
Accordingly, even in the case of the control circuit having the configuration as shown in FIG. 5, pulses that are not synchronized with the external clock are cut off without being output, and pulses after the preset number of pulses are synchronized. The group is input as a clock to the synchronization circuit 12 or the like.
[0052]
FIG. 6 shows another specific configuration of the control circuits 13 and 14 used in the synchronous circuit in which a pulse that is not synchronized by one pulse is generated before the synchronized clock group.
[0053]
This control circuit includes two shift registers 31 and 32, a two-input AND gate 33 and an inverter 34. A reset signal bRESET is input to the data input terminal of the one shift register 31. Further, the data input terminal of the other shift register 32 is connected to the data output terminal of the one shift register 31. The signal at the data output terminal of the other shift register 32 is input to the AND gate 33 together with the input clock T1 for this control circuit. Also, the input clock T1 is input to the one shift register 31 as a shift control signal, and the input clock T1 is input to the other shift register 32 via the inverter 34 as a shift control signal.
[0054]
Next, an example of the operation of the control circuit in FIG. 6 will be described with reference to a timing chart shown in FIG.
[0055]
First, after the reset signal bRESET becomes “H” level and the reset state is released, the input clock T1 is input at the timing shown in FIG. At this time, it is assumed that the first pulse of T1 is a pulse that is not synchronized with the external clock. Then, after the first pulse of T1 rises to the “H” level, the “H” level reset signal bRESET is read into one shift register 31, and the output R1 of this shift register 31 changes from the “L” level. Inverts to “H” level.
[0056]
Next, after the first pulse of T1 falls from the “H” level to the “L” level and the output of the inverter 34 is inverted from the “L” level to the “H” level, the “H” level of one shift register 31 is set. The “level output R1 is read into the other shift register 32, and the output R2 is inverted from the“ L ”level to the“ H ”level. Since the AND gate 33 outputs the input clock T1 while R2 is at the “H” level, the first pulse of the input clock T1 is cut off without being output from the AND gate 33 as shown in FIG. .
[0057]
Therefore, the clock T2 is a second and subsequent pulse group that is synchronized.
[0058]
By the way, as an example of the control circuit using the shift register shown in FIG. 6, only the first non-synchronized pulse is cut off. However, in order to cut off a plurality of continuous pulses, a shift circuit is used. What is necessary is just to add the number of registers.
[0059]
That is, FIG. 8 shows a specific configuration of a control circuit that blocks a plurality of continuous pulses. This control circuit is provided with two or more even-numbered shift registers 35-1 to 35 -n and connected in series, and a reset signal bRESET is input to the data input terminal of the first-stage shift register 35-1. The input clock T1 is input as a shift control signal to the shift registers 35-1, 35-3,... Of the stages, and the shift control signals 35-2,. The input clock T1 is input via each inverter 36, and the signal at the data output terminal of the final shift register 35-n is input to the AND gate 37 together with the input clock T1.
[0060]
According to the control circuit as shown in FIG. 8, the number of continuous input pulses corresponding to half the number of shift registers 35-1 to 35-n can be cut off.
[0061]
By the way, in each of the first to third embodiments, by providing a control circuit that cuts off a pulse that is not synchronized between the synchronization circuits or at the output part of the synchronization circuit or the input part of the synchronization circuit, Although an unsynchronized pulse is not input to the synchronizing circuit, an embodiment in which the synchronizing circuit itself has a function of not outputting an unsynchronized pulse will be described.
[0062]
In the SAD synchronous circuit shown in FIG. 19, the output from the delay monitor circuit 42 after the clock CLK is first input is delayed for a predetermined time by the forward pulse delay line 44, and then the clock CLK arrives. The next clock CLK is delayed and output by the backward pulse delay line 46 for a time corresponding to the delay time of the output clock from the delay monitor circuit 42 delayed by the forward pulse delay line 44. Yes.
[0063]
In order to realize such an operation, each of the plurality of unit delay elements 45 in the backward pulse delay line 46 performs a logical operation as shown in FIG. Each unit delay element 45 in the backward pulse delay line 46 passes a pulse from the subsequent stage or outputs “H” depending on the state of the control circuit 47 and the value of the CLK line to which the clock CLK is transmitted. Or set the output to the “L” level. That is, when the control circuit 47 is in the set state, each unit delay element 45 propagates the output pulse from the previous stage to the subsequent stage regardless of the value of the CLK line. On the other hand, when the control circuit 47 is in the reset state and the value of the CLK line is “H” level, the corresponding unit delay element 45 sets its output to “H” level and the value of the CLK line is “L”. If it is level, it is set to “L” level.
[0064]
In the conventional SAD circuit, in the backward pulse delay line 46 corresponding to the unit delay element 43 in which the pulse is not propagated, in the next stage of the unit delay element 43 in the forward pulse delay line 44 in which the pulse is propagated. The pulse CLK is delayed in the backward pulse delay line 46 by the operation of selecting the pulse CLK in the unit delay element 44 and outputting it to the subsequent unit delay element 44.
[0065]
FIG. 10 shows the operation of the synchronous circuit of FIG. 19 including the conventional SAD circuit after it has been previously reset, such as immediately after power-on or when returning from a power-down mode. It is a timing chart which shows an example of operation at the time of starting. Since the control circuit 47 is in the reset state, when the first clock CLK is input to the control circuit 47, the first clock CLK is selected by the last unit delay element 46 in the backward pulse delay line 46, and Dout (Pulse generated without passing through the delay line in FIG. 10).
[0066]
On the other hand, the first clock CLK is input to the forward pulse delay line 44 as Din after passing through the delay monitor circuit 42. Then, after the time of τ-A has elapsed from the rise of Din corresponding to the first clock CLK, the delay of the next clock CLK is started by the backward pulse delay line 46, and this next clock CLK is the time of τ-A. And is output as Dout (pulse generated through the delay line in FIG. 10).
[0067]
That is, two pulses having different timings corresponding to the first clock CLK are output as Dout, and in response to this, one pulse is output to the internal clock CK ′ before synchronizing with the external clock, This is input to another synchronization circuit as an unsynchronized pulse.
[0068]
FIG. 11 is a block diagram showing a configuration of a synchronizing circuit according to the fourth embodiment of the present invention when the synchronizing circuit itself has a function of not outputting an unsynchronized pulse.
[0069]
The synchronization circuit according to this embodiment includes an SAD circuit SAD11 including an input buffer 41, a delay monitor circuit 42, a forward pulse delay line 44, and a backward pulse delay line 46, and an output, similarly to the synchronization circuit shown in FIG. In addition to the buffer 18, a control circuit 50 is additionally inserted in the middle of the propagation path (CLK line) of the clock CLK between the output of the input buffer 41 and the SAD circuit SAD11.
[0070]
The control circuit 50 has a function of cutting off the first pulse of the clock CLK output from the input buffer 41 and outputting a pulse after the first pulse. For example, as shown in FIGS. A counter using a counter or a shift register shown in FIG. 6 can be used.
[0071]
The delay monitor circuit 42 includes a buffer 51 having a circuit configuration equivalent to the input buffer 41 so as to have a delay time equal to the sum of the delay time in the input buffer 41 and the delay time in the output buffer 48, and an output buffer. 48 and a buffer 52 having a circuit configuration equivalent to 48.
[0072]
As described above, in the synchronization circuit of FIG. 11, the control circuit 50 for cutting off the non-synchronized pulse is inserted in the propagation path of the clock CLK between the output of the input buffer 41 and the SAD circuit SAD11. Therefore, since the clock CLK indicated by C1 in the timing chart of FIG. 10 is cut off by the control circuit 50 and is not input to the SAD circuit SAD11, an unsynchronized pulse is output to the internal clock CK '. Disappear.
[0073]
By the way, in the synchronous circuit of the fourth embodiment in which the control circuit 50 is inserted in the CLK line of the SAD circuit, an error occurs in the output clock (CK ′) depending on the delay time of the clock CLK generated by the control circuit 50.
[0074]
When this error becomes a problem in the operation of the chip, an output generated by inserting the control circuit 50 into the CLK line by providing a circuit having a signal delay time corresponding to the control circuit 50 in the delay monitor circuit 42. The error can be canceled.
[0075]
FIG. 12 is a block diagram showing a configuration of a synchronizing circuit according to the fifth embodiment of the present invention in which an output error caused by providing the control circuit 50 is canceled.
[0076]
In the synchronous circuit according to this embodiment, two imitation circuits 53 and 54 each having a circuit configuration equivalent to the control circuit 50 and having a signal delay time equivalent to the control circuit 50 are included in the delay monitor circuit 42. The buffers 51 and 52 are connected in series.
[0077]
In addition, each of the synchronous circuits according to the sixth embodiment of the present invention shown in the block diagram of FIG. 13 has a circuit configuration equivalent to the control circuit 50 and a signal delay time equivalent to the control circuit 50. Instead of providing the imitation circuits 53 and 54 in the delay monitor circuit 42, one imitation circuit 55 having a signal delay time twice as long as the signal delay time of the control circuit 50 may be provided.
[0078]
Next, the operation of the synchronization circuit shown in FIGS. 12 and 13 will be described with reference to the timing chart of FIG. Note that the signal delay time in the two imitation circuits 53 and 54 in FIG. 12 or one imitation circuit 55 in FIG. 13 is 2c.
[0079]
When the first external clock is input, the clock CLK is output after the delay time D 1 by the input buffer 41. The clock CLK is delayed by the time A + 2c by the delay monitor circuit 42 and input to the SAD circuit SAD11 as Din. Then, Din inputted to the SAD circuit SAD11 is delayed by τ-Ac by the forward pulse delay line 43, and then the next clock CLK is delayed by τ-Ac by the backward pulse delay line 46, and as Dout Output from the SAD circuit SAD11. Further, this Dout is delayed by the signal delay time D2 in the output buffer 48, and the internal clock Tu is generated.
[0080]
As described above, according to the synchronization circuit according to the embodiment shown in FIGS. 12 and 13, by providing the mimic circuit 53 and 54 or 55 in the delay monitor circuit 42, the influence of the signal delay time in the control circuit 50 can be eliminated. The error of the internal clock Tu can be eliminated.
[0081]
In each of the embodiments shown in FIGS. 11 to 13, the case where the internal clock Tu synchronized with the external clock is generated has been described. This is because the phase is 90 ° or 180 ° with respect to the delay amount in the forward pulse delay line. For example, the configuration is changed so that the backward pulse delay line is set to n / m (where n and m are positive integers) of the delay amount in the forward pulse delay line, and the phase is 360 ° with respect to the external clock. An internal clock that is shifted by n / m may be generated.
[0082]
By the way, the two imitation circuits 53 and 54 or one imitation circuit 55 connected in series are circuits having a signal delay time equivalent to the signal delay time in the control circuit 50. When a device using a shift register as shown in FIG. 6 is used, a circuit in which only the AND gate 33 of the control circuit of FIG. 6 is taken out can be used as shown in FIG. That is, in the control circuit of FIG. 6, the signal delay time between the clocks T2 and T1 is determined only by the AND gate 33. When the AND gate 33 is used as an imitation circuit, the power supply potential Vdd corresponding to the “H” level is always input to the other input other than T1.
[0083]
In the embodiment shown in FIG. 12, the case where two imitation circuits 53 and 54 each having a signal delay time equivalent to that of the control circuit 50 are provided in the delay monitor circuit 42 has been described. If a signal delay time equivalent to a delay amount twice that of the control circuit 50 is obtained, three or more imitation circuits may be provided and these may be connected in series.
[0084]
In each of the fourth, fifth, and sixth embodiments, the case where the synchronization circuit is configured not to output an unsynchronized clock by inserting the control circuit 50 in the CLK line has been described. Next, a description will be given of a synchronizing circuit according to a seventh embodiment of the present invention in which the backward pulse delay line 46 is devised so that an unsynchronized clock is not output.
[0085]
FIG. 16 shows a specific configuration of a conventional example of the unit delay element of the backward pulse delay line that performs the logic operation as shown in FIG.
[0086]
This unit delay element operates when the output from the previous stage is input, the control signal Q is at the “L” level and the inverted signal bQ is at the “H” level, and the clocked inverter ( (Synchronous signal inversion circuit) 61 and the clock CLK are input, the clock signal is output when the control signal bQ is at the “L” level and the inverted signal Q is at the “H” level, and the input is inverted and output. An inverter (synchronous signal inverting circuit) 62 and an inverter 63 in which the outputs of both the clocked inverters 61 and 62 are both connected to the input.
[0087]
In the unit delay element having such a configuration, as shown in FIG. 9, when the value of the CLK line becomes “H” level even when the state of the control circuit 47 is reset, the output becomes “H” level. turn into. That is, when the control circuit 47 is in the reset state, the control signal bQ is at the “L” level and the signal Q is at the “H” level, and the clocked inverter 61 operates, so that the output corresponds to the value of the CLK line. Level.
[0088]
Therefore, when the clock CLK first becomes “H” level immediately after reset, an asynchronous pulse is output from the last unit delay element 45 in the backward pulse delay line 46.
[0089]
In order to avoid this, in the synchronizing circuit according to the present embodiment, a unit delay element 45 at the last stage of the backward pulse delay line 46 having the operation logic as shown in FIG. That is, according to the unit delay element having the logic operation as shown in FIG. 17, when the control circuit 47 is in the reset state, the output is “high” even if the value of the CLK line becomes “H” level. It does not become “H” level but remains “L” level.
[0090]
FIG. 18 shows a circuit configuration of the unit delay element 45 at the last stage of the backward pulse delay line 46 that performs the logic operation as shown in FIG.
[0091]
This unit delay element is different from the conventional one shown in FIG. 16 in that, instead of inputting the clock CLK as the input of the clocked inverter 62, the potential of Vss is always input and the "L" level signal is input. This is what I did.
[0092]
According to such a configuration, when the control signal bQ is at the “L” level and the signal Q is at the “H” level, even if the clocked inverter 62 operates, the output is inverted to the “L” level of the input. It becomes “H” level, and the output of the inverter 63 to which this signal is input becomes “L” level.
[0093]
That is, if the unit delay element 45 of the last stage of the backward pulse delay line 46 is used as shown in FIG. 18, the clock CLK is selected by the last unit delay element as described above. It will not be output. As the unit delay elements other than the last stage of the backward pulse delay line 46, the conventional one shown in FIG. 16 is used.
[0094]
Therefore, in the synchronous circuit having such a backward pulse delay line 46, a clock asynchronous with the external clock is not output.
[0095]
By the way, when the upper limit of the frequency of the external clock input to the synchronization circuit having the SAD circuit is such that the clock CLK is selected by the unit delay element at the final stage in the backward pulse delay line 46, the output internal clock is output. This period is longer by the unit delay element, and there is no problem. For example, when the operable frequency is 100 MHz (the cycle is 10 ns) and the signal delay time per unit delay element is 400 ps, for example, the unit delay element as shown in FIG. 17 is used for the backward pulse delay line. In the synchronous circuit of the embodiment, one cycle is 10 ns + 400 ps = 10.4 ns, and operation is possible up to 96 MHz. That is, the effect is very small, 10% or less.
[0096]
Further, since the actual operating frequency of the SAD circuit is sufficiently lower than the operable frequency, there is no problem.
[0097]
Further, even if the unit delay element 45 of the last stage of the backward pulse delay line 46 is used as shown in FIG. 18, the signal delay time when passing the pulse from the previous stage is the unit delay other than the last stage. Since there is no change with the element, the synchronous operation can be performed accurately.
[0098]
In the above description, the case where the unit delay element having only the last stage of the backward pulse delay line 46 is configured as shown in FIG. 18 has been described. However, this is not necessarily limited to the last stage. As long as the frequency does not cause a problem, a plurality of unit delay elements including the final stage may be used so as to have the configuration shown in FIG.
[0099]
【The invention's effect】
As described above, according to the present invention, it is possible to synchronize the entire system at a high speed, and thereby it is possible to stop the operation in an unnecessary period and to prevent an increase in standby power. A circuit system can be provided.
[0100]
In addition, according to the present invention, it is possible to provide a synchronization circuit that can synchronize the entire system at high speed, and can thereby stop the operation during an unnecessary period and prevent an increase in standby power. be able to.
[Brief description of the drawings]
FIG. 1 is a block diagram of a synchronous circuit system according to a first embodiment of the present invention.
FIG. 2 is a block diagram of a synchronous circuit system according to a second embodiment of the present invention.
FIG. 3 is a block diagram of a synchronous circuit system according to a third embodiment of the present invention.
4 is a circuit diagram showing a specific configuration of a control circuit used in each synchronous circuit system of FIGS. 1 to 3; FIG.
5 is a circuit diagram showing another specific configuration of a control circuit used in each synchronous circuit system of FIGS. 1 to 3; FIG.
6 is a circuit diagram showing still another specific configuration of a control circuit used in each synchronous circuit system of FIGS. 1 to 3; FIG.
7 is a timing chart showing an example of the operation of the control circuit in FIG. 6;
FIG. 8 is a circuit diagram showing another specific configuration of a control circuit used in each synchronous circuit system of FIGS. 1 to 3;
FIG. 9 is a diagram collectively showing logic operations of unit delay elements in a backward pulse delay line used in each synchronous circuit system of FIGS. 1 to 3;
FIG. 10 is a timing chart showing an example of the operation of a synchronous circuit including a conventional SAD circuit.
FIG. 11 is a block diagram showing a configuration of a synchronization circuit according to a fourth embodiment of the present invention.
FIG. 12 is a block diagram showing a configuration of a synchronization circuit according to a fifth embodiment of the present invention.
FIG. 13 is a block diagram showing a configuration of a synchronization circuit according to a sixth embodiment of the present invention.
14 is a timing chart showing the operation of the synchronization circuit shown in FIG.
FIG. 15 is a circuit diagram of a control circuit used in each of the fourth to sixth synchronization circuits.
16 is a circuit diagram showing a conventional specific configuration of a unit delay element in a backward pulse delay line that performs the logical operation shown in FIG. 9;
FIG. 17 collectively shows logic operations of unit delay elements in a backward pulse delay line used in a synchronization circuit according to a seventh embodiment of the present invention;
FIG. 18 is a circuit diagram showing a specific configuration of a unit delay element in a backward pulse delay line used in a synchronization circuit according to a seventh embodiment of the present invention;
FIG. 19 is a block diagram of a SAD type synchronization circuit;
20 is a timing chart showing an example of the operation of the synchronization circuit shown in FIG.
FIG. 21 is a block diagram showing a configuration of a clock generation circuit configured using the synchronization circuit of FIG. 19;
22 is a circuit diagram in a case where one synchronization circuit of the clock generation circuit of FIG. 21 is configured using an SAD circuit.
23 is a circuit diagram in the case where the other synchronization circuit of the clock generation circuit of FIG. 21 is configured using an SAD circuit.
24 is a timing chart showing an example of the operation of the clock generation circuit using the synchronization circuit shown in FIGS. 22 and 23. FIG.
[Explanation of symbols]
11: first synchronization circuit,
12 ... Second synchronization circuit,
13, 14 ... control circuit,
21, 23 ... counter,
22 ... Switch circuit,
31, 32, 35-1 to 35-n... Shift register,
33, 37 ... AND gate,
34, 36 ... inverter,
41 ... Input buffer,
42. Delay monitor circuit,
43, 45 ... Unit delay elements,
44. Delay line for forward pulse,
46 ... Reverse pulse delay line,
47, 50 ... control circuit,
48 ... Output buffer,
51, 52 ... buffer,
53, 54, 55 ... imitation circuit,
61, 62 ... clocked inverter,
63 ... an inverter,
SAD11: SAD circuit.

Claims (3)

A first delay monitor circuit first clock are entered, the first forward pulse delay line and a first backward pulse delay line, from the first clock and the first delay monitor circuit The output clock from the first delay monitor circuit after the first clock of the first cycle is input is delayed by a first forward pulse delay line for a predetermined time, The first clock delayed by the first forward pulse delay line after the arrival of the first clock of the second cycle, which is the next cycle of the first cycle, of the first clock of the next second cycle. The second delay pulse is delayed by the first backward pulse delay line for a time corresponding to the delay time of the output clock from the delay monitor circuit or n / m (where n and m are respectively positive integers) . Croc A first synchronization circuit having a first synchronous adjustable delay circuit for outputting,
Of the second clocks output from the first synchronization circuit, at least one pulse output first is cut off, and then the pulse group output from the first synchronization circuit is used as the second clock. A control circuit for sequentially outputting;
A second delay monitor circuit to which a second clock output from the control circuit is input ; a second forward pulse delay line; and a second backward pulse delay line; The output clock from the second delay monitor circuit is input, and the output clock from the second delay monitor circuit after the second clock of the first cycle is input is used as the second forward pulse delay line. And the second forward pulse delay line of the second clock of the next second cycle after the arrival of the second clock of the second cycle that is the next cycle of the first cycle. The second backward pulse delay is delayed by the time corresponding to the delay time of the output clock from the second delay monitor circuit or n / m (where n and m are respectively positive integers). Synchronization circuit system characterized by comprising a second synchronizing circuit having a second synchronous adjustable delay circuit for outputting a third clock delayed by a line. A first delay monitor circuit to which a first clock is input; a first forward pulse delay line; and a first backward pulse delay line; from the first clock and the first delay monitor circuit; The output clock from the first delay monitor circuit after the first clock of the first cycle is input is delayed by a first forward pulse delay line for a predetermined time, The first clock delayed by the first forward pulse delay line after the arrival of the first clock of the second cycle, which is the next cycle of the first cycle, of the first clock of the next second cycle. The first output is delayed by the first backward pulse delay line for a time corresponding to the delay time of the output clock from the delay monitor circuit or n / m (where n and m are respectively positive integers). 1 And a synchronous adjustment delay circuit, a first synchronization circuit for outputting the second clock in accordance with the first clock,
One first input that is inserted between the input node of the first clock and the first synchronous adjustment delay circuit in the first synchronous circuit and is input at least first among the first clocks. A control circuit that cuts off the clock and then sequentially outputs a first clock applied to the input node;
A synchronizing circuit system comprising: a second synchronizing circuit to which a second clock output from the first synchronizing circuit is input. An input buffer to which the clock is input;
A delay monitor circuit that receives the output of the input buffer and has a predetermined signal delay amount;
A first delay line comprising a plurality of first unit delay elements connected in cascade in a plurality of stages, wherein the output of the delay monitor circuit is sequentially delayed by the plurality of first unit delay elements connected in cascade;
From the time when the output of the delay monitor circuit is input and the first cycle clock is output from the delay monitor circuit to the time when the clock of the second cycle, which is the next cycle of the first cycle, is output. A detection circuit for detecting a first unit delay element through which the output of the delay monitor circuit has passed in the first pulse delay line during a period of one cycle;
A plurality of second unit delay elements connected in cascade are connected to each other, and the second cycle clock output from the delay monitor circuit is output by the second unit delay element of the stage according to the detection result of the detection circuit. A second delay line that sequentially delays the selected clock through a plurality of second unit delay elements located at a later stage than the selected clock;
An output buffer to which the output of the second delay line is input;
The signal delay amount in the delay monitor circuit is set to a signal delay amount corresponding to the sum of the signal delay amounts in the input buffer and the output buffer,
The output of the delay monitor circuit is not input to at least the second unit delay element in the final stage of the second delay line, and the output from the second unit delay element in the preceding stage is delayed. A synchronization circuit characterized by the above.

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