JPS6160456B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system clock synchronization circuit between multiple chips that uses a common source oscillation.

Conventionally, when synchronizing system clocks between multiple chips, a common source oscillation signal was used, this source oscillation signal was input to several stages of binary counters, and the output of this binary counter was input to a group of logic gates. The output was used as the system clock. System clock synchronization was accomplished by resetting a binary counter.
However, this case has the disadvantage that a reset signal for synchronizing the system clock must be externally supplied to the binary counter. Moreover, there is a special one for inputting the reset signal.
I had to allocate a book terminal.

An object of the present invention is to provide a multi-chip synchronization circuit that is effective for LSIs and eliminates the above-mentioned drawbacks.
The present invention provides a plurality of shift registers connected in series using an original oscillation signal commonly supplied to a plurality of chips as a shift clock, a feedback circuit for driving these serially connected shift registers as a counter, and other components. A terminal receives an input signal supplied from the chip, and receives an input signal from the terminal and a feedback signal from the feedback circuit, and when the input signal is input, the input signal is prioritized and shifted to the first stage. In addition to the register, the device is characterized in that it includes a gate circuit that adds the feedback signal to the first stage shift register when there is no input signal, and uses the output of any shift register as the system clock.

This invention will be explained below using the drawings.

FIG. 1 shows an embodiment of the invention. This circuit is a circuit that can synchronize the system clock without externally supplying a reset signal. The inverted signal obtained by inputting the original oscillation signal FOS to the inverter 12 is transferred to shift registers 1, 2, and 3.
is the write signal, and the original oscillation signal is the read signal. Shift register 1 output to shift register 2, NAND gate 6 and inverter 4
The output of this inverter 4 is assumed to be the first system clock. The output of shift register 2 is used as the input of shift register 3 and gate 6, the output of shift register 3 is used as the input of gate 6 and inverter 5, and the output of inverter 5 is used as the input of shift register 3 and gate 6. The second system clock. On the other hand, the output of gate 6 is transferred to inverter 7, and AND gate 11
Let it be one of the inputs. The output of the inverter 7 is input to an output buffer 8, and the output of the output buffer 8 is connected to an input/output terminal 10 and is input to an inverter 9. The output of the inverter 9 is used as the input of the inverter 10, the output of the inverter 10 is used as the other input of the AND gate 11, and the output of this gate 11 is used as the input to the first stage shift register 1.

FIG. 2 shows waveform diagrams of the original oscillation signal FOS, shift registers 1, 2, and 3, gates 6, 11, and output buffer 8. In the initial state, shift registers 1, 2, and 3 all output high level. Therefore, each output of gates 6, 11, and 8 becomes low level in section 21. In the next interval 22, a low level is input to the shift register 1, so its output becomes a low level. Further, the next stage shift register 2 becomes low level in the interval 23, and the shift register becomes low level in the interval 24, respectively.
Therefore, the signal obtained by inverting the output of shift register 1 using an inverter is used as the first system clock.
By inverting the output of shift register 3 with inverter 5 and using it as the second system clock, the first and second system clocks are alternately generated every other cycle of the original oscillation signal FOS. be able to.

FIG. 3 is a block diagram when synchronizing the system clocks between two chips. Chips 31 and 32
The source oscillation signal of the chip 32 is made common, and the input/output pin IO of the chip 32 is directly connected to the input/output pin 10 of the chip 31.

FIG. 4 is a waveform diagram of the shift registers 1, 2, 3, gates 6, 11, output buffer 8, and input/output pin IO of the chip 32 in the chip 31 at that time. It is assumed that chips 31 and 32 are not synchronized in the initial state. When the output of the input/output pin of the chip 32 outputs a low level, the gate 1 of the chip 31
The output of gate 1 is forced to a low level, and the output of gate 12
A low level is input to the shift register 1 in synchronization with a write timing using the input original oscillation signal as a write signal. Thereafter, the first and second system clocks are generated as described above and are system clocks that are synchronized with the chip 32 system clock.

In this way, even if the system clocks of multiple chips are not synchronized in the initial state, by making the source oscillation signal common and connecting the input and output pins of each chip, the system clocks can be synchronized based on the synchronization signal from one chip. As a result, the system clock of the other chip can be synchronized with the system clock of one chip, and the reset signal conventionally required for synchronization can be omitted.

As described above, the present invention uses an original oscillation signal commonly supplied to each chip as a write and read signal to a plurality of shift registers, and logically controls each output of the shift register so that the shift register operates as a ring counter. The input signal is fed back to the first stage shift register via the gate, and the input signal to the first stage shift register can be supplied from another chip, and the input signal supplied from the other chip is shifted based on the original oscillation signal. By doing this, it is possible to achieve synchronization within the chip.

In this embodiment, the initial state of the shift register is set to high level, but it can also be set to low level. In this case, it is obvious that the feedback NAND gate 6 may be a NOR gate. In addition, in LSI chips that use a low-level clock as the system clock, inverter 4
And there is no need to add 5. Furthermore, there is a gate (AND gate 1) that receives input signals from other chips.
As for 1), any gate circuit may be used as long as it does not depend on the output from the feedback gate 6 and gives priority to input signals from other chips. It is clear that such modifications of the logic gates can be designed as appropriate depending on the logic level of the signals used. Furthermore, since each output of the shift register is a signal having the same period as the system clock, it is clear that the output of the shift register at any stage can be used as the system clock.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining FIG. 1, FIG. 3 is a block diagram for synchronizing system clocks between multiple chips, and FIG. FIG. 4 is a waveform diagram for explaining FIG. 3. 1, 2, 3...shift register, 4, 5, 7,
9, 10, 12...Inverter, 6...NAND
Gate, 11...AND gate, 8...Output buffer, 10...Input/output terminal, Fos...Original oscillation.

Claims (1)

[Claims] 1. A plurality of shift registers connected in series whose shift clock is an original oscillation signal commonly supplied to multiple chips, a feedback circuit for driving these serially connected shift registers as a counter, and a shift clock supplied from other chips. a terminal for receiving an input signal, and an input signal from the terminal and a feedback signal from the feedback circuit, and when the input signal is input, the input signal is given priority and added to the first stage shift register. , and a gate circuit which applies the feedback signal to a first-stage shift register when the input signal is not present, and the output of any shift register is used as a system clock.