JP2565189B2 - Signal processing circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a signal processing circuit for digital signals, and particularly to miniaturization of the circuit scale.

[Outline of Invention]

According to the present invention, in a signal processing circuit for a digital signal, a flip-flop having a large number of inputs is used to share a flip-flop of a digital circuit having a different function, and the flip-flop is used to operate a digital circuit having a different function in a time division manner. As a result, the circuit scale is reduced.

[Conventional technology]

The digital signal processing circuit is composed of a plurality of digital circuits having different functions. These digital circuits having different functions operate independently.

Therefore, in the conventional digital signal processing circuit, the digital circuits having different functions are independently configured according to their functions.

[Problems to be solved by the invention]

In this way, if each digital circuit is independently configured according to its function, there is a limit to downsizing the circuit scale. If a plurality of digital circuits having different functions are operating for different times, common elements in each circuit can be shared to reduce the size of the circuit.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a signal processing circuit having a reduced circuit scale by sharing common elements in digital circuits having different functions.

[Means for solving problems]

This invention operates by a first clock signal and has at least one flip-flop as a component.
Second functional circuit and a second clock signal which operates by the second clock signal and has at least one flip-flop as a constituent element.
And at least a part of the flip-flops constituting the first and second functional circuits, and the first and second signal input terminals D ₁ and D ₂ and the first and second clock inputs. It is composed of two-input flip-flops F1 to F8 having terminals C ₁ and C ₂ and a common output terminal Q, and the first clock signal TCK is applied to the first clock input terminal and the second clock input terminal is applied to the second clock input terminal. The second clock signal PCK is supplied, the first and second clock signals TCK and PCK operate in a time division manner, and the first functional circuit becomes operable when the first clock signal TCK is in the operating state. The second functional circuit is operable when the second clock signal PCK is in the operating state.

[Action]

The 2-port flip-flops F1 to F8 are commonly provided for the digital retriggerable monostable multivibrator and two digital circuits having different functions of a parity generation or check circuit. Input terminal D ₁ of the two-port flip-flop F1~F7 is connected to the gate circuit G1 constituting the digital Little moth Bull monostable multivibrator. Input terminals of 2-port flip-flops F1 to F8
D ₂ is connected to a gate circuit G 2 which constitutes a parity generation or check circuit. Clock TC to clock input terminal 1
When K is supplied, these 2-port flip-flops F
1 to F7 operate as flip-flops for digital little gable monostable multivibrator. When the clock PCK is supplied to the clock input terminal 2, these 2-port flip-flops F1 to F8 operate as flip-flops for the parity generation or check circuit.

〔Example〕

An embodiment of the present invention will be described with reference to the drawings in the following order.

a. Basic configuration b. One embodiment c. Description of function as retriggerable mono-multi in one embodiment d. Description of function as parity generation or check circuit in one embodiment a. Basic configuration FIG. 1 shows a basic configuration of the invention. First
In the figure, F11, F12, F13 and F14 are multi-port (3 port) flip-flops, and G11, G12 and G13 are combination gate circuits. The multi-port flip-flop has a plurality of input terminals, a plurality of clock input terminals corresponding to the input terminals, and one output terminal. This first
Multiport flip-flops F11 to F14 in the figure are
Three input terminals D ₁ , D ₂ , D ₃ and three clock input terminals
It is a three-port flip-flop having C ₁ , C ₂ , C ₃ and one output terminal Q. This 3 port flip flop
F11~F14, when the clock to the clock input terminal C ₁ is supplied, operates as a flip-flop for data supplied to the input terminal D _1, the clock is supplied to the clock input terminal C _2, input It operates as a flip-flop for the data supplied to terminal D ₂ and operates on clock input terminal C ₃
When the clock is supplied to the input terminal, it operates as a flip-flop for the data supplied to the input terminal D ₃ .

The clock CK11 is supplied to the clock input terminal C ₁ of each of the 3-port flip-flops F11, F12, F13, and F14, the clock CK12 is supplied to the clock input terminal C ₂ , and the clock input terminal C ₃ is supplied to the clock input terminal C ₃ . The clock CK13 is supplied.

A digital circuit can be basically configured by a flip-flop that latches an input / output signal and a combination gate circuit between the flip-flop and the flip-flop. When the multi-port flip-flop is used, the flip-flops in the digital circuits having different functions can be shared.

When the clock CK11 is supplied to each of the three-port flip-flops F11 to F14, 3-port data AD11 supplied to the input terminal D ₁ of the flip-flop F11 is supplied to the gate circuit G11, 3 input ports flip-flop F12 D ₁
The data BD11 supplied to the gate circuit G11 is supplied to the gate circuit G11. The output of the gate circuit G11 is a 3-port flip-flop F.
The signal is supplied to the input terminal D _{1 of} 13 to operate the digital circuit having the first function. The output of the digital circuit having the first function is taken out from the output terminal OT.

When the clock CK12 is supplied to the three-port flip-flops F11 to F14, 3-port data AD12 supplied to the input terminal D ₂ of the flip-flop F11 is supplied to the gate circuit G12, 3 input terminal D ₂ port flip-flop F12 To the gate circuit G12. The output of the gate circuit G12 is supplied to the input terminal D ₂ of the 3-port flip-flop F13, and the output of the 3-port flip-flop F13 is supplied to the input terminal D ₂ of the 3-port flip-flop F14. The output of the 3-port flip-flop F14 is supplied to another digital circuit, and the digital circuit having the second function operates.

When the clock CK13 is supplied to the three-port flip-flops F11 to F14, 3-port data AD13 supplied to the input terminal D ₃ of the flip-flop F11 is supplied to the gate circuit G13, the input terminal D ₃ of 3 port flip-flop F12 To the gate circuit G13. The output of the gate circuit G13 is supplied to the input terminal D ₃ of 3 port flip-flop F13, a digital circuit of the third function operates. The output of the digital circuit having the third function is taken out from the output terminal OT.

Thus, while the clock CK11 is supplied to the 3-port flip-flops F11 to F14, the digital circuit having the first function is in the operating state, and while the clock CK12 is supplied to the 3-port flip-flops F11 to F14, While the digital circuit having the second function is in the operating state and the clock CK13 is supplied to the 3-port flip-flops F11 to F14, the digital circuit having the third function is in the operating state. These first
The circuit scale is reduced because the flip-flop is commonly used for the digital circuit having the third function.

b. One Embodiment FIG. 2 shows a digital retriggerable monostable multivibrator (hereinafter abbreviated as retriggerable monomulti).
1 shows an embodiment of the present invention in which digital circuits each having a separate function of a parity generation or check circuit are combined and configured. In FIG. 2, G1 surrounded by a broken line is a gate circuit that constitutes a retriggerable mono-multi, G2 is a gate circuit that constitutes a parity generation or check circuit, and F1 to F8 are retriggerable mono-multi and parity generation or check. It is a two-port flip-flop provided commonly to both the circuit and the circuit.

The 2-port flip-flop has two input terminals D ₁ and D _2.
And clock input terminals C ₁ and C ₂ to which clocks corresponding to the input terminals D ₁ and D ₂ are supplied, respectively, and a common output terminal Q. The 2-port flip-flop operates as a flip-flop for the data supplied to the input terminal D ₁ when the clock supplied to the clock input terminal C ₁ is operating, and the clock supplied to the clock input terminal C ₂ Operates as a flip-flop for the data supplied to the input terminal D ₂ .

Such a 2-port flip-flop can be realized by the configuration shown in FIG.

The 2-port flip-flop shown in FIG. 3 is a two-input dynamic flip-flop using MOS transistors. 101 and 102 in FIG.
The MOS transistors are shown, and input terminals 103 and 104 are derived from the drains of the MOS transistors 101 and 102, respectively. Gate of MOS transistor 101 to clock input terminal
105 is derived, and the clock input terminal 106 is derived from the gate of the MOS transistor 102. The sources of the MOS transistors 101 and 102 are commonly connected, and this connection point is connected to one end of the series connection of the MOS transistors 108 and 109 via the inverter 107. MOS transistors 108 and 109
The other end of the series connection of the output terminal 113 via the inverter 112
Connected to. Clock input terminals 110 and 111 are derived from the gates of the MOS transistors 108 and 109, respectively.

The first input data DA ₁ is supplied to the input terminal 103,
The second input data DA ₂ is supplied to the input terminal 104.
The clock input terminal 105 is supplied with the inverted clock {circle around ( ₁₎ } of the _first clock CK ₁ , and the clock input terminal 110 is supplied with the first clock CK ₁ . The clock input terminal 106 has an inverted clock ▲ ▼ of the _second clock CK _2.
2 is supplied, and the clock input terminal 111 is supplied with the second clock CK ₂ .

While the clock ( ₂₎ is at the low level, the MOS transistor 102 is turned off and the MOS transistor 109 is turned on. Therefore, if the clock CK ₁ is operated as shown in FIG.
Depending on the capacitance between the sources, as shown in FIG.
It operates as a flip-flop for data DA ₁ from 103.

While the clock ( ₁₎ is at the low level, the MOS transistor 101 is turned off and the MOS transistor 110 is turned on. Therefore, if the clock CK ₂ is operated as shown in FIG.
Depending on the capacitance between the sources, as shown in Fig. 4D, the input terminal
It operates as a flip-flop for data DA ₂ from 104.

When two flip-flops are formed on one chip, the chip area is twice as large as one flip-flop. However, when the two-port flip-flop is configured as described above, the buffer and the inverter can be shared, so that the chip area is less than twice that of one flip-flop.

Note that such a 2-port flip-flop can also be configured in the same manner as a static flip-flop.

In FIG. 2, the clock TCK shown in FIG. 5B is supplied from the terminal 1 to the clock input terminal C ₁ of the 2-port flip-flops F1 to F7. 2-port flip-flop F1
Each of the input terminals D ₁ of to F7 is connected to the gate circuit G1 and the input terminal 11 forming the retriggerable mono-multi. Therefore, when the clock TCK is supplied to the terminal 1, this embodiment operates as retriggerable mono-multi.

Clock input terminals of 2-port flip-flops F1 to F7
The clock PCK shown in FIG. 5A is supplied to the terminal C ₂ from the terminal 2. Input port D ₂ of 2-port flip-flops F1 to F8
Are connected to a gate circuit G2 that constitutes a parity generation or check circuit. Therefore, the clock at terminal 2
When supplied with PCK, this one embodiment operates as a parity generation or check circuit.

c. Description of Function as Little Gubbable Mono Multi in One Embodiment The operation when the function as the retriggerable mono multi is provided will be described with reference to FIG.

The clock TC shown in FIG. 7A is connected to the clock input terminal 1.
K is supplied, and this clock TCK is supplied to the clock input terminals C ₁ of the 2-port flip-flops F1 to F7. The 7th input terminal 11 derived from the 2-port flip-flop F1
When the trigger signal TG that is inverted at the time t ₁ shown in FIG.
It is supplied to the EX-OR gate 12 via F1 and is also supplied to the EX-OR gate 12 via two-port flip-flops F1 and F2. From the EX-OR gate 12 to time t as shown in FIG. 7C. _The set signal ST that is high level is output from ₂ to time t ₃ .

This set signal ST is supplied to the 2-port flip-flop F3 via the OR gate 13
F3 output is set to high level at time t ₃ as shown in FIG. 7 I. In addition, this set signal ST is
Is supplied to one input terminal of each of the AND gates 15, 16, 17, and 18 via.

The output of the AND gate 15 is a 2-port flip-flop F4.
And the output of the 2-port flip-flop F4 is inverted and supplied to the other input terminal of the AND gate 15. Therefore, the inverter 1 is connected to one input terminal of the AND gate 15.
When the set signal ST is supplied via 4 the 2-port flip-flop F4 outputs 2 of the clock TCK shown in FIG. 7D.
A clock with a double cycle is output.

The output of the 2-port flip-flop F4 is an EX-OR gate
It is supplied to one input terminal of 19 and the output of the EX-OR gate 19 is supplied to the 2-port flip-flop F5 via the AND gate 16. The output of 2-port flip-flop F5 is EX-
It is supplied to the other input terminal of the OR gate 19. AND gate 1
A high level is supplied to one of the input terminals of 6 after time t ₃ . Therefore, the 2-port flip-flop F5 outputs 2
The port flip-flop F5 outputs a clock having a cycle four times as long as the clock TCK shown in FIG. 7E.

The output of the 2-port flip-flop F4 and the output of the 2-port flip-flop F5 are supplied to the AND gate 20, and the output of the AND gate 20 is supplied to one input terminal of the EX-OR gate 21. The output of the EX-OR gate 21 is supplied to the 2-port flip-flop F6 via the AND gate 17, and the output of the 2-port flip-flop F6 is supplied to the other input terminal of the EX-OR gate 21. Therefore, the 2-port flip-flop
Due to the output of the AND gate 20, the F6 outputs from the 2-port flip-flop F6 a clock having a cycle eight times as long as the clock TCK shown in FIG. 7F.

Output of AND gate 20 and 2-port flip-flop F6
Is supplied to the AND gate 22. The output of the AND gate 22 is supplied to the EX-OR gate 23. The output of the EX-OR gate 23 is supplied to the 2-port flip-flop F7 via the AND gate 18, and the output of the 2-port flip-flop F7 is EX-OR.
It is supplied to the other input terminal of the gate 23. Therefore, 2
The output of the AND gate 22 of the port flip-flop F7 causes the flip-flop F7 to output a clock having a cycle 16 times as long as the clock TCK shown in FIG. 7G.

In this way, the 2-port flip-flops F4, F5, F6, F7
Thus, a counter that forms a clock having a cycle 16 times the cycle of the clock TCK is configured.

Output of AND gate 22 and 2-port flip-flop F7
Is supplied to the NAND gate 24. The output of the NAND gate 24 is supplied to one input terminal of the AND gate 25. Two-port flip-flop on the other input terminal of AND gate 25
The output of F3 is supplied. The output of AND gate 25 is OR gate 1
3 is supplied to the other input terminal.

From the NAND gate 24, as shown in FIG. 7 H, the time t ₄
The low-level reset signal RE is output from the time to the time t ₅ . This reset signal RE is AND gate 25, OR gate
It is supplied to the 2-port flip-flop F3 via 13 and the 2-port flip-flop F3 is reset by the fall of the reset signal RE. Therefore, as shown in FIG. 7 I, the output of the time t ₅ in the two-port flip-flop F3 goes low.

As described above, the 2-port flip-flop F3 is set by the set signal ST formed by the inverted trigger signal TG shown in FIG.
It is reset by a reset signal RE formed by a counter composed of F4 to F7. Therefore, the output terminal 26 outputs a pulse (FIG. 7I) having a width τ which is 16 times the cycle of the clock TCK.

When the trigger signal TG is supplied again, the set signal ST appears and the output of the inverter 14 becomes low level. Therefore, the counter composed of the 2-port flip-flops F4 to F7 is reset. This enables retrigger.

Therefore, as shown in FIG. 8A, the time t ₀₁ , t ₀₂ , t
_03, t _04, in the trigger signal TG to be inverted is supplied to the input terminal 11, as shown in FIG. 8 B, the trigger signal that is inverted at the time t _01, the pulse from the time t ₀₁ pulse width τ By the trigger signal that is output and inverted at time t ₀₂ ,
A pulse having a pulse width τ is output from time t ₀₂ , a trigger signal that is inverted at time t ₀₃ causes a pulse to be output from time t ₀₃ , and this pulse is re-triggered by a trigger signal that reverses at time t _{04. A} high-level pulse is output until time t _05, which is a time constant τ after ₀₄ .

d. Description of Function as Parity Generation or Check Circuit in One Embodiment The operation when the function as a parity generation or check circuit is provided will be described with reference to FIG.

The clock PCK is supplied to the clock input terminal 2. Data D0 to D7 are supplied to the input terminals 50 to 57, respectively. The load signal XL is supplied to the terminal 92.

The data D0 to D7 supplied to the input terminals 50 to 57 are EX
Supply to one input terminal of each of OR gates 60-67. The outputs of the EX-OR gates 60 to 67 are supplied to the 2-port flip-flops F1 to F8, respectively. The outputs of the 2-port flip-flops F1 to F8 are supplied to one input terminals of the AND gates 70 to 77, and the parity output terminals 80 to 81 are derived from the 2-port flip-flops F1 to F8, respectively. The other input terminal of AND gates 70 to 77 is connected to terminal 92.
The load signal XL is supplied from. Further, the outputs of the 2-port flip-flops F1 to F8 are supplied to the OR gate 90, and the decision output terminal 91 is derived from the inverted output of the OR gate 90.

Then even parity Is Required by. Even parity when (i = 3) Is Is required.

Even parity when (i = 3) In order to obtain, as shown in FIG. 10B, times T _{1 to} T ₃
During this period, the load signal XL supplied to the terminal 92 is at low level. As shown in FIG. 10C, data is collected at time T _{1 to} T ₃ . There is supplied to the input terminal 50 to 57, the data at time T ₃ through T ₅ There is supplied to the input terminal 50 to 57, the data at time T ₅ through T ₇ Is supplied to the input terminals 50 to 57. At times T _{2 to} T ₄ , the 10th
As shown in Figure D, the data Are held in the 2-port flip-flops F1 to F8. EX−
This 2-port flip-flop is provided by OR gates 60 to 67.
Mod.2 addition is performed on the data held in F1 to F8 and the data supplied to the input terminals 50 to 57. Therefore, at times T _{4 to} T ₆ Is sought, at times T _{6 to} T ₈ Is sought, parity Is obtained. This parity Are output from the parity output terminals 80 to 87.

Parity check data And paridi And mod.2 addition, This is done by judging the addition output. In the case of even parity, if no error has occurred, this addition result is 0. If an error has occurred, the addition result will be 1.

When performing the parity check, as shown in FIG. 11B, the load signal XL supplied to the terminal 92 is at the low level during the time T _{11 to} T ₁₂ . Data from time T _{11 to} T ₁₂ Is supplied to each of the input terminals 50 to 57, and the data is supplied at time t _{12 to} t ₁₃ . Are supplied to the input terminals 50 to 57, respectively, and data are collected at the times t _{13 to} t ₁₄ . Is supplied to each of the input terminals 50 to 57. Parity at times T _{14 to} T ₁₅ Is supplied. EX-OR gates 60 to 67 enable data And mod.2 are added. As shown in FIG. 11D,
It is determined whether the addition result is 0 or 1. If this addition result is 0, it is determined that there is no error, and the determination output terminal 91
Output becomes high level. When the addition result is 1, the output of the determination output terminal 91 becomes low level.

The digital circuit in which the retriggerable monaural unit shown in FIG. 2 and the parity generation or check circuit are combined is
If the output of the determination output terminal 91 is supplied to the input terminal 11, the parity check is performed, and when it is determined that there is no error, the circuit operates as a circuit that outputs a pulse of a predetermined width.

As is clear from the configuration of the embodiment shown in FIG. 2, when a multi-port flip-flop is used as the common circuit of the flip-flops, the scale of the gate circuit tends to increase. Therefore, it is desirable to configure the gate circuit using PLA (Programmable Logic Array).

〔The invention's effect〕

According to the present invention, the flip-flops of the digital circuits having different functions can be shared by using the multi-port flip-flops in a time division manner.
Therefore, the digital signal processing circuit can be downsized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a connection diagram of an example of a 2-port flip-flop in an embodiment of the present invention. FIG. 4 is a waveform diagram used to explain the two-port flip-flop in one embodiment of the present invention, FIG. 5 is a waveform diagram used to explain one embodiment of the present invention, and FIG. 6 is a waveform diagram used in one embodiment of the present invention. FIG. 7 is a block diagram used for explaining the function of No. 1, FIG. 7 and FIG. 8 are waveform diagrams used for explaining the first function in one embodiment of the present invention, and FIG. A block diagram used for explaining the function, FIGS. 10 and 11 are waveform diagrams used for explaining the second function in the embodiment of the present invention. Description of main symbols in the drawings F1 to F8: 2-port flip-flops, G1: Gate circuit configuring a digital retriggerable monostable multivibrator, G2: Gate circuit configuring a parity generation or check circuit.

Claims (1)

(57) [Claims] 1. A plurality of functional circuits for realizing mutually different functions, a plurality of signal input terminals corresponding to the number of the functions, and a clock for receiving signals respectively supplied to the plurality of signal input terminals are provided. Has a plurality of clock input terminals and a common output terminal. When a clock is supplied to each of the plurality of clock input terminals, it operates as a flip-flop for a signal given to a signal input terminal corresponding to the clock input terminal. It is composed of a plurality of multi-port flip-flops, and each signal input terminal of the plurality of multi-port flip-flops is assigned to each of the functions, and a clock to be given to the clock input terminal of each of the multi-port flip-flops is provided for each of the functions. Set and operate the multi-port flip-flops for each function in a time division manner. Signal processing circuit is characterized in that so as to.