JP2567463B2 - Programmable input / output circuit - Google Patents

Description

Detailed Description of the Invention [Industrial applications]

The present invention relates to a programmable input / output circuit which is connected to an input pin or an output pin of an integrated circuit such as a programmable logic device and which enables programmable logic processing of an input signal or an output signal.

[Prior art]

2. Description of the Related Art Conventionally, programmable logic devices (PLDs) and the like have been used as integrated circuits (ICs) that allow users to implement logic functions corresponding to applications with high integration. The PLD includes a plurality of programmable logic elements, and the input / output of each logic element can be arbitrarily connected by programmable wiring. An external input signal to the PLD is generally directly input to a predetermined input terminal of a programmable circuit portion (for example, AND plane) of the logic element. As an example of the configuration of the logic element used in the conventional PLD, Japanese Patent Laid-Open No.
There is one proposed in Japanese Patent Publication No. 2-58722. As shown in the configuration diagram of FIG. 12, this logic element is a functional cell 10 that realizes a counter, a shift register, etc. after a logic output of a programmable circuit portion (AND plane 100 and OR plane 101).
It incorporates 2. Also in this example, the input signal from the outside is AND plane 1
Must be input to the input terminal 103 of 00.

[Problems to be Solved by the Invention]

However, the PLD according to the above conventional technique has the following problems. (1) When performing an input process such as removal of a noise component included in an input signal, the AND plane 100 or the like must be used without fail, so that the use efficiency of the element is significantly reduced. (2) Similarly, since the AND plane 100 or the like is used, the area of the circuit becomes large and the operation speed of the circuit becomes slow. The present invention was devised to solve the above-mentioned problems, and is connected to an input pin or an output pin of an integrated circuit to enable programmable input / output signal processing, and the present input / output circuit. Is used for PLD, it increases the use efficiency of programmable logic elements
An object is to provide a programmable input / output circuit that makes it possible to obtain D.

[Means for achieving the object]

The present invention, in a programmable input / output circuit connected between an input pin or output pin of an integrated circuit connected to an external circuit and an internal circuit, connects the input / output circuit to the input pin of the integrated circuit or the internal circuit. Input terminal for
An output terminal for connecting the input / output circuit and an output pin of the internal circuit or the integrated circuit, a plurality of storage elements, at least one combinational logic circuit, an input side of each storage element and the combinational logic circuit, or A plurality of programmable selectors provided on the output side, at least one of the storage elements is cascade-connected to another storage element via one of the selectors, and the input terminal of the selector is Two or more signals are connected from among signals including an input pin signal, a storage element output signal, and a combination logic circuit output signal, and the output selected by the selector is connected to the storage element input terminal and combination logic. The above object is achieved by connecting either the input terminal of the circuit or the output pin. Further, at least one dynamic selector circuit whose connection state can be controlled by a selection signal is provided, and the dynamic selector circuit selects a signal output from another input / output circuit or a signal selected from the input pin. Is supplied to the storage element or one input terminal of a selector provided on the input side thereof, and one output signal of the storage element can be supplied to other input / output circuits. Further, one of the selectors is connected so as to select any one of a plurality of clocks supplied to the input / output circuit and supply it to one of the storage elements. Further, one of the selectors is connected so as to select and output either one output of the storage element or an inverted output.

[Action and effect]

According to the present invention, direct connection to an input / output pin of an integrated circuit is possible, and an input signal applied to an input pin or an output signal from an output pin can be directly processed with the shortest wiring. Further, the programmable selector and the storage element for holding an input signal can efficiently form an input / output circuit and can be formed small in area. In this way, the direct processing of the input / output signals, the shortest wiring and the structure in which the area is reduced can increase the operation speed. In addition, when this input / output circuit is used for PLD, programmable logic elements can be used only for the configuration of the original logic function, and the utilization efficiency of PLD can be improved to obtain high density PLD. it can. Further, at least one dynamic selector circuit is provided so that a signal output from another input / output circuit can be input to a storage element and an output signal of the storage element can be supplied to another input / output circuit. In that case, connection with other input / output circuits becomes possible and expansion becomes easy.

【Example】

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In this embodiment, the input terminal 1 of the input / output circuit, the three D-type flip-flops 2, 3, and 4 which are storage elements, one combinational logic circuit 5, and each flip-flop 2, 3, and 4 are provided.
Of selectors 6, 7, which select the input of
8, 9 and 10, selectors 11 and 12 for programmable selection of the input of the combinational logic circuit 5, and selector 14 for programmable selection of the output to the output terminal 13 of the input / output circuit. The signal input to the D input of the flip-flop 2 is selected by the selector 6. The input signal of the input terminal 1, the inverted output of the flip-flop 2 itself and the inverted output of the other flip-flop 3 are connected to the input of the selector 6, and any one of them can be arbitrarily selected. The signal input to the clock input CK of the flip-flop 2 is selected by the selector 7. The selector 7
Two clocks, for example, a high-speed clock CLK ₁ and a low-speed clock CLK _2, etc., are input to the, and any one of them can be arbitrarily selected. Other examples of these two clocks include those having the same frequency and the phases shifted (including those having the mutually inverted relationship). The signal input to the D input of the flip-flop 3 is selected by the selector 8. The input of the selector 8 is connected to the output of the flip-flop 2 and the selector 6
Selection output is connected and any one of them can be arbitrarily selected. The selection output of the selector 9 is connected to the clock input CK of the flip-flop 3, and
One of the two clocks CLK ₁ and CLK ₂ is arbitrarily selected and input. Although the combinational logic circuit 5 is configured as an AND circuit in this embodiment, it may be configured as an OR circuit or a NOR circuit. The signal input to the combinational logic circuit 5 is the selector.
11 and selector 12 respectively. The selector 11
The output Q of the flip-flop 2 and the inverted output of the flip-flop 2 are connected to the input of, and any one of them can be arbitrarily selected. The output of the flip-flop 3 and the inverted output are connected to the input of the selector 12, and any one of them can be arbitrarily selected. The output of the combinational logic circuit 5 is connected to the D input of the flip-flop 4, while the select output of the selector 10 is connected to the clock input CK, and the two clocks CLK ₁ and CLK ₂ described above are connected. Is selected and input. The signal output to the output terminal 13 is the selector 14
Is selected. The input of the selector 14 is the input terminal 1
Of the flip-flop 2, the output Q of the flip-flop 2, the output of the combinational logic circuit 5, and the output Q of the flip-flop 4 are connected, and any one of them can be arbitrarily selected. FIG. 2 is a circuit diagram showing one configuration example of a programmable selector. This selector is a two-input selector composed of two N-channel MOS transistors 15 and 16. The signal A is connected to the input side of one transistor 15, the signal B is connected to the input side of the other transistor 16, and the output sides of the two transistors are commonly connected. Either one of the inputs A or B is selected as the output C by making either of the two transistors 15 and 16 conductive by plugging. FIG. 3 is a circuit diagram showing another configuration example of the programmable selector. This selector is a two-input selector consisting of three NAND gates 17, 18, 19 and an inverter 20. NAND gate 17
When the signal obtained by inverting the gate input I by the inverter 20 is at high level, the gate is opened and one input A is passed. The NAND gate 18 opens when the gate input I is at high level, and allows the other input B to pass. The NAND gate 19 functions as an OR circuit in which the input from the NAND gate 17 or 18 is a negative logic input, and one of the inputs is a positive logic and is an output C. The gate input I is freely set by plugging, and if set to high level,
The NAND gate 17 is closed and the NAND gate 18 is opened, so that the input B is selected. Conversely, if it is set to low level, the NAND gate 17 opens and the NAND gate
Gate 18 is closed and input A is selected. In the embodiments of the selectors shown in FIGS. 2 and 3, the case of two inputs has been described, but if the number of gate elements or circuits is increased according to the inputs, a selector with multiple inputs such as three inputs and four inputs will be the same. Can be formed. It is also possible to form the gate element by a complementary transfer gate composed of an N-channel type MOS transistor and a P-channel type MOS transistor. Hereinafter, application examples of the input / output circuit configured by using the first embodiment having the above configuration will be described. FIGS. 4 (a) and 4 (b) show a low level detection circuit diagram (a) of an input signal, which is one application example of the input / output circuit configured by using the first embodiment, and its operation. It is a timing chart (b). In the circuit diagram (a), the selector is omitted and only the result selected by the selector is shown. The clock input CK of flip-flop 4 is the clock input to the clock input CK of flip-flops 2 and 3.
Clock CLK _{2, which} is the inverse of CLK ₁ , is input. Input terminal 1
The signal IN input from is input to the D input of the flip-flop 2, and its output Q is the D input of the flip-flop 3 in the next stage. The inverted outputs of the flip-flop 2 and the flip-flop 3 are input to the combinational logic circuit 5, and the logical product is used as the D input of the flip-flop 4. Output terminal 13
Output OUT of the flip-flop 4 is selected. This input / output circuit, as shown in FIG. 4 (d), does not change to a low level until the input signal IN is continuously at a low level of 1.5 clocks or more due to the shift function of the flip-flops 2, 3, and 4. Detected at output OUT. Input signal IN
If the low level of is less than 1.5 clock, it is not detected at the output OUT and its input signal IN can be regarded as noise and eliminated. FIGS. 5 (a) and 5 (b) are another example of the application of the input / output circuit configured by using the first embodiment, and FIG. 5 (a) is a high level detection circuit diagram of an input signal and its operation. Is a timing chart (b). The circuit configuration is the same as that shown in FIG. 4A, except that the input of the combinational logic circuit 5 is the outputs Q of the flip-flops 2 and 3. As shown in FIG. 5 (b), this input / output circuit does not change to a high level until the input signal IN is continuously at a high level of 1.5 clocks or more by the shift function of the flip-flops 2, 3, and 4. Detected at output OUT. Input signal IN
If the high level of is less than 1.5 clock, it is not detected at the output OUT, and its input signal can be regarded as noise and eliminated. 6 (a) and 6 (b) are still another application example of the input / output circuit configured by using the first embodiment, which is a falling edge detection circuit diagram of an input signal (a), It is a timing chart (b) showing the operation. Also in this circuit, the flip flops 2 and 3 are connected in the same manner as in FIG. 5 (a) to form a shift circuit. The inverted output of the flip-flop 2 and the output Q of the flip-flop 3 are selected and input to the input of the combinational logic circuit 5, and the logical product thereof is output to the output terminal 13. If the set inputs S of the respective flip-flops are connected to each other and the SET input is applied from the outside,
It is suitable because it can be used as the lock of the output OUT at the time of initializing when the power is turned on or as the enable input at the time of operation. This input / output circuit, as shown in FIG.
If the input is at high level, the shift function of flip-flops 2 and 3 shifts one clock from the shift of the low level of the input signal IN to the flip-flop 2 in the preceding stage to the shift in the flip-flop 3 in the subsequent stage. During this period, the output OUT can be sent out. FIGS. 7 (a) and 7 (b) are still another application example of the input / output circuit configured by using the first embodiment, and FIG. 7 (a) is a rising signal detection circuit diagram of the input signal and its operation. Is a timing chart (b). The circuit configuration is such that the signal input to the combinational logic circuit 5 is the output Q of the flip-flop 2 and the inverted output of the flip-flop 3, and the reset terminals of each of the flip-flops 2 and 3 are connected to reset from the outside. It is the same as FIG. 6 (a) except that the input is possible. If the RESET input is provided in this way, it is suitable because it can be used as the lock of the output OUT at the time of initialization such as when the power is turned on, or as the enable input during operation. This input / output circuit, as shown in FIG.
If T input is high level, flip-flop 2, 3
With the shift function of (1), the output OUT can be sent for one clock from the time when the high level of the input signal IN is shifted to the front flip-flop 2 to the time when it is shifted to the rear flip-flop 3. FIGS. 8 (a) and 8 (b) are still another example of the application of the input / output circuit constructed by using the first embodiment.
FIG. 2 is a circuit diagram (a) and a timing chart (b) thereof that configures a 1/2 frequency divider circuit of CLK ₁ . This frequency dividing circuit returns its inverted output to the D input in the flip-flop 2 and outputs the output Q to the output terminal 13. In this way, as shown in FIG. 8 (b),
Clock CLK ₁ can be divided in half. FIGS. 9 (a) and 9 (b) are clocks showing another example of application of the input / output circuit constructed by using the first embodiment.
FIG. 2A is a circuit diagram (a) and its timing chart (b) that constitutes a 1/4 frequency divider circuit of CLK _1. FIG. This frequency divider circuit inputs the same clock CLK ₁ to the clock input CK in the flip flops 2 and 3, inputs the inverted output of the flip flop 3 into the D input of the flip flop 2, and inputs the flip flop 2 into the D input of the flip flop 3. Input the output Q. The output Q of the flip-flop 3 is output to the output terminal 13. If you do this,
As shown in FIG. 9B, the clock CLK ₁ can be divided into 1/4. As described above, in the first embodiment, the programmable selector makes it possible to freely construct an input / output circuit that directly processes an input signal or an output signal. Therefore, the input signal from the input pin of the integrated circuit or the output signal to the output pin can be processed with the shortest wiring, which is advantageous in increasing the operation speed. In addition, since the configuration is programmable and is always suitable for the input / output circuit, and there is little waste, it can be formed in a smaller area than the configuration of the input / output circuit using programmable logic elements, and the operating speed can be increased. It is possible to increase the speed and improve the efficiency of use of the device. FIG. 10 is a circuit diagram showing a second embodiment of the present invention which facilitates expansion. This embodiment is similar to the first embodiment in that the input terminal 1 of the input / output circuit and the three D-type flip flops 2, 3, 4 are used.
, One combinational logic circuit 5, eight selectors 6,
7,8,9,10,11,12,14 and output terminal of input / output circuit
A programmable input / output circuit having an input terminal 21 from an adjacent input / output circuit (Input Output Block; IOB), a signal (A) input from the input terminal 21 and the input terminal 1 A dynamic selector circuit that supplies the signal (C) selected from the signals (B) to the selector 6 that selects the input D of the flip-flop 2.
22 and a parallel-serial switching terminal 23 for inputting a signal (S) for switching to the dynamic selector circuit 22.
And the output signal of the flip-flop 2 to the adjacent IO
An output terminal 24 for outputting to B is added. A signal input to one of the input terminals of the selector 6 is selected by the dynamic selector circuit 22. The inputs A and B of the dynamic selector circuit 22 are connected to adjacent IOs.
The output signal of B and the input signal of the input terminal 1 are connected, and the input / output circuit is used in parallel state independent of each other according to the state of the switching signal S input from the parallel to serial terminal 23. Alternatively, it can be arbitrarily selected during operation whether to be used in a serial state connected to each other. FIG. 11 is a circuit diagram showing one structural example of the dynamic selector circuit 22. The dynamic selector circuit 22 is a two-input selector including two N-channel type MOS transistors 25 and 26 and an inverter 27. The signal A is connected to the input side of one transistor 25, the signal B is connected to the input side of the other transistor 26, and the output sides C of the two transistors are commonly connected. One of the transistors 25 and 26 is turned on and the other is turned off by the switching signal S or a signal obtained by inverting the switching signal S by the inverter 27.
Either the input A or the input B is the output C. In the second embodiment, the flip-flop 2 of the first stage is used.
Since the output from the adjacent IOB can also be input as the input of, the expansion by the serial connection of the input / output circuit is easy. Note that the storage element that should be able to input the output from the adjacent IOB is not limited to this, and may be the flip-flops 3 and 4 in the second and subsequent stages or in the final stage. Further, different signals may be input to two or more storage elements. Further, in the second embodiment, the output from the adjacent IOB is not directly inputtable to the storage element but is inputtable through the programmable selector 6, so that the selection range of the input signal of the storage element is wide. It should be noted that the output from the adjacent IOB may be directly input to the storage element without going through the selector 6. Further, in the second embodiment, since the output to the adjacent IOB is output from the flip-flop 2 itself, which is capable of receiving the output from the adjacent IOB, the expansion is easy. The storage elements that should output signals to the adjacent IOBs are not limited to this, and the flip-flops 3 and 4 in the second and subsequent stages or the final stage may be used. Further, it may be possible to output from two or more storage elements. It should be noted that the present invention is not limited to the circuits of the first and second embodiments, and for example, a signal output to the output terminal is changed by the selector to a signal from the input terminal (pin),
It can be arbitrarily configured so that either the signal from the output of the D-type flip-flop or the signal from the output of the combinational logic circuit can be selected. In addition, the signal input to the D input of the D-type flip-flop and the signal from its own output are input to the input terminal (pin) by the selector.
From the output of the combinational logic circuit,
It can be arbitrarily configured so that either the signal from the output of the other D-type flip-flop can be selected. Further, the input of the combinational logic circuit uses the selector to select one of the signal from the output of the other combinational logic circuit, the signal from the input terminal (pin), and the signal from the output of the D-type flip-flop. It can be arbitrarily configured so that it can be selected. Further, the clock input of the D-type flip-flop may be arbitrarily selected from the signals from its own output in addition to the clock input from the outside. As described above, the present invention can be variously applied and embodied along the gist of the invention.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a circuit diagram showing a configuration example of a programmable selector used in the first embodiment, and FIG. 3 is a first embodiment. 4 is a circuit diagram showing another configuration example of the programmable selector used in FIG. 4, FIGS. 4 (a) and 4 (b) are a low level detection circuit diagram showing an application example of the first embodiment and its operation timing chart, FIG. FIGS. 6 (a) and 6 (b) are high-level detection circuit diagrams showing other application examples of the first embodiment and their operation timing charts, and FIGS. 6 (a) and 6 (b) are further diagrams of the first embodiment. Falling edge detection circuit diagram showing another application example and its operation timing chart. FIGS. 7A and 7B show a rising edge detection circuit diagram showing still another application example of the first embodiment and its operation. Timing chart, FIGS. 8 (a) and 8 (b) show the first embodiment. FIG. 9 (a) and FIG. 9 (b) are 1/2 division circuit diagrams showing still another application example of FIG. 9 and operation timing charts thereof, and FIG. Circuit diagram and its operation timing chart, FIG. 10 is a circuit diagram showing a second embodiment of the present invention, FIG. 11 is a circuit diagram showing an example of the configuration of a dynamic selector circuit used in the second embodiment, FIG. 12 is a block diagram showing a conventional example of a programmable logic element. 1, 21 ... Input terminal, 2, 3, 4 ... D-type flip-flop (memory element), 5 ... Combination logic circuit, 6, 8, 11, 12, 14 ... Selector, 13, 24 ... Output Terminal, 22 …… Dynamic selector circuit, 23 …… Switching terminal.

Claims (4)

(57) [Claims] 1. A programmable input / output circuit connected between an input pin or output pin of an integrated circuit connected to an external circuit and an internal circuit, wherein the input / output circuit is connected to an input pin of the integrated circuit or an internal circuit. Input terminal for connecting the input / output circuit and the output pin of the internal circuit or the integrated circuit, a plurality of storage elements, at least one combinational logic circuit, and each storage element and set A plurality of programmable selectors provided on the input side or the output side of the matching logic circuit, wherein at least one of the storage elements is cascade-connected to another storage element via one of the selectors; 2 or more signals among signals including the input pin signal, the storage element output signal, and the combinational logic circuit output signal are connected to the input terminal of Was selected output data, the input terminal of said memory element, an input terminal of the combinational logic circuit, a programmable input-output circuit, characterized in that it is connected to one of said output pins. 2. The device according to claim 1, further comprising at least one dynamic selector circuit whose connection state can be controlled by a selection signal, and a signal output from another input / output circuit by the dynamic selector circuit. A signal selected from the signals from the input pins is supplied to one input terminal of the storage element or a selector provided on the input side, and one output signal of the storage element is input to another input / output circuit. A programmable input / output circuit that can also be supplied. 3. The selector according to claim 1, wherein one of the selectors is connected to select one of a plurality of clocks supplied to the input / output circuit and supply it to one of the storage elements. A programmable input / output circuit characterized in that 4. The programmable input / output according to claim 1, wherein one of the selectors is connected to select and output either one output or inverted output of the storage element. circuit.