KR0134270B1 - Feed back shift register - Google Patents

Abstract

The present invention relates to a feedback shift register for processing two states during a clock by using a T flip flop, wherein a plurality of T flip flops are connected in series, and each toggle input T of each of the T flip flops is directly sheared. A T flip-flop group connected to a non-inverted output terminal (Q) of a T flip-flop (T) for providing a non-inverted output and a clock signal of each T flip-flop as a status signal; A NOR gate for negating and inverting the inverted output and the non-inverted output of the T flip flop connected to the last end of the T flip flop group; And the output of the clock signal and the output of the NOR gate are ANDed to provide a toggle input terminal of a T flip flop positioned at the first end of the T flip flop group.

Description

Feedback shift register

1 is a detailed block diagram showing a feedback shift register of the prior art.

2 is an operation timing diagram according to FIG.

3 is a detailed block diagram showing an embodiment of the present invention.

4 is an operation timing diagram according to FIG.

* Description of the symbols for the main parts of the drawings *

31,32,33,34: T flip flop 41: Ora gate

43: end gate

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a feedback shift registor used in sequential generators, counters, serial / parallel converters, and the like, in particular for two clocks using a T flip-flop. It relates to a feedback shift register for processing the state of.

In general, one of the most commonly used circuits in computers is the multivibrator (multivibrator). Among them, bistable multivibrators are the most commonly used circuits, and they are used for counters that control timing required for various operations of the computer and counters that perform arithmetic operations.

At this time, the counter circuit can be divided into synchronous and asynchronous. FIG. 1 shows a conventional 4-bit feedback shift register composed of a D flip-flop among the counters described above.

First, the 4-bit feedback shift register has four D flip flops 11, 12, 13, and 14 connected in series, and the clock stages C1 and C2 of each D flip flop 11, 12, 13, and 14 are connected in series. The clock signal CLK is simultaneously input to the C3 and C4, and the reset signal RST is also applied to the reset stages R1, R2, R3, and R4 of the D flip-flops 11, 12, 13, and 14, respectively. Are simultaneously applied, while the status signals S1, S2, S3, and S4 are applied to four bits by the non-inverting output terminals Q1, Q2, Q3, and Q4 of the respective D flip-flops 11, 12, 13, and 14. Is configured to output.

In addition, the exclusive NOR gate 15 exclusively ORs the outputs S3 and S4 of the non-inverting output terminals Q3 and Q4 of the D flip flops 13 and 14 and inverts the result, thereby inverting the result of the D flip flop. It is configured to input to (11).

The operation description of the prior art feedback shift register configured as described above is as follows.

First, a reset signal RST is applied to each of the reset stages R1, R2, R3, and R4 of the D flip flops 11, 12, 13, and 14 (FIG. 2A), so that each D flip flop ( 11, 12, 13, 14 (initialization of Fig. 2 (c), (d), (e), (f)) outputs logic 0000, and then D flip flops (11, 12, 13, 14). The clock signal CLK is applied to the clock stages C1, C2, C3, and C4 of FIG. 2 (b), and the non-inverting outputs S3 and S4 of the D flip-flop 13 and 14 are exclusive NOR gates. Exclusively by (15) and then inverted and latched to the D flip flop 11 and the output S1 of the D flip flop 11 is latched to the D flip flop 12 and the output of the D flip flop 12 ( S2 is latched to the D flip flop 13, and the output S3 of the D flip flop 13 is latched to the D flip flop 14, respectively, so that the output of each D flip flop 11, 12, 13, 14 (S1). , S2, S3, S4 is the logic 1000 (FIG. 2 (c), (d), (e), (f)).

When the clock signal CLK is applied to each of the D flip flops 11, 12, 13, and 14 after being latched to each of the D flip flops 11, 12, 13, and 14, the rising edge of the clock signal is applied. (rising edge) the output S1 of the D flip flop 11 to the D flip flop 12, the output S2 of the D flip flop 12 to the D flip flop 13, the D flip flop 13 Output S3 is latched to the D flip flop 14, respectively, and the D flip flop 11 is exclusively ORed after the D flip flop 13 and the outputs S3 and S4 of the D flip flop 14 The inverted signal is latched so that the outputs S1, S2, S3, S4 of each of the D flip flops 11, 12, 13, and 14 become logic 1100 (FIG. 2 (c), (d), ( e), (f)).

As can be seen above, when the clock signal CLK is continuously applied to the clock stages C1, CC2, C3, C4 of each of the D flip flops 11, 12, 13, 14, the output of the feedback shift register ( S1, S2, S3, S4) is 0000,1000,1100,1110,0111,1011,1101,0110,0011,1001,0100,1010,0101,0010,0010,0001,0000 and 16 status signals are sequentially Output (FIG. 2 (c), (d), (e), (f)).

However, the conventional feedback shift register has a problem in that the operation speed is limited when the sequential circuit is required at a high speed, and it is composed of a D flip-flop, thereby having a large area when applying the product.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a feedback shift register capable of improving an operation speed and reducing an area occupied by a product.

According to the present invention, a plurality of T flip flops are connected in series to achieve the above object, and each toggle input terminal of each of the T flip flops is connected to a non-inverted output terminal of a T flip flop located immediately before each of the T flip flops. A group of T flip flops in which a non-inverting output and a clock signal are provided as status signals; A NOR gate for negating and inverting the inverted output and the non-inverted output of the T flip flop connected to the last end of the T flip flop group; And the output of the clock signal and the output of the NOR gate are ANDed to provide a toggle input terminal of a T flip-flop for the first stage of the T flip-flop group.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a detailed block diagram illustrating an embodiment of the present invention configured by connecting four T flip flops, wherein four T flip flops 31, 32, 33, and 34 are connected in series, and each T flip flop 31 is connected. The discharge input terminal T of 32, 33, 34 is connected to the non-inverted output terminal Q of the previous stage, and the outputs S1, S2, S3 of the respective T flip flops 31, 32, 33 and The signal in which the clock signal CLK is combined becomes the output CLK, S1, S2, S3 of the feedback shift register.

In addition, the toggle input terminal of the first T flip-flop 31 has logics for outputting the non-inverting output terminal Q of the last T flip-flop 34, the outputs S4 and S5 of the inverting output terminal Q, and the clock signal CLK. The combined signal can be input and the reset signal RST is simultaneously applied to the reset terminals R5, R6, R7, and R8 of the respective T flip flops 31, 32, 33, and 34.

In this case, a logic combination of the non-inverting output terminal Q of the T flip-flop 34, which is a toggle input signal of the T flip flop 31, and the outputs S4 and S5 of the inverting output terminal Q and the clock signal SLK is performed. The signal is divided into OR gates 41 and OR gates 41, which OR-outputs the outputs S4 and S5 of the inverted output terminal Q of the non-inverted output terminal Q of the T flip-flop 34. The output signal is generated by an AND gate 42 which multiplies the output signal with the clock signal CLK and outputs the output signal to the toggle input terminal of the T flip-flop 31.

The operation of the embodiment of the present invention configured as described above will be described with reference to FIG.

First, a reset signal RST is applied to each of the reset stages R5, R6, R7, and R8 of the T flip flops 31, 32, 33, and 34 (FIG. 4 (a)). 31, 32, 33 and 34 are initialized (Figs. 4 (c), (d), (e), and (f)) to output logic 0000, and then the clock of the first period at one input terminal of the AND gate 42 is output. When a clock signal having a high state is applied (CLK) (FIG. 4B), logic 1 is input to the toggle input terminal T of the T flip-flop 31 (see FIG. 4C).

That is, when the OR gate 41 receives the inverted output S5 and the non-inverted output S4 of the T flip flop 34 and inputs an output (logic 1) obtained by logically adding the same to the type force terminal of the AND gate 42, The AND gate 42 inputs the output of the high state of the first clock signal CLK and the output of the OR gate 41, that is, logic 1, to the toggle input terminal T of the T flip-flop 31.

At this time, the characteristic of the general T flip-flop is latched at the falling edge of the input clock signal CLK, so that the output of the T flip-flop 31 while the clock signal CLK is kept high (S1). ) Is logic 0 (Figure 4 (d)).

Accordingly, logic 0 is latched on the T flip flop 31 and counterweight logic 0 is latched on the T flip flops 32, 33, and 34, respectively, resulting in the output of the feedback shift register CLK, S1, S2, S3 being logic 1000. (Fig. 4 (b), (d), (e), (f)).

As described above, when the first clock signal CLK in the high state is applied and then converted to the low state, the output of the AND gate 42 is inverted to logic 0, and the output of the AND gate 42 is inverted from logic 1 to logic 0. The output S1 of the T flip-flop 31 is also inverted to output logic 1 at the falling edge, but the output of the T flip-flops 32, 33, and 34 maintains the previous logic 0, resulting in a feedback shift register. The outputs of CLK, S1, S2, and S3 become logic 0100 (Figs. 4 (b), (d), (e), and (f)).

In this case, the OR gate 41 outputs the non-inverted output S4 and the inverted output S5 of the T flip-flop 34 by outputting a logic sum, so that the output of the OR gate 41 is always logic 1, and the AND gate ( Logic 1 is always applied to the other input terminal of 42 so that the output of the AND gate 42 coincides with the clock signal CLK (FIGS. 4C and 4B).

On the other hand, when the second clock signal CLK in the high state is applied, the T flip flop of the AND gate 42 is inverted to logic 1, but the T flip flop 31 continues to maintain logic 1 to the previous state and the T flip flop 32 33 maintains the previous logic 0, and the outputs of the feedback shift registers CLK, S1, S2, and S3 become logic 1100 (FIG. 4 (b), (d), (e), and (f)). ).

In addition, when the second clock signal CLK is inverted to the low state, the output of the AND gate 42 becomes logic 0, and the output S1 of the T flip flop 31 is inverted to logic 0, and the T flip flop 32 Output S2 is inverted at the falling edge portion of output T1 of T flip-flop 31 that is inverted to logic 0 in logic 1 to become logic 0, but the output of T flip flop 33 returns to logic 0 that was in the previous state. The outputs of the feedback shift registers CLK, S1, S2, and S3 become logic 0010 (Figs. 4 (b), (d), (e), and (f)).

When the clock signal CLK is sequentially input, the clock signal CLK is inverted at the falling edge of the clock signal CLK of the output S1 of the T flip flop 31, and the output S2 of the T flip flop 32 is T flipped. Inverted at the polling edge of the output of the output S1 of the flop 31, output S3 of the T flip flop 33 is inverted at the polling edge of the output S2 of the output S2 of the T flip flop 32. do.

As a result, the output S1 of the T flip flop 31 is a signal obtained by dividing the clock signal CLK by two, and the output S2 of the T flip flop 32 divides the output of the T flip flop 31 by two. The signal S1 of the T flip-flop 33 is a signal obtained by dividing the output of the T flip-flop S2 by two.

Therefore, the four-stage feedback shift register according to the embodiment of the present invention sequentially outputs 0000,1000,0100,1100,0010,1010,0110,1110,0001,1001,0101,1101,0011,1011,0111,1111 during 8 clocks. 16 states are created (Fig. 4 (b), (d), (e), (f)).

As described above, the present invention has the effect of generating two states in one clock, thereby facilitating high-speed data processing, and forming a feedback shift register by a T flip-flop to reduce the area.

Claims (2)

A plurality of T flip flops are connected in series so that a toggle input terminal T of each of the T flip flops is connected to a non-inverting output terminal Q of a T flip flop T located immediately in front, and a ratio of each T flip flop A T flip flop with an inverted output and a clock signal provided as a status signal; A NOR gate for negating and inverting the inverted output and the non-inverted output of the T flip flop connected to the last end of the T flip flop group; And the output of the clock signal and the output of the NOR gate are ANDed to provide an AND gate to a toggle input terminal of a T flip flop positioned at the first end of the T flip flop group. 2. The feedback shift register according to claim 1, wherein a reset signal (RST) is simultaneously applied to the reset terminal of each T flip-flop.