KR100234048B1 - Dividing circuit - Google Patents

Abstract

The present invention relates to a divider circuit suitable for extracting an arbitrary clock from a clock.

The conventional divider circuit has a problem in that many flip-flops and logic elements are required.

In order to solve this problem, the present invention includes a clock unit for generating a clock required for division; A division unit for dividing N into a clock generated by the clock unit; A selection unit for selecting N divisions; A division selector which selects N divided clocks of the division according to the signal selected by the selection unit; The clock selector selects the N divided clocks in the divider according to the select signal output from the selector.

Description

Frequency divider

The present invention relates to a frequency divider circuit, and more particularly to a frequency divider circuit suitable for extracting any clock from the clock.

As shown in FIG. 1, a conventional frequency division circuit includes a clock unit 1 for generating a clock required for division and a division unit 2 for generating n arbitrary clocks with the clock generated by the clock unit 1. ), A selector 3 that selects an arbitrary number of clocks, and a clock controller that generates a clock control signal by combining a clock selected by the selector 3 and a clock output from the frequency divider 2 ( It is composed of 4).

Referring to the accompanying drawings, the operation of the conventional frequency division circuit configured as described above is as follows.

First, there are times when you need to create a clock based on a clock.

In order to do so, it is necessary to anticipate the desired clocks in advance and divide the clocks to select the desired clocks.

That is, the clock unit 1 generates an arbitrary clock for division and inputs it to the division unit 2.

Then, the divider 2 outputs a clock divided by 2 to n with an arbitrary clock inputted from the clock unit 1.

On the other hand, the clock controller 4 outputs an arbitrary clock by combining the clock output from the frequency divider 2 and the clock selected by the selector 3.

However, this conventional divider circuit has a problem in that many flip-flops and logic elements are required.

It is therefore an object of the present invention to provide a divider circuit suitable for extracting an arbitrary clock from a clock.

Technical means for achieving this object, the clock unit for generating a clock required for dispensing; A division unit for dividing N into a clock generated by the clock unit; A selection unit for selecting N divisions; A division selector which selects N divided clocks of the division according to the signal selected by the selection unit; The clock selector selects a clock divided by N based on the selection signal output from the selector.

1 is a block diagram of a conventional frequency divider circuit.

2 is a block diagram of a frequency divider circuit according to the present invention.

<Explanation of symbols for main parts of drawing>

101: clock portion 102: divider

103: selection unit 104: dispensing selection unit

105: clock selector

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a frequency division circuit according to an embodiment of the present invention. As shown in FIG. 2, a clock unit 101 for generating a clock required for division and a clock N generated by the clock unit 101 are divided. A division unit 102, a selection unit 103 for selecting an N division, and a division selection unit 104 for selecting an N divided clock of the division unit 102 according to a signal selected by the selection unit 103. And a clock selector 105 for selecting a clock N divided by the divider 102 in accordance with the select signal output from the selector 103.

Referring to the accompanying drawings, the operation and effect of the present invention configured as described above are as follows.

First, the clock generated by the clock unit 101 is input to the division unit 102.

As an example, when the eight division is described, the signals 1S to 3S output from the selection unit 103 to the first to N exclusive oar gates 104a to 104c in the division selection unit 104 are set to "low". The output signals 4S to (N-1) S are selected as "high" and input.

Then, the first to N exclusive orifices 104a to 104c in the dispensing selector 104 output "high" when the input data 2D, 3D, and 4D are all "high".

As a result, the signal output from the frequency division selector 104 is input to the first to third end gates 4a to 4c in the frequency division 102 to take the form of 8 divisions.

Therefore, when the first to N-th gates 4d to 4n in the divider 102 are "low" input, the output terminal of the fourth to Nth flip-flops 5d to 5n, that is, the outputs of 5D to ND is 8 divisions. It continues to be output as "low" so that only the first to third flip-flops 5a to 5c operate.

Accordingly, the outputs 2D to ND of the divider 102 are input to the clock selector 105 to output only 4D by the output selected by the selector 103.

In other words, the 8-division clock of the clock generated by the clock unit 101 is generated in 4D.

As described above, the present invention has an effect of effectively dividing the flip-flop and the logic element in dividing.

Claims (2)

A clock unit 101 for generating a clock required for division; A division unit 102 for dividing N into a clock generated by the clock unit 101; A selection unit 103 for selecting N divisions; A plurality of exclusive oracle 104a to 104n for exclusively ORing the input data and the signal output from the selector 103, and ORing the signals output from each of the exclusive oragates A division selector (104) configured of an AND gate (104y) output to the division section (102) to select N-divided clocks of the division section (102); And a clock selector (105) for selecting a clock divided by the divider (102) according to the selection signal output from the selector (103). The frequency divider 102 includes a first inverter 3a for phase inverting the input data 2D, and a second inverter for phase inverting the signal output from the frequency division selector 104. 3b), a first end gate 4a for performing an AND operation on the signals output from the first and second inverters 3a and 3b, respectively, and a signal output from the first endgate 4a. The first flip-flop 5a which is output in synchronization with the clock output from the clock unit 101, and the first exclusively outputting by exclusively ANDing the input data 2D and the data 3D input to the other side. A signal outputted from the broogate 2a and the first exclusive oar gate 2a from the frequency division selector 104 by a phase inverted signal through a third inverter 3c; The second AND gate 4b to be ANDed and output, and the signal output from the second AND gate 4b is clocked. A second flip-flop 5b outputted in synchronization with the clock output from 101, a first AND gate 1a outputted by logically multiplying the input data 2D and the data 3D input to the other side; A second exclusive oracle 2b for exclusively ORing the signal output from the first end gate 1a and the data 4D input to the other side, and the second exclusive ogate ( A third end gate 4c for performing an AND operation on the signal output from 2b) and the signal output from the frequency division selector 104 phase-inverted through the fourth inverter 3d, and the third end gate 4c. A third flip-flop 5c for synchronizing the signal output from the clock unit 101 with the clock output from the clock unit 101, and a second for logically multiplying the input data 2D to (N-2) D. The AND gate 1b, the signal output from the second AND gate 1b, and the signal ((N-1) D) input to the other side are doubled. Nth exclusive oar gate 2N outputting the logical OR sum and the signal output from the Nth exclusive oar gate 2N and the frequency division selector 104 inverted in phase from the Nth inverter 3n N-th gate 4n for ANDing and outputting the signal output from the N-th flip, and the N-th flip for synchronizing the signal output from the N-th AND gate 4n with the clock output from the clock unit 101. A divider circuit comprising a flop 5n.