JPH0815392A - Test mode setting circuit - Google Patents

Abstract

PURPOSE:To obtain a test mode setting circuit in which a test mode can be set at one outer terminal by employing normal operation clock and reset signal commonly in a test mode control signal generation circuit provided in an LSI. CONSTITUTION:JKFFs 11-14 generate test mode setting codes and a test mode decode section 15 decodes a count holding the test mode setting codes to generate test mode control signals T1-T16. A clock signal outer input terminal 16 is connected with the CK terminal of the FF 11 and the CK terminal of the FF 12-14 is connected with the Q terminal of a prestage FF. Reset outer input terminal 17 and main control signal outer input terminal 18 are connected, respectively, with the reset terminals J, K of the FFs 11-14. These signal inputs are employed for controlling the test mode setting circuit to generate the signals T1-T16. In other words, the operation clock and reset signal are shared by the FFs 11-14 and the normal operation terminals 16, 17 and a test mode setting code is generated by a control signal delivered from one dedicated terminal 18.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an LSI (large scale).
In executing the integrated circuit test, L
The present invention relates to a test mode setting circuit of an LSI in which a test mode setting circuit is provided inside the SI and a test mode can be switched from an external terminal.

[0002]

2. Description of the Related Art In recent LSI development, electronic devices, which are conventionally composed of a plurality of LSIs, are gradually integrated into one due to a demand to reduce the number of parts, and the LSIs tend to have multiple functions. When testing such a multi-functional LSI from an external terminal, it is necessary to appropriately allocate an external terminal to each internal function block in addition to the terminal during normal operation. Had set.

[0003]

However, as the number of test modes increases, the number of external terminals required for mode setting also increases, which is disadvantageous in that limited external terminals can be effectively used. For example, when the test mode is up to 8 types, the number of control external terminals is 3 terminals, and when the test mode is up to 16 types, the control external terminal number is 4 terminals.

FIG. 5 shows a conventional circuit configuration for up to 16 test modes. Reference numerals 31 to 34 are test mode control external terminals, and the input signals C _{1 to} C ₄ generate 16 test mode control signals T _{1 to} T _{16 in} the test mode decoding section 35.

Further, as shown in FIG.
Serial control signal C from the external terminal 46 for control₀give
The shift registers 41 to 44 provided inside the LSI.
With the method of switching the test mode by
Clock terminal 47 for data shift
Give a ck signal, and match it with C₀Control each shift
The count value from the register 41 to 44 in the test mode
Test mode control signal T₁~
T₁₆To occur. In the example of the waveform diagram in Figure 7,
Stop the clock at C₀Control
By doing, _A, T_B, T_C, T_DTo L,
The case where H, L, and H are output is shown.

Another conventional test mode setting circuit is shown in FIG. The circuit configuration has 4-bit counting units 51, 52, 5
3 is connected in an n-stage serial manner. Then, the counting units 51 to 53 are operated by the control signal C ₀ from the external input terminal 55 and the RESET signal from the reset terminal 56.
And the count value is decoded by the test decoding unit 54 to generate test mode control signals T _{1 to} T ₁₆ . In this method, the count value is increased each time a clock pulse is given by the external control signal C ₀ to set a desired test mode. For example, when the number of stages of the counting unit is two, the input signal to the decoding unit 54 is T _A , T _B , T _C , T
_{When D} is set to L, L, L, and H, respectively, it is necessary to apply the clock pulse 128 times. In the test mode in which T _D is controlled by a decode value of H, the number of clock pulse inputs is limited to 128 to 256, for example. In other words, change the test mode one after another according to the number of clock pulses given,
It is possible to perform various tests with one test pattern. However, this means that there is a restriction on the period of holding the test mode, and the degree of freedom of the test is reduced. Also, there is a limit to the capacity of the test pattern that can be provided by the current LSI tester, and the LS
In order to perform all the tests of I, it is necessary to divide the test pattern into some. With one test pattern,
Even in the case of this test method in which a plurality of internal functional blocks are changed one after another and each block is tested little by little, it is necessary to execute a plurality of test patterns.

The present invention solves such a conventional problem, and suppresses the increase in the number of external terminals required for the test mode switching due to the increase in the number of test modes, and makes effective use of limited external terminals. It is an object of the present invention to provide a test mode setting circuit capable of performing the above.

Another object of the present invention is to provide a test mode setting circuit that does not require a separate shift register clock terminal, as compared with the conventional method of serially supplying test mode setting data.

The present invention also provides a test mode setting circuit capable of simplifying the test mode setting circuit and facilitating the test mode setting method, as compared with the test mode setting method in which n stages of counting units are provided. The purpose is to

[0010]

In order to achieve the above-mentioned object, the present invention uses a circuit which directly supplies a signal from an external terminal in order to switch the test mode of the LSI.
A circuit for generating a test mode control signal is provided inside the SI, and the operation clock and the reset signal of the control circuit are shared with the LSI normal operation clock and the reset signal, respectively, so that the test mode can be set from a single external terminal. It can be performed by the control signal of.

[0011]

Therefore, according to the present invention, by providing the test mode control signal generating circuit inside the LSI and controlling it, the number of test modes increases due to the LSI becoming more multifunctional and the outside of the LSI. The number of dedicated terminals assigned to the terminals for setting the test mode can be suppressed to only one terminal, and the increase in the number of external terminals can be suppressed. As a result, the margin of LSI external terminal allocation increases, the degree of freedom in testing increases, which contributes to ease of test design and also contributes to reduction in external dimensions.

Further, according to the present invention, the test mode control external terminal for controlling the generation of the test mode control signal reduces the number of shift register clock input terminals as compared with the conventional serial control signal supply method. In addition, in comparison with the conventional control method using the counting clock pulse, the circuit configuration of the counting unit is simplified and the degree of freedom for holding the count value, that is, the test mode is increased, which contributes to the simplification of the test. You can

[0013]

【Example】

(Embodiment 1) FIG. 1 shows the configuration of a test mode setting circuit in a first embodiment of the present invention. 11, 12, 13, 1
Reference numeral 4 is a JK flip-flop which is an asynchronous counting section for generating a test mode setting code, and 15 is a decoding of the count value held by each JK flip-flop 11-14 to generate test mode control signals T ₁ -T ₁₆ . It is a test mode decoding unit that does. Reference numerals 16 and 17 denote a clock signal external input terminal for inputting an LSI machine clock and a reset signal external input terminal for inputting an LSI reset signal, respectively, which are shared with existing terminals for normal LSI operation. Reference numeral 18 is a main control signal external input terminal for inputting a main control signal C ₀ for controlling the test mode. The clock signal external input terminal 16 is connected to the ck terminal of the first-stage JK flip-flop 11 and the ck terminals of the second-stage and subsequent flip-flops 12 to 14 are connected to the Q terminals of the previous-stage flip-flops, respectively. There is. The reset signal external input terminal 17 is connected to each flip-flop 11
To RESET terminals, and the main control signal external input terminal 18 is connected to the J and K terminals of the flip-flops 11 to 14, respectively. These signals input to control the test mode setting circuit, for generating a test mode control signal T ₁ through T _16.

Next, the operation of this embodiment will be described with reference to the waveform diagrams of FIGS. First, after resetting the JK flip-flops 11 to 14 is released, when C _{0 is set} to the H level, the JK flip-flops 11 to 14 start the counting operation as shown in FIG. The values counted by the JK flip-flops 11 to 14 can be stopped by setting C ₀ to the L level, and by controlling C ₀ at a predetermined timing, an arbitrary count value can be tested. The input terminals T _A and T of the mode decoding unit 15
It can be output to _B , T _C and T _D. This count value is held in the JK flip-flop unless the reset is applied or C _{0 is set} to the H level, and the test mode can be fixed. Conversely, the test mode can be freely changed by setting C ₀ to the H level. In FIG. 2, C ₀ is set to the L level in the counting phase (13), and T _A , T _B , T _C , and T _D are set to H and H, respectively.
The case where L, H, and L are output is shown.

The test mode is set by this T _A ,
This is performed by decoding the values of T _B , T _C and T _D by the test mode decoding unit 15 and generating test mode control signals T _{1 to} T ₁₆ . C in the counting phase (13) of FIG.
_{When 0 is set} to the L level, only T ₆ of the output of the test mode decoding unit 15 becomes the H level, and this signal is used as the test mode control signal.

Here, the control signal pattern including C ₀ can be easily given as a test pattern for an LSI tester or the like.

The following (Table 1) shows a list of operations of the test mode decoding unit 15.

[Table 1]

(Embodiment 2) Next, a test mode setting circuit according to a second embodiment of the present invention will be described with reference to FIG. The present embodiment differs from the first embodiment shown in FIG. 1 in that a ripple carry synchronization type counting unit is used instead of the asynchronous counting unit. That is, the clock signal external input terminal 16 and the reset signal external input terminal 17 are respectively connected to c of the flip-flops 11 to 14.
The main control signal external input terminal 18 is connected to the k terminal and the RESET terminal, and the main control signal external input terminal 18 is connected to the J of the first-stage flip-flop 11.
And flip-flop 1 of the second stage connected to the K terminal
The J and K terminals of 2 are connected to the flip-flop 11 of the first stage.
Connected to the Q terminal of the third stage flip-flop 13, and the J and K terminals of the third-stage flip-flop 13 output the carry propagation AND gate 21 to which the Q outputs of the first-stage and second-stage flip-flops 11 and 12 are input. And the J and K terminals of the fourth-stage flip-flop 14 are connected to the output of the AND gate 21 and the output of the carry-propagation AND gate 22 to which the Q output of the third-stage flip-flop 13 is input. Has been done. Each flip-flop 11 to 14 is
The counting operation is performed in synchronism with k.
Since the same operation is performed as described above, the description of the operation will be omitted.

(Embodiment 3) Next, a test mode setting circuit according to a third embodiment of the present invention will be described with reference to FIG. The present embodiment differs from the first embodiment shown in FIG. 1 in that a parallel carry-synchronous counting unit is used instead of the asynchronous counting unit. That is, the clock signal external input terminal 16 and the reset signal external input terminal 17 are respectively connected to the ck of the flip-flops 11 to 14.
And a RESET terminal, the main control signal external input terminal 18 is connected to the J and K terminals of the first-stage flip-flop 11, and the second-stage flip-flop 12 is connected.
The J and K terminals of are connected to the Q terminal of the first-stage flip-flop 11 and the J-terminal of the third-stage flip-flop 13.
And K terminals are connected to the output of a carry propagation AND gate 21 which receives the Q outputs of the first and second stage flip-flops 11 and 12, and the J and K terminals of the fourth stage flip-flop 14. Is connected to the output of a carry propagation AND gate 23 which receives the Q outputs of the first-stage, second-stage and third-stage flip-flops 11, 12 and 13. Each flip-flop 11-14 is clo
The counting operation is performed in synchronism with ck, and its operation waveform diagram is similar to that of FIG.

[0020]

As is apparent from the above embodiment, the present invention is provided by being provided inside the LSI and sharing the operation clock and the reset signal with the external operation external clock input terminal and the reset terminal of the LSI, respectively. Since it is provided with a plurality of counting units that generate a test mode setting code by a control signal from an external input terminal and a decoding unit that decodes the count value held in each counting unit and generates a test mode control signal. In addition, the number of external control terminals for test mode setting can be reduced to one, regardless of the number of test modes, which contributes to effective use of LSI external terminals during testing, increasing the functionality of LSIs and increasing the complexity of test modes. It is possible to flexibly cope with the increase in test modes due to the increase in the number of test modes. Further, this effect can suppress an increase in the LSI external area, further eliminate the need for a shift register-dedicated clock terminal as in the prior art, and can realize a reduction in the circuit of the counting unit, which holds or counts the count value. Mode setting is facilitated, and simplification of the circuit configuration and facilitation of test pattern creation can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing a test mode setting circuit according to a first embodiment of the present invention.

FIG. 2 is an operation waveform diagram in the embodiment of the invention.

FIG. 3 is a block diagram showing a test mode setting circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a test mode setting circuit according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional test mode setting circuit.

FIG. 6 is a block diagram showing another example of a conventional test mode setting circuit.

FIG. 7 is a conventional operation waveform diagram.

FIG. 8 is a block diagram showing still another example of a conventional test mode setting circuit.

[Explanation of symbols]

 11 JK Flip-Flop 12 JK Flip-Flop 13 JK Flip-Flop 14 JK Flip-Flop 15 Test Mode Decode Unit 16 Clock Signal External Input Terminal 17 Reset Signal External Input Terminal 18 Main Control Signal External Input Terminal 21 Carry Propagation AND Gate 22 Carry Propagation Logic Product gate 23 Carry propagation AND gate

Claims (4)

[Claims] 1. A test mode setting code which is provided inside an LSI and shares an operating clock and a reset signal with an external clock input terminal for normal operation and a reset terminal of the LSI, respectively, and by a control signal from a dedicated external input terminal. A test mode setting circuit comprising: a plurality of counting units for generating a test mode control signal; and a decoding unit for decoding a count value held by each of the counting units to generate a test mode control signal. 2. The test mode setting circuit according to claim 1, wherein the counting unit for generating the setting code is asynchronous. 3. The test mode setting circuit according to claim 1, wherein a ripple carry synchronization method is adopted in the counting section for generating the setting code. 4. The test mode setting circuit according to claim 1, wherein a parallel carry synchronization method is adopted in the counting section for generating the setting code.