JPH04181186A - Test mode setting circuit for integrated circuit - Google Patents

Abstract

PURPOSE:To simply set a large number of test modes only by providing a reduced number of always constant test exclusive input terminals by using the outputs of logical gates as a plurality of test mode signals. CONSTITUTION:The respective outputs T0 - T3 of a plurality of shift registers 10a, 10b... wherein the first test exclusive input terminal 13 is set to clock input and the second test exclusive input terminal 14 is set to serial data input are supplied to a decoder 11. A plurality of the decoding outputs M0 - M15 obtained from the decoder 11 are supplied to AND gates 12a, 12b... but, only at the time of a test mode, a clock TEST making the decoding outputs effective is further supplied to said gates. Therefore, only at the time of the test mode, any logical outputs according to serial data are used as test mode setting signals TEST0 - TEST15. By this constitution, when (N) shift registers are used, only by providing two test exclusive input terminals, test modes of 2N kinds can be set.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention provides a test mode setting circuit for an accumulation circuit having a test-only input terminal, in particular, by providing a large number of test modes due to the large scale of the circuit, etc., and reducing the test time. The present invention relates to a test mode setting circuit for an integrated circuit that requires shortening of the time.

BACKGROUND ART Conventionally, various functional tests performed to guarantee the quality of integrated circuits (IC circuits) are performed using a test mode setting circuit built into the IC circuit.

This test mode setting circuit can either set the test mode using only the data input terminal for normal data signals, or provide multiple test-dedicated terminals in the IC circuit.
The test mode is set by a decoder provided inside the IC circuit.

[Problems to be Solved by the Invention] In such a conventional test mode setting circuit, the former technique (Japanese Patent Laid-Open No. 1-27
4081), only one test mode can be executed using three data input terminals. Therefore, there is no need for a terminal dedicated to testing, but it is not possible to set a large number of test modes.

On the other hand, in the latter case, the number of test-dedicated input terminals is N
Since up to (2N-1) test modes can be set, this circuit is suitable as a test mode setting circuit for large-scale IC circuits, although it requires a dedicated test input terminal.

However, even in this conventional example, only up to (2N-1) test modes can be set, and if it is necessary to set even more test modes, the number of test-dedicated input terminals must be increased. If this happens, the scale of the IC circuit will become large and it will not be very effective.

The present invention solves these conventional drawbacks, and provides a large-scale IC circuit that can easily set a large number of test modes by simply providing a constant, small number of test-dedicated input terminals. This provides a test mode setting circuit suitable for.

[Means for Solving the Problems] In order to solve the above-mentioned problems, in the first invention, in a test mode setting circuit for an integrated circuit having a test-only input terminal, the first test-only input terminal is used as a clock; It has a plurality of shift registers whose second test-dedicated input terminal is a serial data input, and a logic gate to which each output of these shift registers and the above-mentioned clock are supplied, and the logic gate output sets a plurality of test modes. It is characterized in that it is used as a signal.

In the second invention, there are provided a plurality of registers whose data input is a normal data input terminal not exclusively for testing, and whose clock is a first input terminal exclusively for testing, and the outputs of these registers and the clock are supplied. The present invention is characterized in that the output of the logic gate is used as a plurality of test mode setting signals.

[Function] Figure 1 shows an example in which a large number of test modes can be set using a test-dedicated input terminal, in which the first test-dedicated input terminal 13 is used as a clock, and the second test-dedicated input terminal A plurality of shift registers 10a, 10b each having 14 as a serial data input.

The respective outputs TO to T3 are supplied to the decoder 11.

A plurality of decode outputs MO to M15 obtained from this are supplied to AND gates 12a, 12b, which are further supplied with a lock TEST so that the decode outputs are valid only in the test mode.

Therefore, only in the test mode, which logic gate output according to the serial data is used as the test mode setting signals TESTO to TEST1'5.

According to this, if N shift registers are used, 2
By simply providing two test-dedicated input terminals, 2 N test modes can be implemented.

The second invention uses one test-dedicated terminal 13 as shown in FIG. 5, and the others are normal data input terminals 34a.
~B4d is also used as a test mode setting terminal, and in this example, the decoder 11 is also used.

Sixteen types of decoded outputs are obtained by each output of a plurality of registers 30a to 30d whose data input terminals are used as data inputs and whose clocks are signal TEST.

This decoded output is finally used as a test mode setting signal.

[Embodiment] Next, an example of a test mode setting circuit for an accumulation circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the invention.

This invention is an example in which a large number of test modes can be set using a small number of test-dedicated input terminals. In FIG. 0, two test-dedicated input terminals 13 and 14 are used.

The first test-dedicated input terminal 13 is input to the clock terminals of a plurality of shift registers that refine the shift registers, in this example three D-type flip-flops 10a, ]Ob, and 10C.

On the other hand, the second input terminal 14 exclusively for the chest is connected to the data input terminal of the first-stage flip-flop 10a that refines the shift register.

Then, three flip-flops 10a are connected in cascade.
, 10b, 10c each output and input terminal 14
The input data TO are respectively supplied to a decoder 11, where two flip-flops 10a, 10b,
10c each output T1. T2. T3 and input data TO are decoded to produce decoded outputs MO, M1 .
・1M15 is output.

AND gates 12a, 12b, -12p provide decode outputs MO, Ml, only during testing.

Sixteen AND gates 12a are logic gates provided to enable M15, and these decode outputs and clock TEST correspond to each other.

12b and 12p. And these AND gates 12a, 1.2b, , 1
TESTO2TESTl, which is the output of 2p.

TEST15 is supplied as a test mode signal to a logic circuit under test (not shown) provided inside the IC circuit.

FIG. 2 shows an operation timing chart of FIG. 1.

Clock (pulse) T is input to the first test-dedicated input terminal 13.
While adding EST, input data To is applied from the second test-dedicated input terminal 14. According to this input data To, flip-flops 10a, 10b, 10c
determine the state of

Input data TO supplied to the input terminal 14 is sequentially shifted by flip-flops 10a, 10b, 10c, and these are outputted as outputs To, Tl, T2,
T3 are obtained, and these are further decoded by the decoder 11. Then, the decoded outputs MO, M1 .
...Since Ml5 is ultimately used as the test mode setting signal TESTn (either TESTO-TESTl5) shown in FIG. 2, the data content of the input data TO should be adjusted according to the test mode signal you want to use. is determined.

The third section shows the truth value of this test mode setting circuit.

For example, if it is desired to use the test mode signal TESTO, input data (input data T○ to T3 for test 0) such that only the decode output MO becomes high level may be provided to the input terminal 14.

Note that when the clock pulse TEST is kept at a low level, as is clear from FIG. 2, 16 types of test mode signals TESTO, TEST1.
・ , TESTl5 are all low level,
It is in normal operating mode.

IC only when clock pulse TEST is set to high level
[1ill path test mode is entered, and 16 AND gates 12a to 12p are activated.

Figure 1 shows a test mode setting circuit that can set 16 test modes using three flip-flops. (−
By simply increasing N), the number of decoded outputs and therefore the number of test modes can be increased to the power of 2 (N+1).

Even in this case, there is no need to add a new test-dedicated input terminal.

FIG. 4 is a modification of FIG. 1, and can be applied to an IC circuit that does not require a large number of test modes.

The figure shows a case where the circuit is applied to a test mode setting circuit that can realize four test modes, and the difference from FIG. 1 is that the decoder 11 is omitted.

Therefore, there are two test-only input terminals (13, 14).
and input data TO and flip-flop 1
The outputs TI, T2 . T3 is a direct AND gate 52a,
52b, 52c, and 52ci, and is configured to be ANDed with the clock pulse TEST.

According to this configuration, since the four outputs To to T3 are used as they are as the test mode setting signals TESTO to TEST3, there are four types of test modes.

Therefore, although the number of test modes that can be set is small compared to the embodiment shown in FIG.
Since the contents of 0'c can be output as is, a plurality of test mode setting outputs can be set to high level at the same time.

Of course, even in this configuration, if the number of stages of flip-flops to be connected in cascade is increased, the number of test modes will increase by the increase (J is easily understood.

Incidentally, the above-mentioned embodiments are all applied to 10 circuits provided with a plurality of dedicated terminals for test mode.

The embodiment shown below uses one test-dedicated terminal, but by using the data input terminal as a test mode terminal, multiple test modes can be performed without increasing the number of test terminals. An example of a test mode setting circuit that can be implemented is shown below.

FIG. 5 shows a case where the present invention is applied to a test mode setting circuit that realizes 16 test modes as in the case of FIG. 1.

Therefore, in addition to the test-dedicated input terminal 13, the four data input terminals 34a, 34b, 34c, and 34d are also used as test input terminals as terminals used in the test mode. Data input terminals 34a, 3
4b, 34c, and 34d are connected to respective data terminals of D-type flip-flops 30a, 30b, 3Qc, and 30d, and provide parallel data DATAO corresponding to the test mode.

DATAI, DATA2. DATA3 is supplied.

These flip-flops 30a, 30b, 30
A clock pulse TEST is supplied from the test-dedicated input terminal 13 to each of the clock terminals C and 30d, and when this is at a high level, the data DATA is output as shown in FIG.
O~DATA3 is captured, and the captured level is output as is.

~T3.

The outputs To, Tl, T2°T3 obtained from each are supplied to the decoder 11, and a total of 16 decoded outputs MO, M1 .・M2S can be obtained.

The decode outputs MO to M15 are connected to the AND gates 12a, 12b, . . . , 12 along with the clock pulse TEST.
p. And flip-flops 30a-3
When the clock pulse TSET is inverted to high level again after the data loading to 0d is completed, this is determined to be a test mode and one of the AND gates 12a to 12p is opened. As a result, the input data DATAO~DAT
Test mode setting signal TEST specified by A3
n < any one of T E S T O to T E S T 15) is output, and the test mode is executed.

When the clock pulse TE ST is at low level, it is a normal operation mode, but the test mode setting signal TES is
Tn (any one from TESTO to TESTI 5)
is not output.

Even if only one terminal is used for testing in this way, a plurality of test modes can be realized by using the data input terminal also as a testing terminal.

In other words, when the number of data input terminals used is N, 2 to the Nth power of test modes can be realized.

Note that when it is not possible to use multiple data input terminals for test settings, use the flip floor controllers 130a to 3.
Only one of the terminals 0d may be used, and the flip-flops connected to that terminal may be configured in cascade (shift register configuration) as in the first embodiment.

In this way, a test mode similar to that described above can be realized by simply using one data input terminal and a test-dedicated terminal.

FIG. 7 shows still another example of FIG. 5, which is a modification corresponding to FIG. 4. In other words, even in the case of FIG. 5, the decoder 11 may be omitted and refined as in the seventh section.

However, in this case, only the number of data input terminals used is the number of test modes.

[Effects of the Invention] As explained above, the test mode setting circuit of the present invention can always easily set the test mode using one or two test-dedicated input terminals, regardless of the number of test modes, and can always set the test mode easily in the normal operation mode. This has the effect that switching to can be easily performed.

Therefore, the present invention is particularly suitable for large-scale I/O circuits that have a large circuit scale and require setting a large number of test modes.
It is extremely suitable for application to C circuits.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a test mode setting circuit according to the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, and FIG. 3 is a diagram showing a truth table of the operation. , FIG. 4 is a circuit diagram showing a modification of FIG. 1, FIG. 5 is a circuit diagram showing a second embodiment of the test mode setting circuit according to the present invention, and FIG. 6 is a timing chart showing its operation.
FIG. 7 is a circuit diagram showing a modification of FIG. 5. 10a, 10b, 10c, 30a, 30b
, 30c, 30d - Flip-flop circuit 11... Decoder 12a, 12b, 12p... AND gate 13 - First test-only input terminal 14 - Second test-only input terminal 34a, 34b, 34c, 34d... Data signal input terminals TESTO, TESTI, TESTI5/Test mode setting signal

Claims (4)

[Claims] (1) In a test mode setting circuit for an integrated circuit having a test-dedicated input terminal, a plurality of shift registers each having a first test-dedicated input terminal as a clock and a second test-dedicated input terminal as serial data input; A test mode setting circuit for an integrated circuit, comprising a logic gate to which each output of a register and the clock are supplied, and the logic gate output is used as a plurality of test mode setting signals. (2) A decoder for decoding the outputs of the plurality of shift registers is provided between the plurality of shift registers and the logic gate, and the output of this decoder and a clock are supplied to the logic gate. 2. A test mode setting circuit for an integrated circuit according to claim 1. (3) It has a plurality of registers whose data inputs are normal data input terminals that are not dedicated to testing, and whose clocks are the first test-only input terminals, and logic gates to which the outputs of these registers and the above-mentioned clocks are supplied. A test mode setting circuit for an integrated circuit, wherein the logic gate output is used as a plurality of test mode setting signals. (4) A decoder for decoding the outputs of the plurality of registers is provided between the plurality of registers and the logic gate, and the output of this decoder and a clock are supplied to the logic gate. 4. A test mode setting circuit for an integrated circuit according to claim 3.