JPH02181950A - System of setting operation mode of semiconductor integrated circuit - Google Patents

System of setting operation mode of semiconductor integrated circuit

Info

Publication number
JPH02181950A
JPH02181950A JP1002412A JP241289A JPH02181950A JP H02181950 A JPH02181950 A JP H02181950A JP 1002412 A JP1002412 A JP 1002412A JP 241289 A JP241289 A JP 241289A JP H02181950 A JPH02181950 A JP H02181950A
Authority
JP
Japan
Prior art keywords
terminal
semiconductor integrated
clock
input
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1002412A
Other languages
Japanese (ja)
Inventor
Mikio Ogisu
荻須 幹雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1002412A priority Critical patent/JPH02181950A/en
Publication of JPH02181950A publication Critical patent/JPH02181950A/en
Pending legal-status Critical Current

Links

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  • Microcomputers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To set a specific operation mode from a plurality of operation modes by providing one shift register which has been connected from one operation- mode setting terminal. CONSTITUTION:A shift register 4 which uses a mode-setting terminal 1 of a semiconductor integrated circuit as a data input is constituted in such a way that a data is shifted by a signal, of a shift clock signal line, generated at an AND circuit 6 by individual input signals to a clock input terminal 2 and to a reset input terminal 3. An input data 1' for operation-mode setting use is input from the mode-setting terminal 1 in synchronization with the signal of the shift clock signal line 7. A shift clock 7' is generated as an output signal from the AND circuit 6 by a clock 2' and a reset signal 3' which is input from the reset terminal 3. The clock 2' is a system clock which operates a semiconductor integrated circuit and is always oscillated. A data from individual flip- flops 8 constituting the shift register 4 is output from an output terminal 5; an operation mode is judged at the inside of the semiconductor integrated circuit when a reset is released.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体集積回路の動作モード設定方式%式% 従来の技術 従来、半導体集積回路は動作モードを設定する複数の端
子を備え、この端子に特定の設定信号を与えることによ
り、端子状態の組み合わせ、或いは設定信号を特殊なタ
イミングで与えることで動作モードを設定していた。こ
のため、端子に特定の設定信号を与えて動作モードを設
定する場合、端子数をNとすると設定できる動作モード
はN2であり、半導体集積回路の動作モードによっては
、多くの端子を必要としていた。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an operating mode setting method for semiconductor integrated circuits. The operating mode was set by applying a setting signal to a combination of terminal states or by applying a setting signal at a special timing. Therefore, when setting an operating mode by giving a specific setting signal to a terminal, the number of operating modes that can be set is N2, where the number of terminals is N, and depending on the operating mode of the semiconductor integrated circuit, many terminals are required. .

発明が解決しようきする課題 従来の動作モードを複数の端子で設定する方法では、多
くの端子をモード設定用に割り付ける必要があり、また
、特殊なタイミングで設定する方法ではモード設定の手
順が非常に困難であった。
Problems to be Solved by the Invention In the conventional method of setting the operating mode using multiple terminals, it is necessary to allocate many terminals for mode setting, and in the method of setting at special timing, the mode setting procedure is extremely complicated. It was difficult.

本発明は上記の従来の問題点を解決するものであり、一
本の動作モード設定端子により、複雑な設定方法なしに
、複数の動作モードを設定する方法を提供するものであ
る。
The present invention solves the above conventional problems and provides a method for setting a plurality of operation modes using a single operation mode setting terminal without a complicated setting method.

課題を解決するための手段 この目的を達成するために本発明は、一本の動作モード
設定端子と該設定端子より半導体集積回路内部に接続さ
れた一本のシフトレジスタを備え、このシフトレジスタ
の値により複数の動作モードから特定の動作モードを設
定する方式である。
Means for Solving the Problems In order to achieve this object, the present invention includes one operation mode setting terminal and one shift register connected to the inside of the semiconductor integrated circuit from the setting terminal. This is a method of setting a specific operation mode from multiple operation modes depending on the value.

作用 この構成によって、一本の動作モード設定端子によって
、特定の動作モードを設定し、複数のモード設定端子や
、特殊なタイミングを使うことなしで、半導体集積回路
の動作モードを自在に設定することができる。
Effect: With this configuration, a specific operation mode can be set using a single operation mode setting pin, and the operation mode of the semiconductor integrated circuit can be freely set without using multiple mode setting pins or special timing. Can be done.

実施例 以下本発明の一実施例について説明する。Example An embodiment of the present invention will be described below.

第1図は本発明の回路構成を示すものである。FIG. 1 shows the circuit configuration of the present invention.

半導体集積回路のモード設定端子1をデータ入力とする
シフトレジスタ4はクロック入力端子2とリセット入力
端子3への各入力信号によってアンド(AND)回路6
で発生されるシフトクロック信号線7の信号によってデ
ータをシフトする構成になっている。
A shift register 4 whose data input is a mode setting terminal 1 of a semiconductor integrated circuit is connected to an AND circuit 6 by input signals to a clock input terminal 2 and a reset input terminal 3.
Data is shifted by a signal on a shift clock signal line 7 generated by a shift clock signal line 7.

以上のように構成された半導体集積回路の動作モード設
定方式を第2図の各入力信号のタイミング図を用いて説
明する。半導体集積回路のモード設定端子1から動作モ
ード設定用入力データ1゛がシフトクロツタ信号線7の
信号と同期して入力される。このシフトクロック信号線
7の信号(シフトクロック7″)はクロック2′とリセ
ット端子3から入力されるリセット信号3′とのAND
回路6からの出力信号として発生される。クロック2゛
は半導体集積回路を動作させるシステムクロックであり
、常に発娠している。リセット信号3′はリセット時は
“1”であり、リセット解除時は“O”であるとする。
The operation mode setting method of the semiconductor integrated circuit configured as described above will be explained using the timing chart of each input signal in FIG. Operation mode setting input data 1' is inputted from the mode setting terminal 1 of the semiconductor integrated circuit in synchronization with the signal on the shift clock signal line 7. The signal on the shift clock signal line 7 (shift clock 7'') is an AND of the clock 2' and the reset signal 3' input from the reset terminal 3.
It is generated as an output signal from circuit 6. Clock 2' is a system clock that operates the semiconductor integrated circuit, and is always activated. It is assumed that the reset signal 3' is "1" at the time of reset and "O" when the reset is released.

このクロック2′とリセット信号3゛との論理1 (A
ND)でシフトクロック7゛が発生されるため、リセッ
ト信号3が“1”のとき、システムクロック7゛はクロ
ック2′と同じ信号が出力されるが、リセット信号3゛
が“O”のときはクロック7′は0”のままである。従
って動作モード設定用入力データ1゛はシステムクロッ
ク7″が発生しているとき、すなわち、リセット信号3
゛が“1”のとき、システムクロック7゛と同期して入
力され、動作モード設定用入力データ1°が全で入力さ
れた時点でリセット信号3′を“0”にしてデータをシ
フトレジスタ4内に保持する。シフトレジスタ4を構成
している各フリップフロップ8からのデータは出力端子
5から出力され、リセット解除時に半導体集積回路内部
で動作モードを判断する。
The logic 1 (A
ND), the shift clock 7' is generated, so when the reset signal 3 is "1", the system clock 7' outputs the same signal as the clock 2', but when the reset signal 3' is "O" The clock 7' remains 0''. Therefore, the input data 1'' for setting the operation mode is generated when the system clock 7'' is generated, that is, the reset signal 3
When ゛ is “1”, it is input in synchronization with the system clock 7゛, and when all the input data 1° for operation mode setting has been input, the reset signal 3′ is set to “0” and the data is transferred to the shift register 4. hold within. Data from each flip-flop 8 constituting the shift register 4 is output from the output terminal 5, and the operation mode is determined inside the semiconductor integrated circuit when reset is released.

以上のように、一本の動作モード設定端子より接続され
た一本のシフトレジスタを備えることにより、動作モー
ドを設定することができる。
As described above, by providing one shift register connected to one operation mode setting terminal, the operation mode can be set.

なお、本実施例ではシフトレジスタを4ビツトとしたが
、動作モードの数によってシフトレジスタを構成してい
るフリップフロップの数を簡単に変更できる。また、フ
リップフロップの型体を特に規定しなかったが、シフト
レジスタを構成できるものであれば制限はない。
In this embodiment, the shift register has 4 bits, but the number of flip-flops constituting the shift register can be easily changed depending on the number of operation modes. Further, although the type of the flip-flop is not particularly specified, there is no restriction as long as it can constitute a shift register.

発明の効果 以上のように本発明は、一本の動作モード設定端子より
接続された一本のシフトレジスタを備えることにより複
数の動作モードから、特定の動作モードを設定できる半
導体集積回路の動作モード設定方式を実現できるもので
ある。
Effects of the Invention As described above, the present invention provides an operating mode for a semiconductor integrated circuit that can set a specific operating mode from a plurality of operating modes by providing one shift register connected to one operating mode setting terminal. It is possible to realize a setting method.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の回路構成図、第2図は本発
明の一実施例における各信号のタイミング図である。 1・・・・・・半導体集積回路のモード設定端子、2・
・・・・・クロック入力端子、3・・・・・・リセット
入力端子、4・・・・・・シフトレジスタ、5・・・・
・・シフトレジスタを構成しているフリップフロップか
らの出力端子、6・・・・・・AND回路、7・・・・
・・シフトクロック信号線、8・・・・・・シフトレジ
スタを構成しているフリップフロップ。 代理人の氏名 弁理士 粟野重孝 ほか1名3g−
FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 2 is a timing diagram of each signal in an embodiment of the present invention. 1...Mode setting terminal of semiconductor integrated circuit, 2.
... Clock input terminal, 3 ... Reset input terminal, 4 ... Shift register, 5 ...
...Output terminal from the flip-flop configuring the shift register, 6...AND circuit, 7...
...Shift clock signal line, 8...Flip-flops forming the shift register. Name of agent: Patent attorney Shigetaka Awano and 1 other person 3g-

Claims (2)

【特許請求の範囲】[Claims] (1)一本の動作モード設定端子を備え、複数の動作モ
ードを持ち、前記端子より特定の動作モード設定信号を
入力することにより、前記複数の動作モードのうちの1
つの動作モードを決定する半導体集積回路の動作モード
設定方式。
(1) It is equipped with one operation mode setting terminal and has a plurality of operation modes, and by inputting a specific operation mode setting signal from the terminal, one of the plurality of operation modes can be selected.
An operating mode setting method for semiconductor integrated circuits that determines two operating modes.
(2)一本の動作モード設定端子に接続された一本のシ
フトレジスタを備え、このシフトレジスタの値により複
数の動作モードから特定の動作モードを設定することを
特徴とする請求項(1)記載の半導体集積回路の動作モ
ード設定方式。
(2) Claim (1) characterized by comprising one shift register connected to one operation mode setting terminal, and setting a specific operation mode from a plurality of operation modes according to the value of this shift register. Operation mode setting method of the semiconductor integrated circuit described.
JP1002412A 1989-01-09 1989-01-09 System of setting operation mode of semiconductor integrated circuit Pending JPH02181950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1002412A JPH02181950A (en) 1989-01-09 1989-01-09 System of setting operation mode of semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1002412A JPH02181950A (en) 1989-01-09 1989-01-09 System of setting operation mode of semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH02181950A true JPH02181950A (en) 1990-07-16

Family

ID=11528533

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1002412A Pending JPH02181950A (en) 1989-01-09 1989-01-09 System of setting operation mode of semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH02181950A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5449225A (en) * 1990-10-17 1995-09-12 Alfred Teves Gmbh Master cylinder with two internal valves
JP2010103422A (en) * 2008-10-27 2010-05-06 Kyocera Mita Corp Integrated circuit, circuit substrate having the same, and image forming apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120350A (en) * 1984-07-09 1986-01-29 Nippon Telegr & Teleph Corp <Ntt> Ic and method of its redundant switching
JPS62199048A (en) * 1986-02-27 1987-09-02 Nec Corp Large scale integrated circuit with testing circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6120350A (en) * 1984-07-09 1986-01-29 Nippon Telegr & Teleph Corp <Ntt> Ic and method of its redundant switching
JPS62199048A (en) * 1986-02-27 1987-09-02 Nec Corp Large scale integrated circuit with testing circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5449225A (en) * 1990-10-17 1995-09-12 Alfred Teves Gmbh Master cylinder with two internal valves
JP2010103422A (en) * 2008-10-27 2010-05-06 Kyocera Mita Corp Integrated circuit, circuit substrate having the same, and image forming apparatus

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