JPH02170070A - Test pattern generator - Google Patents

Abstract

PURPOSE:To obtain a high fault detection rate by using flip-flops the number of which is more than the input terminals of a circuit to be tested and multiplexers which select and transmit inverted and uninverted output signals of the flip-flops. CONSTITUTION:When a control signal C1 is '1', the inverted signals of data stored in the flip-flops 1A-1E are inputted to the following-stage flip-flops 1B-1E. The inverted output signals (Q) of the flip-flops 1C and 1E are inputted to an exclusive OR gate G1, whose output is inputted as a feedback signal to the flip-flop 1A. The inverted output signals (Q) of the flip-flops 1B-1E are applied as test patterns to the input terminals D4-D1 of the circuit to be tested through multiplexers 2B-2E. When 0 is supplied to the terminal D4 at certain time (t), the data at the terminal D3 becomes 1 at time (t+1) and every time a cock phiis applied, the data is shifted in order while inverted into 0 at the terminal D2 and into 1 at the terminal D1. Therefore, more combinations of patterns can be generated and the high fault detection rate is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a test pattern generator, and more particularly, to a test pattern generator that facilitates functional testing of integrated circuits and that is capable of being integrated so that the testing can be performed even on extremely complex circuits. It relates to a test pattern generator built into the circuit itself.

[Conventional technology]

One method to facilitate logic function testing of highly integrated and complex integrated circuits is to incorporate test mechanisms such as a test pattern generator and test output evaluation section into the integrated circuit to be tested. There is. By doing this,
Embedded inside the integrated circuit and controlled directly from external terminals,
This is because logic function tests can now be easily performed on parts of the circuit that have been difficult to test because they cannot be observed.

When incorporating such a test mechanism into an integrated circuit, a major issue is what kind of pattern generator to incorporate. This is because there is a need for a pattern generator that can be implemented using simple hardware due to the restriction of being built into an integrated circuit, and that can also generate highly efficient test patterns.

Conventionally, as this type of test pattern generator, a feedback type shift register is often used because of its simple hardware configuration, and in particular, a linear feedback type shift register that can generate a maximum long period sequence is often used. (For example, IEE PROCEED
INGS) Volume 1.32, Issue 3, Page 105, 198
(See Year 5).

FIG. 2 is a block diagram of a test pattern generator using a conventionally known linear feedback shift register.

Figure 2 shows each flip-flop IF~ of a linear feedback shift register IOA having a generator polynomial of X4+X+1.
Output data D4 to D in each clock cycle of 11
1 is a built-in test pattern generator that applies 1 as a test pattern to each input terminal (D4) to (Dl) of the circuit under test 20.

In this circuit, each time the clock signal φ is input, the data of the previous stage flip-flops IF to IH are taken into the flip-flops IG to II, and the data of the flip-flops I
The result of exclusive OR operation of the data of flip-flops lo and 1+ by exclusive OR gate G1 is taken into F as a feedback signal. At the same time, the data of each flip-flop IF-11 is output as output data D4-D1.

This operation continues as long as the clock signal φ is input.

In this way, the linear feedback shift register IOA generates test patterns one after another simply by inputting the clock signal φ, and if a primitive polynomial is adopted as the generating polynomial, the linear feedback shift register IOA can generate the maximum long period sequence. It becomes a register, and all patterns can be generated except that the outputs of all flip-flops IF to 11 become ``0''.

Therefore, if the circuit under test 20 is a combinational circuit, by preparing a linear feedback shift register IOA with the same number of stages as the number of input terminals (D4) to (Dl) of the test pattern, the circuit under test 20 can be completely completed. testing becomes possible.

(As is well known, a test pattern of all '0°' can be generated by adding one NOR gate.) Moreover, such a test pattern generator uses flip-flops IF~11, Since it can be constructed by reusing the input latch of the circuit under test 10A, the amount of additional hardware can be reduced.

[Problem to be solved by the invention]

However, when the circuit under test is composed of a CMO8 circuit, which is most widely used in current LSIs, a problem arises with the conventional test pattern generator described above.

It is a stack opening (STUCK) specific to CMO3 circuits.
-OPEN) The presence of the fault converts the circuit under test from a combinational circuit to a sequential circuit.

Unlike a combinational circuit, whose output value is determined only by the applied inputs, a sequential circuit's output value is determined by both the inputs and the internal state, so failure detection can be performed after setting the internals to a known state. It is necessary to apply a test pattern for That is, one 5TUCK-O
Detecting a PEN failure requires two consecutive patterns: [Initialization pattern] and [Detection pattern].
When the circuit under test is composed of eight CMO circuits, a test pattern generator that can generate many sets of two consecutive patterns is desired.

However, in the conventional test pattern generator described above, the output data D4(t) to DI at a certain time t
Output data D3(1) to Di(t) of (t) are:
Output data D4 at time (tl) one clock ago
Output data D4 among (t-1) to D1 (t-1)
(t-1) to D2 (1-1,), which has extremely strong regularity, and there are only a limited number of sets of two patterns that can occur consecutively, and high failure detection for CMO3 circuits. rate is difficult to obtain.

The purpose of the present invention is to improve the above-mentioned problems of the prior art, and
The object of the present invention is to provide a pattern generator for test 1 that can obtain a high failure detection rate even for MO3 circuits.

[Means to solve the problem]

The test pattern generator of the present invention includes a plurality of flip-flops that output an inverted signal and a non-inverted signal respectively and are sequentially arranged in a plurality of stages, and an inverted signal and a non-inverted signal of each flip-flop except the last stage of the plurality of flip-flops. a plurality of pre-stage multiplexers each receiving an inverted signal and selecting one of the inverted signal and non-inverted signal according to a control signal and outputting the selected signal to each of the flip-flops in the immediately following stage; A last-stage multiplexer inputs a non-inverted signal and selects and outputs one of the inverted signal and the non-inverted signal according to the control signal, and inputs an output signal of a predetermined multiplexer among the middle-stage and last-stage multiplexers. a feedback circuit that outputs a feedback signal to the flip-flop at the frontmost stage to form a feedback shift register together with each flip-flop and each multiplexer; and a predetermined output of the output signals of the middle and last stage multiplexers. and at least one less test pattern output terminal than the number of stages of the flip-flops, each of which transmits a signal in a corresponding manner.

[Effect]

5Tt of CMO3 circuit that changes the circuit under test to a sequential circuit
To detect a CK-OPEN failure, it is sufficient to apply an initialization pattern that sets the internal circuit to a certain state, and then apply a pattern that can activate the path.The failure is determined by how many pairs of the two patterns can occur. The detection rate is determined.

In conventional test pattern generators using feedback type shift registers, data is shifted in one direction.
As described above, if the pattern at a certain time t is determined, the pattern at time (1+1.) is almost determined.

For example, if the data of two adjacent flip-flops at a certain time t is 00'', then the time (1
+1. ), the data that can be accommodated by these flip-flops are two sets of ``OO'' and ``lO''', and the data ``01'' and ``11'' can never be taken.

In contrast, the test pattern generator of the present invention operates not only as a linear feedback shift register similar to the conventional one, but also as a linear feedback shift register that inverts and shifts the data of each flip-flop.

Therefore, if the data of two adjacent flip-flops at a certain time t is "o o", the possible data at time (t + 1.) is 'O
O"', "10', "01", and "11" all occur, and compared to the conventional technology, it is possible to generate more sets of two patterns, resulting in a higher failure rate. Detection rate is expected.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

In this embodiment, a plurality of flip-flops IA to 18 each outputting an inverted signal (Q) and a non-inverted signal (Q>) are arranged in sequence, and each of the flip-flops IA to IE except the last stage Input the inverted signal (Q> and non-inverted signal (Q) of ~ID, respectively, and control these inverted signal (page) and non-inverted signal (Q) by control signal C1.
> select one of the next stage flip-flops IB~I
E'\ Pre-stage multiplexer 2A~2 that outputs each
D and the inverted signal of the last stage flip-flop IE<Q)
and a final stage multiplexer 2L that inputs the non-inverted signal (Q) and selects and outputs one of the inverted signal (Q) and the non-inverted signal (Q) according to the control signal C1. An exclusive OR gate G1 of a feedback circuit inputs the output signals of multiplexers 2c and 2r among multiplexers 2A to 2r, takes an exclusive OR of these, and outputs the result as a feedback signal to the flip-flop IA at the front stage. These flip-flops 18-]L, multiplexers 2A-28, and exclusive OR gate G1 form a linear feedback shift register 10, and flip-flops IA-IT-.

Test pattern output terminals T4 to T that are one less than the number of stages of
, the output data D4 to D1 of a predetermined multiplexer 2B to 2° of the multiplexers 2A to 2E are connected to the input terminals (Di) to (Di) of the circuit under test 20, respectively.
Dl).

Next, the operation of this embodiment will be explained.

First, when the control signal C1 is "o", that is, each multiplexer 2A to 2'a in FIG.
In other words, when selecting and outputting the non-inverted output signal (Q) of each flip-flop 1A to 1E, these flip-flops IA to IE, multiplexers 2^ to 2r, and exclusive OR gate G form a generator polynomial of A linear feedback shift register 10 is realized, and the output signals of the flip-flops IB to IL in each stage other than the front flip-flop IA of the linear feedback shift register 10 are sent to the circuit under test via multiplexers 2B to 2E. 20 as a test pattern.

In this case, as in the conventional example, the data held in the flip-flip IA at a certain time t is at the time (t + ,
1) is held in the flip-flop IB, and thereafter every time the clock signal φ is input, the flip-flops lc, l
It is sequentially shifted to the cloth as o, 1+z.

That is, the output data D4 applied to the input terminal (Di) of the circuit under test 20 at a certain time t is sequentially applied to the input terminals (DB), (D
2), (Di).

Therefore, if the data input to two adjacent input terminals (Di) to (Dl) of the circuit under test 20 at a certain time t is 00''', then at the time (t+1) of these two input terminals, The data that can be obtained is “o
There are two sets, ``o''' and ``10''', and if patterns are exhaustively generated in the linear feedback shift register 10, ``o''
o '”, “oo” and “o o '” p10
Two pairs of two patterns ``'' are generated.

Next, when the control signal C1 is 1'', that is, in FIG. 1, each multiplexer 2A to 2° selects and outputs the inverted output signal (Q) of 1E to the lower input, that is, each flip-flop. Explain when to do so.

At this time, the inverted signals of the data stored in each of the flip-flops 18 to 1D are input to the immediately following flip-flops 1B to ]n, and the inverted output signal (Q) of the flip-flop 1c and the inverted signal of the flip-flop IB The output signal (Q>) is input to the exclusive OR gate G1, and the output signal of the exclusive OR gate G1 is input as a feedback signal to the flip-flop IA.At the same time, the inverted output signals of the flip-flops IB to 1r (Q) is connected to the input terminal (D) of the circuit under test 20 via multiplexers 2B to 2E.
i) to (Dl) as a test pattern.

That is, if 0'' is given to the input terminal (Di) of the circuit under test 20 at a certain time t, then the time (t+
1>, the data given to the input terminal (DB) is °°1″
Henceforth, each time the clock signal φ is applied, the data is sequentially shifted while being inverted, such as 0''' to the input terminal (D2) and 1°'' to the input terminal (Dl).

Therefore, if the data input to two adjacent input terminals (Di) to (Dl) of the circuit under test 20 at a certain time t are "' o o", then the time ( There are two sets of data that can be taken at t+1. ''' and "o o '"
, "11"', two patterns of bears are generated.

That is, in this embodiment, two test pattern generators can be realized by switching the control signal C1, and these two test pattern generators can control the input terminals (D4) to (1) of the circuit under test 20. If the data input to two adjacent ones of is 'o o' at time t, the data that can be taken at time (t + 1 >) are 'o o', ''] O', '01'' and All four types of 11″″ can occur.

What has been explained so far is that it is sufficient to have a feedback shift register with the same number of stages of flip-flops as the number of input terminals of the circuit under test; There is no need to use type shift registers. The reason why a feedback shift register having more stages than the number of input terminals of the circuit under test is used is as follows.

In the case of a linear Jifr return shift register with the same number of stages as the number of input terminals of the circuit under test, when the test pattern (D4, D3.D2.DI) at a certain time t is determined, the time (t+1
) is uniquely determined, and this value changes depending on the generating polynomial of the linear feedback shift register. In other words, in the case of a linear feedback shift register with the same number of stages as the number of input terminals of the circuit under test, a detection pattern exists for a hypothetical fault in the case of a certain generator polynomial, but a detection pattern exists in the case of a different generator polynomial. A situation may arise in which there is no such thing.

Since the test pattern generator of the present invention is a feedback shift register having at least one stage more than the number of input terminals of the circuit under test, there is no problem in selecting any of the primitive polynomials as the generator polynomial. This is because the value of the output data D4 at time (t+1) is the data of the flip-flop IA (or its inverted data) at the time, regardless of the generating polynomial.

〔Effect of the invention〕

As explained above, the present invention selects and switches one of the inverted output signal and the non-inverted output signal of these flip-flops, and selects and switches the flip-flops that have at least one stage more than the number of input terminals of the pattern to test 1 of the circuit under test. By forming a feedback shift register equipped with a multiplexer that transmits data to the circuit under test, and supplying the test pattern from the output terminal of a predetermined multiplexer to the circuit under test,
It is possible to generate more sets of two patterns than in the prior art, and even when the circuit under test is composed of eight CMO circuits, there is an effect that a higher failure detection rate can be obtained.

Disjunction gate.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional test pattern generator.

Claims (1)

[Claims] A plurality of flip-flops that output inverted signals and non-inverted signals respectively and are sequentially arranged in multiple stages are inputted with inverted signals and non-inverted signals of each flip-flop except the last stage of these plural flip-flops, and are controlled by a control signal. A plurality of front-stage multiplexers select one of these inverted signals and non-inverted signals and output the selected signal to the flip-flop in the immediately following stage; The final stage multiplexer selects and outputs one of the inverted and non-inverted signals, and the output signal of a predetermined multiplexer of the middle and last stage multiplexers is inputted and the feedback signal is sent to the first stage multiplexer. a feedback circuit that outputs to the flip-flops and forms a feedback shift register together with each of the flip-flops and each multiplexer, and transmits predetermined output signals among the output signals of the middle and last stage multiplexers, respectively; and at least one test pattern output terminal less than the number of stages of the flip-flops.