KR100252763B1 - Audio signal processor enabling volume control - Google Patents

Abstract

PURPOSE: A volume controllable audio signal processor is provided in which a serial/parallel interface reduces the power of a signal based on the number of shift times without using a separate volume control device to perform volume control and sound erasure. CONSTITUTION: A volume controllable audio signal processor includes a shift register(10) for shifting data applied to the data input port in response to a control clock signal, a control clock signal generator(20) for generating the control clock signal in response to volume control and sound erasure signals, the first and second control signals applied from the outside, and a selector(30) for selectively outputting external signal data and the most significant bit of the shift register to the data input port of the shift register in response to the volume control and sound erasure signal. The first control signal is a synchronous signal for dividing the signal data into left and right for stereo output of the signal data. The second control signal is a synchronous signal that is clocked at a predetermined cycle to control data input.

Description

Audio signal processing device with volume control

TECHNICAL FIELD The present invention relates to an audio signal processing apparatus, and more particularly, to an audio signal processing apparatus for controlling muting and volume in a serial / parallel interface of audio using a shift register.

In the conventional audio, the volume is controlled by adjusting a gain by inserting a variable resistor into an analog switch capacitor portion of a digital / analog converter in an audio system for volume control.

However, it is difficult to implement the variable resistor, the area of the circuit is large, and it is difficult to control. In addition, the mute function puts a switch transistor on a chip in an audio system, but there is a problem of increasing noise due to the possibility of glitch occurring at the moment of switching.

The present invention has been made to solve the above problems, volume control by reducing the power of the signal primarily in the serial / parallel interface of the audio signal processing apparatus without having to control the volume in the analog switch capacitor portion of the digital / analog converter And a signal processing apparatus capable of muting.

1 is a simplified diagram for explaining an audio signal processing apparatus according to an embodiment of the present invention.

2A and 2B are timing diagrams for explaining an operation of an audio signal processing apparatus according to an embodiment of the present invention as shown in FIG.

* Explanation of symbols for main parts of the drawings

10: shift register section 20: control clock signal generation section

30: multiplexer

According to an aspect of the present invention, there is provided an audio signal processing apparatus capable of volume control, comprising: a shift register unit for shifting out data applied to a data input terminal in response to a control clock signal; Control clock signal generating means for generating a control clock signal of said shift register section in response to a volume control and a mute signal and externally input first and second control signals; And selecting means for selectively outputting signal data input from the outside or the most significant bit data MSB of the shift register part to a data input terminal of the shift register part in response to the volume control and mute signal, wherein the first control signal Is a synchronization signal for discriminating left and right for the stereo output of the signal data, the second control signal is a synchronization signal that is clocked at a predetermined period to control data input, and the control clock signal generating means is the volume control and mute signal. First logical product means for receiving and ANDing the first and second control signals; Second logical product means for receiving and ANDing the first and second control signals; And a logical sum means for receiving the signals output from the first and second logical products, respectively, and performing logical OR to output the control clock signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

1 is a circuit diagram illustrating an audio signal processing apparatus according to an embodiment of the present invention, in which reference numeral SDATA is a signal data input in series, and BICK is a signal input from an external source, and is clocked at a predetermined period to control data input. LPCK is a signal for stereo output, and is a synchronization signal used to distinguish left and right, and is a signal maintaining a high level or a low level to output left or right data for a predetermined period.

As shown in the figure, the audio signal processing apparatus of the present invention includes a shift register section 10 for shifting out and outputting data applied to the data input terminal D in response to a control clock signal, a volume control and mute signal, and an external device. A control clock signal generator 20 for generating a control clock signal of the shift register 10 in response to an input BICK or LRCK, and SDATA or the shift register 10 in response to a volume control and mute signal; The multiplexer 30 selectively outputs the most significant bit data MSB to the data input terminal of the shift register unit 10.

Specifically, the shift register unit 10 includes a plurality of D flip-flops driven in response to a clock signal, and data is output from the output terminal of each D flip-flop.

In addition, the control clock signal generator 20 receives an inverter 21 for inverting the LRCK signal, a logical product for receiving and logically multiplying the volume control and mute signal, the BICK signal, and the inverted LPCK signal output from the inverter 21. The gate 22, the AND gate 23 for receiving and logically multiplying the BICK signal and the LRCK signal, and the signals output from the two AND gates 22 and 23, respectively, are input and ORed to output a control clock signal. It consists of a logical sum gate 24 for this purpose.

In a general audio signal processing chip, when a serial signal SDATA is input, the signal is input to the shift register unit 10 through the multiplexer 30, and a signal input to the shift register unit 10 is output in response to a general clock signal. It is sequentially shifted from the most significant bit (MSB) via the D flip-flop, and is output in parallel when all signals to the least significant bit (LSB) are input. For example, when SDATA is 16-bit data, when the first bit data is shifted sequentially, the first bit data is shifted to the least significant bit (LSB), and all 16 bits are input to the shift register unit 10. 16 bits are output in parallel from the D flip-flop.

However, in the present invention, after the serial signal SDATA is input, the control clock generator 20 generates a control clock signal so that the data can be output in parallel after performing the volume control and mute functions, and the generated control. The shift operation of the shift register section 10 is performed in synchronization with the clock signal.

That is, when the signals BICK and LRCK input from the outside become high at the same time, after the data SDATA is shifted through the shift register section 10 in response to the control clock signal, the volume control is performed. Data is output in parallel.

Reference numeral 1 in FIG. 1 denotes a clock signal for converting serial data SDATA into parallel data, and reference numeral ② denotes a clock signal for performing a volume control and mute function.

First, when the volume control and mute signal are kept low, the control clock signal generator 20 generates a signal as ① as a control clock signal for converting the serial data SDATA into parallel data, thereby shifting the shift register unit. (10). Therefore, the shift register unit 10 shifts the data SDATA in response to the generated control clock signal and outputs the data in parallel. This operation is the same as in the prior art.

2A and 2B are timing diagrams for explaining an operation of an audio signal processing apparatus according to an exemplary embodiment of the present invention as shown in FIG. 1, and FIG. 2A is an operation during mute operation. 2B is a timing diagram for explaining an operation during volume control.

In the figure, the LRCK signal is input to maintain the high level signal for the output of the left data and the low level signal for the output of the right data, and the BICK signal is continuously input as a signal that is clocked at a certain period.

First, the operation of the mute function will be described with reference to FIG. 2A.

When the volume control and mute signals are continuously input in the high state (H) to perform the mute function, the most significant bit data MSB of the shift register section 10 is selected by the multiplexer 30 to shift the shift register. The serial signal data SDATA is blocked from being inputted by being continuously input to the data input terminal of the section 10. At this time, the control clock generator 20 is clocked during the low level period of the LRCK signal (since FIG. 2a shows the left data output as an example). In a high-in period (a section in which left data is output), a? Signal in which the BICK signal is output as it is is ORed and outputs a control clock signal (1? Therefore, the D flip-flop in the shifter register is shifted in response to the control clock signal (① + ② in FIG. 2a) generated from the control clock generator 20 as described above, thereby outputting the most significant bit output from the multiplexer 30. The data MSB is continuously shifted so that all bits of the shift register are set with only the most significant bit MSB.

Next, the volume control operation will be described with reference to FIG. 2B.

For example, a volume control and a mute signal are input low to perform a volume control operation, and a high level (H) is input for only 2 clocks. For example, a section in which the volume control and mute signals are input low (SDATA input section) ), The control clock signal generator 20 generates the signal ① for converting the serial data SDATA into parallel data as it is, and applies it to the shift register unit 10. Therefore, the shift register unit 10 shifts the data SDATA in response to the control clock signal generated at this time.

Subsequently, when the volume control and mute signals are input high in the low level section (volume control / mute function section) of the LRCK signal (during the a and b sections in the drawing), the shift register unit ( The most significant bit data MSB of 10) is selected and input to the data input terminal of the shift register section 10, thereby preventing the serial signal data SDATA from being input. At this time, the control clock generator 20 generates a ② signal for volume control through the AND gate 22 and outputs it as a control clock signal (1+ 2 in FIG. 2B). Accordingly, as described above, the D flip-flop in the shifter register shifts in response to the control clock signal (1 + 2 in FIG. 2B) except for the highest order and the bit output from the multiplexer 30. The data MSB is shifted twice to attenuate the size of the data by a quarter. Therefore, the size of the data SDATA is attenuated by 1/4 to implement the volume control effect.

On the other hand, if the volume control and mute signal is applied high only during the "a" period, the shift register unit 10 shifts once to attenuate the size of the data by 1/2 to perform the volume control operation.

As described above, the volume control and the mute function can be performed by controlling the shift operation of the shifter register in response to the volume control and the mute signal.

The audio signal processing apparatus according to the present invention described above is not limited to the following claims and drawings, and should be understood by those skilled in the art without departing from the scope of the present invention. Various substitutions, modifications and alterations that may be made by the same are also within the scope of the present invention.

Therefore, the present invention can perform both mute and volume control functions with one input pin while converting a serial signal into a parallel signal, thereby eliminating the need for a separate volume control using a variable resistor in the system. It can reduce the area of, and can eliminate the noise due to the volume control.

Claims (5)

An audio signal processing apparatus capable of volume control, A shift register unit for shifting out data applied to a data input terminal in response to a control clock signal; Control clock signal generating means for generating a control clock signal of said shift register section in response to a volume control and a mute signal and externally input first and second control signals; And Selecting means for selectively outputting signal data input from the outside or the most significant bit data MSB of the shift register part to the data input terminal of the shift register part in response to the volume control and mute signal; The first control signal is a synchronization signal for distinguishing left and right for the stereo output of the signal data, The second control signal is a synchronization signal that is clocked at a predetermined period to control data input. The control clock signal generating means, First logical product means for receiving and multiplying the volume control and mute signals and the first and second control signals; Second logical product means for receiving and ANDing the first and second control signals; And Logic sum means for outputting the control clock signal by receiving and outputting the signals output from the first and second logical means respectively; Audio signal processing apparatus comprising a. The method of claim 1, wherein the control clock signal generating means, Inverting means for inverting said first control signal, And the first logical product receives the inverted first control signal output from the inverting means. The method of claim 2, wherein the volume control and mute signal, The audio signal processing apparatus is input at a "high" level during a mute operation, and input at a "high" level only during a period required for volume control of the signal data during a volume control operation. The method of claim 3, wherein the selection means, And outputting the most significant bit data (MSB) of the shift register unit in response to the "high" level of the volume control and mute signal. The method of claim 1, wherein the shift register unit, And a plurality of D flip-flops driven in response to the control clock signal, wherein the signal data are output in parallel from an output terminal of each of the D flip-flops.