KR0153047B1 - Digital volume control device - Google Patents

Abstract

The present invention relates to a digital volume control device, and in particular, a first clock enable unit for providing a first clock signal in response to an up / down signal; In response to the first clock signal generated by the first clock enable unit and the up / down signal, the shifting operation is performed at a first adjustment speed when the control is performed in a narrow width, and when the control is performed at a large width, A first volume control value generator configured to generate a lower volume control value by performing a shifting operation at a fast second control speed; A second clock enable unit configured to generate a second clock signal at every cycle of the first volume control value; And a second volume control value generator configured to generate a higher volume control value by performing a shifting operation at a first control speed in response to the second clock signal generated by the second clock enable part and the up / down signals.

Therefore, in the present invention, it is possible to adjust the desired volume at a high speed at the time of large volume adjustment.

Description

Digital Volume Control

1 is a circuit diagram of a conventional digital volume control device.

2 is a detailed circuit diagram of the 5-bit bidirectional shift register of FIG.

3 is a timing diagram for explaining the operation of FIG.

4 is a circuit diagram of a digital volume control device according to one preferred embodiment of the present invention.

5 is a detailed circuit diagram of the 5-bit bidirectional shift register of FIG.

6 is a timing diagram for explaining the operation of FIG.

* Explanation of symbols for main parts of the drawings

41: first volume control generator or 5-bit bidirectional shift register

42: second volume control generator or 7-bit bidirectional shift register

43: first clock enable unit 44: second clock enable unit

51-55: 4: 1 multiplexer 56-60: D flip-flop

43-1, 44-5: Oa gate 44-3: inverter

43-2, 44-2, 44-4: AND gate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital volume control device, and more particularly, to a digital volume control device capable of adjusting a volume level at a high speed in the case of adjusting a large volume.

Conventional digital volume control device shifts the shifted adjustment value by shifting the value stored in each shift register in the up / down direction by an up / down signal input using a bidirectional shift register to obtain a user-specified volume level. By operating the attenuation circuit in the final stage, the corresponding volume level is adjusted.

1 is a circuit diagram of a conventional volume control device.

Referring to FIG. 1, a conventional volume control device is provided to enable a 5-bit bidirectional shift register 11, a 7-bit bidirectional shift register 12, and a clock CK1 of the shift register 11. A clock enable section 13 is made.

The 5-bit bidirectional shift register 11 has its output (X1-X5) input as a control signal of the attenuation circuit of 2 dB steps, and the 7-bit bidirectional shift register 12 has its output (Y1-Y7) attenuating 10 dB steps. It is input to the control signal of the circuit.

Among the outputs of the 5-bit bidirectional shift register 11, the most significant bit X5 is used as the clock signal CK2 of the 7-bit bidirectional shift register 12, and the shift registers 11 and 12 are up signals (U). ) Is shifted to the right to perform the up operation, and when the down signal DOWN is applied to the left to perform the up operation.

The clock enable unit 13 is for enabling the clock of the 5-bit shift register 11 when the up or down signal UP or DOWN is applied, and the up and down signals UP and DOWN. The input of the OR gate 14, which is driven when the up or down signal is applied, and the output of the OR gate 14 and the clock signal CK are input, and the clock of the 5-bit shift register 11 is inputted. It consists of the AND gate 15 which enables the signal CK1.

FIG. 2 shows a detailed circuit diagram of the 5-bit bidirectional shift register of FIG.

Referring to FIG. 2, the 5-bit bidirectional shift register 11 includes five D flip-flops 26- that respectively input the outputs of the five 2: 1 multiplexers 21-25 and the multiplexers 21-25. 30).

The first multiplexer 21 is an output of the second D flip-flop 27 applied to the first input terminal I1 and the second input terminal I2 according to the up, down signals UP and DOWN. One of the outputs of the 5D flip-flop 30 is selected and output, and the second multiplexer 22 is applied to the first input terminal I1 according to the up, down signals UP and DOWN. One of the output of the flop 28 and the output of the first D flip-flop 21 applied to the second input terminal I2 is selected and output.

The third multiplexer 23 is applied to the output of the fourth D flip-flop 29 applied to the first input terminal I1 and the second input terminal I2 according to the up, down signals UP and DOWN. One of the outputs of the 2D flip-flop 27 is selected and output, and the fourth multiplexer 24 is applied to the first input terminal I1 according to the up, down signals UP and DOWN. One of an output of the flop 30 and an output of the third D flip-flop 28 applied to the second input terminal 12 is selected and output. The fifth multiplexer 25 is configured to provide an up, down signal UP, ( Selects one of an output of the first D flip-flop 25 applied to the first input terminal I1 and an output of the fourth D flip-flop 29 applied to the second input terminal I2 according to DOWN). .

The first to fifth multiplexers 21-25 select and output one of signals applied to the first input terminal I1 and the second input terminal I2 according to the up, down signals UP and DOWN. If the up, down signals UP and DOWN are respectively 10, the signal applied to the second input terminal I2 is selected. If the up, down signals UP and DOWN are each 1, the first input terminal I1 is selected. Is applied to the signal.

In addition, if the up, down signals UP and DOWN are 0, the multiplexer maintains the previous state and assumes that the state 11 is not present.

The operation of the conventional volume control device as described above will be described in detail with reference to the timing diagram of FIG.

In FIG. 3, the section 31 is in an initial state, and the section 32 is in an up operation state for uplifting in the initial state, the section 33 is in a state in which the up operation is completed, and the section 34 is in the up state. Each down operation state for bringing down the volume is shown.

It is assumed that a conventional volume adjusting device is set to a specific unit volume adjusting value and stored in the registers 11 and 12.

In the initial state, the output of the 5-bit shift register 11 in Figs. 2 (d)-(i) (X1-X50 is 00100 and the output of the 7-bit shift register 12 in Figs. 2 (j)-(o). It can be seen that (Y1-Y7) is set to 1000000.

When the up signal UP as shown in FIG. 2 (b) is applied to increase the volume in the initial state, the output of the OR gate 14 of the clock enable unit 13 becomes high and the AND gate 15 Is applied).

Therefore, when the clock signal CK is applied to the clock terminal CK1 of the 5-bit shift register 11, the shift register 11 as shown in FIG. 2 has an up, down signal UP, and DOWN. As shown in FIGS. 3B and 10C, the multiplexer 21-25 outputs a signal applied to the second input terminal I2 and is applied to the D flip-flop 26-30.

At this time, in the initial state, the output X1-X5 of the D flip-flop 26-30 is 00100. When the up signal UP is applied, a signal applied to the second input terminal I2 by the multiplexer 21-25. Is selected, and its output (X1-X5) is 00010.

In this way, when the up signal is applied, the shift register 21 sequentially outputs the output registers X1-X5 of the shift register 11 from 00100 to 00010, 00001 for each negative edge of the clock signal CK.

Therefore, the output of the shift registers X1-X5 is applied as a control signal of the 2dB step attenuation circuit so that the level of the volume is sequentially increased by 2dB.

The outputs X1-X5 of the shift register 11 then become 10000 at the negative edge of the next clock signal CK. At this time, since the most significant bit output (X5) of the shift register 11 is applied to the clock terminal CK2 of the 7-bit bidirectional shift register 12, the shift register 12 is applied to the clock signal applied to the clock terminal CK2. When the negative edge, i.e., the output X5 of the shift register 11 goes from high to low, its output Y1-Y7 goes from 1000000 to 0100000, so the volume level continues to increase by 2 dB.

That is, during the up operation of the volume, as shown in the section 32 of FIG. 3, the shift registers 11 and 12 are shifted to the right for each clock, and are sequentially increased by 2 dB each time the bit is shifted to the right by one bit. .

On the other hand, when the outputs X1-X5 and (Y1-Y7) of the shift registers 11 and 12 are 00001 and 0100000, respectively, in the section 33 of FIG. The same down signal DOWN as in FIG. 3C is applied to the volume adjustment circuit of FIG.

Therefore, since the output of the OR gate 14 of the clock enable part 13 becomes high and is applied to the AND gate 15, the clock signal CK is applied to the clock terminal CK1 of the 5-bit shift register 11. Is applied.

When the clock signal CK is applied to the clock terminal CK1 of the 5-bit shift register 11, the shift register 11, as shown in FIG. 2, causes the up, down signals UP and DOWN to become third. As shown in Figs. (B) and (c), the multiplexer 21-25 outputs a signal applied to the first input terminal I1 and is applied to the D flip-flop 26-30.

Therefore, when the output signal X1-X5 of the D flip-flop 26-30 is 00001, when the up signal UP is applied, the signal applied to the first input terminal I1 is selected, so the output X1-X5 is selected. ) Becomes 00010.

As such, when the down signal is applied, the shift register 11 is shifted to the left for each negative edge of the clock signal CK so that the outputs X1-X5 of the shift register 11 are sequentially changed from 00001 to 00010, 00100, 01000, 10000. To be sequentially.

Therefore, the output of the shift registers X1-X5 is applied as a control signal of the 2 dB step attenuation circuit so that the level of the volume is sequentially reduced by 2 dB.

The outputs X1-X5 of the shift register 11 then become 00001 on the negative edge of the next clock signal CK. At this time, since the most significant bit output (X5) of the shift register 11 is applied to the clock terminal CK2 of the 7-bit bidirectional shift register 12, the shift register 12 is applied to the clock signal applied to the clock terminal CK2. When the positive edge, i.e., the output X5 of the shift register 11 goes from low to high, its outputs Y1-Y7 go from 0100000 to 1000000 and the volume level continues to decrease by 2 dB.

That is, during the down operation of the volume, as shown in the section 34 of FIG. 3, the shift registers 11 and 12 are shifted to the left by one clock, and the volume level is increased by 2 dB whenever shifted to the left by one bit. Decrease sequentially.

However, the conventional volume control device as described above has a problem that can not be quickly adjusted to the desired volume level when the volume is set very low or very high because the volume level is constantly changed by 2dB.

An object of the present invention is to solve the problems of the prior art as described above, to provide a digital volume control device that can be adjusted at different control speeds in the case of adjusting the narrow width and the large width.

Digital volume control device of the present invention for achieving the above object comprises a first clock enable unit for providing a first clock signal in response to the up / down signal; In response to the first clock signal generated by the first clock enable unit and the up / down signal, the shifting operation is performed at a first adjustment speed when the control is performed in a narrow width, and when the control is performed at a large width, A first volume control value generator configured to generate a lower volume control value by performing a shifting operation at a fast second control speed; A second clock enable unit configured to generate a second clock signal at every cycle of the first volume control value; And a second volume control value generator configured to generate a higher volume control value by performing a shifting operation at a first control speed in response to the second clock signal generated by the immersion second clock enable part and the up / down signal.

Therefore, in the present invention, the volume can be adjusted to the desired volume at the correct speed.

DETAILED DESCRIPTION Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 shows a circuit of a volume control device according to an embodiment of the present invention.

Referring to FIG. 4, the volume control apparatus according to the embodiment of the present invention includes a first volume control value generator, that is, a 5-bit bidirectional shift register 41 and a second volume control value generator, that is, a 7-bit bidirectional shift register 42. , The first clock enable section 43 for enabling the clock CK1 of the 5-bit bidirectional shift register 41 and the clock CK2 of the 7-bit bidirectional shift register 42. And a second clock enable portion 44 for the purpose.

The first clock enable part 43 for enabling the clock CK1 of the 5-bit bidirectional shift register 41 is similar to the clock enable part 23 of FIG. And the first end gate 43-2 are identical in configuration and operation.

The second clock enable unit 44 has a second OR gate 44-1, which is a logic error by using the upper two-bit outputs X4 and X5 of the 5-bit bidirectional shift register 41 as two inputs, and the volume control speed. A second end gate 44-2 for inputting and outputting the selection signal FAST and the output of the second OR gate 44-1, and an inverter for inverting the volume control speed selection signal FAST. 44-3, the third end gate 44-4 which logic-ends the output of the inverter 44-3, the most significant bit output X5 of the 5-bit bidirectional shift register 41, and the second and A third ore for inputting the outputs of the third and fourth gates 44-2 and 44-4, and applying a logic ore to the clock terminal CK2 of the 7-bit bidirectional shift register 42; It was composed of a gate 44-5.

5 shows a detailed view of the 5-bit bidirectional shift register 41 of FIG. 4 in accordance with an embodiment of the present invention.

Referring to FIG. 5, the 5-bit bidirectional shift register 11 according to an embodiment of the present invention may input 5 outputs of the five 4: 1 multiplexers 51-55 and the multiplexers 51-55, respectively. D flip-flops 56-60.

The first multiplexer 51 outputs the second and second flip-flops 57 applied to the first input terminal I1 according to the volume control speed selection signal FAST and the up, down signals UP and DOWN. The output of the 5D flip-flop 60 applied to the input terminal I2, the output of the 4D flip-flop 59 applied to the third input terminal I3, and the 3D flip-flop applied to the fourth input terminal I4 ( Select one of the outputs of 58) and output it.

The second multiplexer 52 outputs and outputs the third 3D flip-flop 58 applied to the first input terminal I1 according to the volume control speed selection signal FAST and the up, down signals UP and DOWN. The output of the first D flip-flop 56 applied to the input terminal I2, the output of the fifth D flip-flop 50 applied to the third input terminal I3, and the fourth D flip-flop applied to the fourth input terminal I4 ( Select one of the outputs of 59) and output it.

The third multiplexer 53 outputs the second and fourth outputs of the 4D flip-flop 59 applied to the first input terminal I1 according to the volume control speed selection signal FAST and the up, down signals UP and DOWN. The output of the 2D flip-flop 57 applied to the input terminal I2, the output of the 1D flip-flop 56 applied to the third input terminal 13, and the fifth D flip-flop applied to the fourth input terminal I4 ( One of the outputs of 60) is selected and output.

The fourth multiplexer 54 outputs and outputs the fifth 5D flip-flop 60 applied to the first input terminal I1 according to the volume control speed selection signal FAST, the up and down signals UP, and DOWN. The output of the 3D flip-flop 58 applied to the input terminal I2, the output of the 2D flip-flop 57 applied to the third input terminal I3, and the first D flip-flop applied to the fourth input terminal I4 ( Select one of the outputs of 56) and output it.

The fifth multiplexer 55 outputs and outputs the first D flip-flop 56 applied to the first input terminal I1 according to the volume control speed selection signal FAST, up, down signals UP, and DOWN. Output of the fourth D flip-flop 59 applied to the second input terminal I2, output of the third D flip-flop 58 applied to the third input terminal I3, and second 2D flip applied to the fourth input terminal I4. One of the outputs of the flop 57 is selected and output.

The first to fifth multiplexers 51 to 55 are applied to the first to fourth input terminals I1 to I4 according to the volume control speed selection signal FAST and the up and down signals UP and DOWN. One of the signals is selected and outputted. When the volume control speed selection signal FAST is 0, a signal applied to the first input terminal I1 is selected when the up, down signals UP and DOWN are 1, respectively. When the up, down signals UP and DOWN are respectively 10, the signal applied to the second input terminal I2 is selected.

When the volume control speed selection signal FAST is 1, a signal applied to the third input terminal I3 is selected when the up, down signals UP and DOWN are 10, respectively. ) And (DOWN) are each 1, the signal applied to the fourth input terminal (I4) is selected.

In addition, if the up, down signals UP and DOWN are 0, the multiplexer maintains the previous state regardless of the volume control speed selection signal FAST, and assumes that the state 11 is not present.

The operation of the volume control device of the present invention having the configuration as described above will be described with reference to the waveform diagram of FIG.

In FIG. 6, the section 61 is the initial state, the sections 62 and 64 are the up operation state for increasing the volume, the section 63 is the fast up operation state for quickly adjusting the volume, Section 65 is a state in which the up operation is completed, sections 66 and 68 are down operation states for bringing down the volume, and sections 67 represent fast down operation states, respectively.

In the sections 61, 62, 64, 65, 66 and 68, the volume control speed selection signal FAST is 0, as shown in FIG. Adjust

That is, in the normal volume control operation, the volume control speed selection signal FAST is turned low and is applied to the second end gate 44-2 of the second clock enable part 44 so that its output is turned low. do.

The volume control speed selection signal FAST in the low state is inverted to the high state through the inverter 44-3 and applied to the third end gate 44-4. Accordingly, the top of the 5-bit bidirectional shift register 41 is applied. Only the bit output X5 is applied to the clock terminal CK2 of the 7-bit bidirectional shift register 42.

Therefore, the volume control device of the present invention increases or decreases the volume level by normal speed, that is, by 2 dB.

On the other hand, the section 43 is a section for performing a fast up operation to quickly increase the volume level. In this section 43, the volume control speed selection signal FAST and the up signal UP become 1, so that the multiplexer 51 -55 selects and outputs a signal applied to the third input terminal I3, respectively.

Therefore, since the fast up operation is performed while the outputs X1-X5 of the D flip-flop 56-60 are 01000, the outputs X1-X5 are 00010.

At this time, the second clock enable part 44 is applied with the highest two-bit output of the 5-bit bidirectional shift register 41 because the volume control speed selection signal FAST of the high state is applied to the second end gate 44-2. X4 of the X4, X5 becomes high to enable the clock terminal CK2 of the 7-bit bidirectional shift register 42 so that the output (Y1-Y7) of the 7-bit bidirectional shift register 42 goes from 0100000 to 0010000. do.

As such, when the up signal is applied, the shift register 41 is shifted 2 bits to the right for each negative edge of the clock signal CK, so that the outputs X1-X5 of the shift register 41 are sequentially 01000 to 00010, 10000, and so on. 007 00000, 00001 sequentially, and the 7-bit bidirectional shift register 42 is also one of the upper 2-bit outputs (X4, X5) of the 5-bit bidirectional shift register 41 according to the operation of the second clock enable unit 44. Each time becomes high, it becomes 0100000, 0010000, 0001000.

Accordingly, the outputs X1-X5 and Y1, Y of the shift registers 41 and 42 are applied as control signals of the 2 dB step attenuation circuit and the 10 dB step attenuation circuit to rapidly decrease the volume level in steps of 4 dB. Let it be.

In the section 67, since the volume control speed selection signal FAST becomes high and the down signal DOWN becomes high, the multiplexers 51-55 select signals applied to the fourth input terminal I4. In the same way as in the fast up operation, the output of the 5-bit bidirectional shift register 51 is shifted left from 01100 to 10001, 00110, 11000, and the output of the 7-bit bidirectional shift register 52 is from 0000100 to 0001000, 0010000, 0100000. As it is shifted to the left, it is shifted to the left by 2 bits, so that the volume is turned down rapidly in 4dB increments.

As described above, when the volume is to be finely adjusted, the low volume control speed selection signal FAST is selected, and when the volume is too high or too low, the high volume control speed selection signal is selected. By selecting (FAST), it is possible to adjust the volume you want at normal speed or at high speed.

According to the present invention as described above, in the prior art, the volume was sequentially up or down by 2dB, but in the present invention, in the normal operation, the volume is gradually adjusted up and down by 2dB type sequentially, and the volume is too high or too low. If you want to adjust the volume up or down by 4dB by adjusting the volume quickly, there is an advantage that the user can easily adjust the desired volume. In addition, the control device of the present invention has the advantage that can be used not only in the volume control device, but also in the tone (tone) control device.

Claims (3)

A first clock enable unit configured to provide a first clock signal in response to an up / down signal; In response to the first clock signal generated by the first clock enable unit and the up / down signal, the shifting operation is performed at a first adjustment speed when the control is performed in a narrow width, and when the control is performed at a large width, A first volume control value generator configured to generate a lower volume control value by performing a shifting operation at a fast second control speed; A second clock enable unit configured to generate a second clock signal at every cycle of the first volume control value; And a second volume control value generator configured to generate a higher volume control value by performing a shifting operation at a first control speed in response to a second clock signal generated by the second clock enable unit and the up / down signal. Digital volume control device, characterized in that. According to claim 1, wherein the first adjustment value generator in response to the volume control speed selection signal, when adjusting the narrow width in response to the up / down signal of the previously generated first adjustment value of about one bit before and after A plurality of multiplexers for selecting a value before and after two bits in response to an up / down signal among previously generated first adjustment values when selecting and adjusting a large amount; And a plurality of flip flops for respectively inputting and latching an output of a corresponding multiplexer in response to the first clock signal. 2. The apparatus of claim 1, wherein the second clock enable portion comprises: first means for providing the most significant bit output of the first adjustment value generator as a clock signal of the second adjustment value generator when narrowly adjusted; Second means for combining the output of the upper two bits of the first adjustment value generator to provide a clock signal of the second adjustment value generator when the adjustment is large; And third means for selecting outputs of the first and second means in response to the volume control speed selection signal and generating the second clock signal.