JP3038757B2 - Shift register circuit - Google Patents

Abstract

PURPOSE:To attain the fast working and a small structure for a shift register by using the rear stage part of two pairs of latch circuits connected in series and forming a single bit as a 2-input NOR gate where a clock is used as one of both inputs. CONSTITUTION:Each of register parts 1a1 - 1a5 consists of a latch circuit L1 where a transfer gate TG, an inverter 2, and a clocked inverter 3 are cascaded in a parallel circuit and a NOR gate 4 where a clock signal phi is inputted via one of two input terminals. In other words, the rear stage part of two pairs of latch circuits connected in series forming a single bit is used as a NOR gate 5. When an input signal DIN is inputted, the data of an H level is shifted to a higher rank bit from a lower rank bit at the rise and fall time points of a clock phi. This shift speed is doubled. Thus the faster working and a small structure are attained for a shift register.

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a shift register circuit, and more particularly to a shift register circuit for transferring 1-bit data.

[Conventional technology]

FIG. 5 is a circuit diagram of an example of a conventional shift register circuit.

This shift register circuit includes a transfer gate TG having a CMOS structure, an inverter 2 and a clocked inverter 3.
Latch circuits L ₁ , L
_There are four stages of register units 1 _C1 to 1 _{C4 in} which ₂ are cascade-connected, and the registers of each stage output signals S1 _{b to} S _4b of each bit.

As shown in FIG. 6, when the data input D _IN is input,
At each rising edge of clock signal φ, “H” level data is shifted to upper bits by one bit.

[Problems to be solved by the invention]

In the above-described conventional shift register circuit, data is shifted from lower bits to upper bits at the rise of the clock φ.

That is, only one bit of data can be shifted in one cycle of clock φ.

Therefore, when data is shifted at a high speed, there is a disadvantage that the clock φ must be input at the high-speed cycle.

Further, when the number of bits is large, the number of MOS transistors constituting the circuit is large and it is difficult to reduce the size.

An object of the present invention is to provide a small shift register circuit having high-speed characteristics.

[Means for solving the problem]

The shift register circuit of the present invention supplies an input signal from a lower bit to a source of a transfer gate, and connects a drain of the transfer gate, an input terminal of an anti-parallel inverter and an output terminal of a clocked inverter. The output terminal of the inverter and the input terminal of the clocked inverter are connected to one input terminal of a two-input logic gate, a clock signal is input to the other input terminal, and the output terminal of the two-input logic gate is connected to the upper bit. It is configured by cascading a plurality of register units connected to the input terminal.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of a first embodiment of the present invention.

The shift register circuit according to the present embodiment includes a register _1a1
The to 1 _a5 latch circuit L ₁ Cascaded and parallel circuit of a transfer gate TG and the inverter 2 and the clocked inverter 3 constitute a NOR gate 4 having one input terminal for inputting a clock signal phi.

That is, the latch circuits L _1, the rear stage part L ₂ of L ₂ connected to two pairs of series constituting the conventional register 1 _C1 shown in FIG. 5 is, in the embodiment of the present invention, NOR It is gate 5.

FIG. 2 is a timing chart of each signal for explaining the operation of the circuit of FIG.

When the input signal _DIN is input, the "H" level data is shifted from the lower bit to the upper bit at each rising and falling time of the clock φ.

 Here, the shift speed is twice the conventional speed.

 FIG. 3 is a circuit diagram of a second embodiment of the present invention.

In this embodiment, the shift register unit 1 _a1 shown in FIG.
The shift register circuit according to the first embodiment is the same as the shift register circuit according to the first embodiment except that the NOR gate 4 of ~ _1a5 is replaced with a NAND gate 5.

In this shift register circuit, as shown in FIG.
Since the same phase clock signal φ is input to both the NAND gate 5 and the transfer gate TG, 1-bit “L” level data is transferred from the lower bit to the upper bit at each rising and falling edge of the clock. Has shifted to

〔The invention's effect〕

As described above, according to the present invention, the latter part of the two sets of serially connected latch circuits constituting one bit of the conventional shift register has a clock as one input.
By using an input NOR gate or a two-input NAND gate, data can be shifted from lower bits to upper bits at the rising and falling edges of the clock.

That is, data can be shifted by two bits in one cycle of the clock, and the speed of data shift can be increased.

In addition, the two-input NOR gate or the two-input NAND gate can reduce the number of elements by four when calculated at the transistor level as compared with the latch circuit forming the conventional shift register circuit. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a timing chart of each signal for explaining the operation of the circuit of FIG. 1, and FIG. 3 is a second embodiment of the present invention. FIG. 4 is a timing chart of each signal for explaining the operation of the circuit of FIG. 3, FIG. 5 is a circuit diagram of an example of a conventional shift register circuit, and FIG. FIG. 5 is a timing chart of each signal for explaining the operation of the circuit of FIG. 5; 1 _a1 to 1 _a5 , 1 _b1 to 1 _b5 ... shift register section, 2 ... inverter, 3 ... clocked inverter, 4 ... 2 input NO
R gate, 5 ... 2 input NAND gate, D _IN ... input signal,
D ₀ …… Output signal, L ₁ , L ₂ …… Latch circuit, S _{1a to} S _5a , S _1b
~ S _5b …… Bit signal, TG… Transfer gate,
φ: Clock signal.

Claims (1)

(57) [Claims] An input signal from a lower bit is supplied to a source of a transfer gate, and a drain of the transfer gate is connected to an input terminal of an anti-parallel inverter and an output terminal of a clocked inverter. Is connected to the input terminal of the clocked inverter by 2
A plurality of cascaded register units are connected to one input terminal of the input logic gate, input a clock signal to the other input terminal, and connect the output terminal of the two-input logic gate to the input terminal of the upper bit. Characteristic shift register circuit.