JP3143022B2 - JK flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a JK flip-flop circuit comprising a semiconductor integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, as a technique in this kind of field, for example, there has been a technique shown in FIG.

FIG. 7 is a circuit diagram showing a configuration example of a conventional JK flip-flop circuit.

According to the JK flip-flop circuit, when the "H" level J signal and the "L" level K signal are input to the terminals 101 and 102, respectively, NO
The output of R gate 103 is at "L" level, and the output of NOR gate 105 is at "H" level. As a result, the output of clocked inverter 106 attains "L" level at the next rising edge of inverted clock signal BCP, and the outputs of antiparallel-connected inverters 107 and 108 attain "H" level.

When the clock signal CP subsequently rises, the output of the clocked inverter 109 goes low. Therefore, the inverter 1 connected in anti-parallel
The output signal Q, which is the output of the inverter 10,10, becomes "H" level, the inverted output signal BQ, which is the output of the clocked inverter 109, becomes "L" level, and the JK flip-flop circuit is set.

When the "L" level J signal and the "H" level K signal are input to the terminals 101 and 102, the output of the NOR gate 105 becomes "L" level.
As a result, the output signal Q becomes "L" level, and this J-
The K flip-flop circuit is reset.

When the J signal and the K signal both having the "L" level are input to the terminals 101 and 102, the output signal Q maintains the previous state. Also, terminals 101 and 10
2, when the J signal and the K signal both at the “H” level are input, the entire circuit becomes a toggle flip-flop circuit, and every time the clock signal CP changes from the “L” level to the “H” level. The output signal Q is inverted.

[0008]

However, in the above-mentioned conventional JK flip-flop circuit, the number of MOS transistors constituting the circuit is large, so that the area occupied by the MOS transistor when used in an integrated circuit increases, and There was a problem that the cost was increased. That is, when the circuit shown in FIG.
The input NOR gate 103 has four elements, the K signal and the NOR
The AND-NOR composite gate 105 to which the output of the gate 103 is input is 6 elements, and the two clocked inverters 106 and 109 are each 4 elements, for a total of 8 elements, and the four inverters 107, 108, 110 and 111 are respectively There are a total of eight elements with two elements. These are all summed up to 26 elements.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a JK flip-flop circuit which can be configured with a small number of elements. Another object is to provide a JK flip-flop circuit in which the area occupied by the integrated circuit is reduced and the cost of the integrated circuit can be reduced.

[0010]

According to a first aspect of the present invention, at least three first conductive type MOS transistors connected in series between a first power supply node and an output node are provided. A transistor, at least three second conductivity type MOS transistors connected in series between the output node and a second power supply node, and a first level holding a voltage level corresponding to an output from the output node Holding part,
A clocked inverter connected to an output side of the first level holding unit; and a second level holding unit holding a voltage level corresponding to an output of the clocked inverter, the second level holding unit J whose output is the output data
-K flip-flop circuit, wherein the first conductivity type M
At least a clock signal, an inverted signal of the K signal, and an inverted signal of the output data are supplied to each gate of the OS transistor, and the second conductive type MOS
At least an inverted signal of a clock signal, a J signal, and an inverted signal of the output data are supplied to each gate of the transistor.

A second feature of the present invention is that at least three first conductivity type MOS transistors connected in series between a first power supply node and an output node;
At least three second conductivity type MOS transistors connected in series between the power supply node and a first level holding unit for holding a voltage level corresponding to an output from the output node; A clocked inverter connected to the output side of the holding unit; and a second level holding unit for holding a voltage level corresponding to the output of the clocked inverter, wherein the output of the clocked inverter is output data. -K flip-flop circuit, wherein at least a clock signal, an inverted signal of a J signal, and the output data are supplied to each gate of the first conductivity type MOS transistor, and the second conductivity type MOS transistor is provided.
At least an inverted signal of a clock signal, a K signal, and the output data are supplied to each gate of the S transistor.

[0012]

According to the present invention having the above-described configuration, for example, when the J signal and the K signal are different, the output data is set or reset according to the contents, and the J signal and the K signal are set.
When the signals are the same, the previous output data is output or the toggle mode is set according to the contents. As described above, a function equivalent to that of the conventional JK flip-flop circuit can be realized with a small number of elements.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of a JK flip-flop circuit showing a first embodiment of the present invention.

This JK flip-flop circuit has a P-type MOS transistor of a first conductivity type between a power supply potential VDD (first power supply node) and a node N1 (output node).
Channel MOS transistors (hereinafter simply referred to as P-MOS) 1, 2, and 3 are connected in series. Further, the node N1 and a ground potential GND (second power supply node)
And an N-channel MOS transistor (hereinafter simply referred to as an N-MOS) which is a second conductivity type MOS transistor.
4, 5, and 6 are connected in series.

The gates of the P-MOSs 1 and 2 are connected to input terminals 7 and 8, respectively. The input terminals 7 and 8 receive a clock signal CP and an inverted signal BK of a K signal, respectively. It has become. In addition, the NM
Input terminals 9 and 10 are connected to the gates of the OSs 4 and 5, respectively. The inverted terminals BCP and J of the clock signal CP are input to the input terminals 9 and 10, respectively.

Inverters 11 and 12 (first level holding units) connected in anti-parallel are connected between the nodes N1 and N2, and a clocked inverter 13 is connected to the node N2. ing. Here, the clocked inverter 13 sets the clock signal CP to “H”.
It has the function of inverting the input when it is level and outputting it. Node N on the output side of clocked inverter 13
3 is connected to each gate of the P-MOS3 and the N-MOS6.

The inverters 14 and 15 (second inverters) are connected in anti-parallel between the node N3 and the output terminal 16.
, And the output signal Q is transmitted from the output terminal 16, while the node N3 is connected to the output terminal 17, and the inverted signal BQ of the output signal Q is transmitted from the output terminal 17. It has become.

Next, the operation (A), (B),
(C) will be described.

(A) Operation when the J signal is at "H" level and the K signal is at "L" level When the J signal is at "H" level and the K signal is at "L" level, the N-MOS 5 is turned on. , P-MOS2 are turned off.
Here, when the node N1 is at the "H" level, the node N3 is also at the "H" level, so that the N-MOS 6 is on. At this time, when the inverted clock signal BCP goes to the "H" level, N-MOS MOS4 is also turned on, and node N1 changes from "H" level to "L" level. Then, when the clock CK rises to the “H” level next, the node N3, that is, the output terminal 17 goes to the “L” level, and the output terminal 16 goes to the “H” level. That is, the output signal Q becomes "H" level, and the inverted output signal BQ becomes "L" level.

When node N1 is at "L" level, node N2 is held at "H" level by inverters 11 and 12, so that node N3 is at "L" level.
The output terminal 16 is maintained at the “H” level by the inverters 14 and 15. At this time, since the node N3 is at the “L” level, the P-MOS 3 is on and the N-MOS 6 is off, but since the P-MOS 2 is off, the clock C
Even if K goes low and P-MOS1 turns on, the potential at node N1 does not change. Therefore, even if clock CK goes high next time and clocked inverter 13 is activated, the output will not change. Signal Q maintains "H" level.

(B) Operation when the J signal is at "L" level and the K signal is at "H" level When the J signal is at "L" level and the K signal is at "H" level, the N-MOS 5 is turned off. , P-MOS2 are turned on.
Here, when the node N1 is at the "L" level, the node N2 is held at the "H" level by the inverters 11 and 12, so that the node N3 is at the "L" level. As a result, the P-MOS3 is on. At this time, when the clock signal CP goes to the “L” level, the P-MOS1 turns on, and the node N1 changes from the “L” level to the “H” level. Then, when the clock CK rises to the “H” level next time, the node N3, that is, the output terminal 17 goes to the “H” level, and the output terminal 16 goes to the “L” level.
That is, the output signal Q is at the “L” level,
Attains an "H" level, and the circuit is set.

When node N1 is at "H" level, node N2 is held at "L" level by inverters 11 and 12, so that node N3 is at "H" level.
The output terminal 16 is maintained at the “L” level by the inverters 14 and 15. At this time, since the node N3 is at the “H” level, the P-MOS 3 is off and the N-MOS 6 is on, but since the N-MOS 5 is off, the inverted clock signal BCK becomes “H” level. Even if the N-MOS 4 is turned on, the potential of the node N1 does not change. Therefore, even if the clock CK goes high next time and the clocked inverter 13 is activated, the output signal Q maintains the low level. I do.

(C) Operation when both J signal and K signal are at "L" level When both J signal and K signal are at "L" level, NM
The OS5 and the P-MOS2 are both off, and the potential of the node N1 does not change even if the clock signal CP goes to "L" level or its inverted signal BCP goes to "H" level. Therefore, the previous state of the node N2 and the output terminal 16 is maintained by the inverters 11 and 12 and the inverters 14 and 15, respectively. Therefore, next, the clock signal CP goes high and the clocked inverter 1
Even if 3 is activated, the output signal Q maintains the previous state.

(D) Operation when both J signal and K signal are at "H" level When both J signal and K signal are at "H" level, NM
OS5 and P-MOS2 are both on. At this time,
The entire circuit is a toggle flip-flop circuit (toggle mode), and the output signal Q is inverted each time the clock signal CP changes from “L” level to “H” level.

As described above, it can be seen that the circuit of FIG. 1 operates as a JK flip-flop circuit.

The number of elements of the circuit of this embodiment is P-MOS
1, 2, 3, and N-MOSs 4, 5, 6 for a total of 6 elements, and four inverters 11, 12, 14, and 15 each for a total of 8 elements for 2 elements
The element and the clocked inverter 13 become four elements,
A total of 18 elements can be used, and the number of elements can be significantly reduced as compared with the case where the conventional circuit of FIG. 7 having the same function requires a total of 26 elements.

FIG. 2 shows a modified example of the first embodiment.
FIG. 2 is a circuit diagram of a −K flip-flop circuit, in which components common to FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

This JK flip-flop circuit includes two-input NAND gates 11A and 14A in place of the inverters 11 and 14 in the circuit shown in FIG. 1, and one of the inputs of these NAND gates 11A and 14A is provided. It is commonly connected to an SN signal input terminal 21.

According to this circuit, when the SN signal is at the "L" level, the output signal Q is at the "H" level and the inverted output signal BQ is at the "L" level.

FIG. 3 is a circuit diagram of a JK flip-flop circuit showing another modification of the first embodiment. Elements common to those in FIG. 1 are denoted by the same reference numerals, and are described in detail. Is omitted.

This JK flip-flop circuit has two-input NOR gates 11B and 14B in place of the inverters 11 and 14 in the circuit shown in FIG.
One of the inputs of the NOR gates 11B and 14B is commonly connected to an R signal input terminal 22.

According to this circuit, when the R signal is at the "H" level, the output signal Q is at the "L" level and the inverted output signal B
Q is reset to the “H” level.

FIG. 4 is a JK diagram showing a second embodiment of the present invention.
FIG. 2 is a circuit diagram of a flip-flop circuit, in which components common to FIG. 1 are denoted by the same reference numerals.

This JK flip-flop circuit is different from the circuit shown in FIG. 1 in that an inverted signal BJ of the J signal is input to the terminal 8 in place of the inverted signal BK of the K signal, and a terminal 10 is replaced with the J signal. Input the K signal and output terminal 16
, And an output signal Q from the output terminal 17. That is, according to the configuration of the present embodiment, the output signal Q extracted from the node N3 is supplied to each gate of the P-MOS3 and the N-MOS6.

Next, the operations (A), (B),
(C) will be described.

(A) Operation when the J signal is at the "H" level and the K signal is at the "L" level When the J signal is at the "H" level and the K signal is at the "L" level, the N-MOS 5 is turned off. , P-MOS2 are turned on.
Here, when the node N1 is at the "L" level, the node N3 is also at the "L" level, so that the P-MOS3 is also on. At this time, when the signal BCP goes to the "L" level, the P-MOS1 Turns on. Node N1 changes from "L" level to "H" level, and then clock signal CP
Rises to the "H" level, the node N3 goes to the "H" level, the output terminal 16 goes to the "L" level, and the circuit is set.

When node N1 is at "H" level, node N3 is at "H" level, P-MOS3 is off and N
-MOS6 is on, but N-MOS5 is off. Therefore, even if the inverted clock signal BCP goes to "H" level and N-MOS4 is turned on, the potential of the node N1 does not change. Even if signal CP attains "H" level, output signal Q remains at "H" level, and the circuit is in the set state.

(B) Operation when the J signal is at "L" level and the K signal is at "H" level When the J signal is at "L" level and the K signal is at "H" level, the N-MOS 5 is turned on. , P-MOS2 are turned off.
Here, when the node N1 is at the "H" level, the node N3 is also at the "H" level, and therefore, the N-MOS 6 is also on. At this time, the inverted clock signal BCP becomes “H”.
Level, the N-MOS 4 is turned on and the node N
1 changes from the “H” level to the “L” level, and when the clock CK subsequently rises to the “H” level, the node N
3 goes low and the output terminal 16 goes high. That is, the circuit is reset.

When the node N1 is at the "L" level, the node N3 is at the "L" level,
-MOS6 is off, but P-MOS2 is off, so that the clock signal CP goes to "L" level and PM-
Even when OS1 is turned on, the potential of the node N1 does not change. Therefore, even if the clock signal CP goes high next time, the output signal Q remains at low level, and the circuit is in a reset state. .

(C) Operation when both J signal and K signal are at "L" level When both J signal and K signal are at "L" level, NM
OS5 and P-MOS2 are both off and the node N1
Does not change even if the clock signal CP goes low or the inverted signal BCP goes high, and the next time the clock signal CP goes high, the output signal Q remains unchanged. Maintain state.

(D) Operation when both the J signal and the K signal are at the "H" level When both the J signal and the K signal are at the "H" level, NM
OS5 and P-MOS2 are both on. At this time,
Like the circuit of FIG. 1, the entire circuit is a toggle flip-flop circuit (toggle mode), and the clock signal CP
Changes from "L" level to "H" level, the output signal Q is inverted.

As described above, it can be seen that the circuit of this embodiment also operates as a JK flip-flop circuit.

Also, the number of elements of the circuit of this embodiment can be constituted by a total of 18 elements as in the case of the circuit of FIG. 1, which is much larger than that of the conventional circuit of FIG. 7 having the same function. The number of elements can be reduced.

FIG. 5 shows a modified example of the second embodiment.
FIG. 5 is a circuit diagram of a −K flip-flop circuit, in which elements common to FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted. This JK flip-flop circuit includes two-input NAND gates 11A and 14A in place of the inverters 11 and 14 in the circuit shown in FIG. 4, and one of the inputs of these NAND gates 11A and 14A is connected to terminal 2
1 is connected in common, and an RN signal is input to this terminal 21.

According to this circuit, when the RN signal is at "L" level, the circuit is reset.

FIG. 6 is a circuit diagram of a JK flip-flop circuit showing another modification of the second embodiment. Elements common to those in FIG. 4 are denoted by the same reference numerals, and are described in detail. Is omitted.

This JK flip-flop circuit has two input NOR gates 11B and 14B in place of the inverters 11 and 14 in the circuit shown in FIG.
One of the inputs of the NOR gates 11B and 14B is commonly connected to a terminal 22, and an S signal is input to this terminal 22.

According to this circuit, when the S signal is at "H" level, the circuit is set.

FIGS. 8 and 9 show a second level fetching and holding circuit comprising a clocked inverter 13 and inverters 14 and 15 in FIGS. 1 and 4, respectively, comprising a transmission gate 16 and inverters 17 and 18. Another embodiment will be described.

[0050]

As described above in detail, according to the present invention, the number of elements can be significantly reduced as compared with the conventional JK flip-flop circuit while having the same function as the conventional JK flip-flop circuit. As a result, the area occupied by the integrated circuit can be reduced, and the cost of the integrated circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a JK flip-flop circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a JK flip-flop circuit showing a modification of the first embodiment.

FIG. 3 is a circuit diagram of a JK flip-flop circuit showing another modification of the first embodiment.

FIG. 4 is a circuit diagram of a JK flip-flop circuit showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a JK flip-flop circuit showing a modification of the second embodiment.

FIG. 6 is a circuit diagram of a JK flip-flop circuit showing another modification of the second embodiment.

FIG. 7 is a circuit diagram showing a configuration example of a conventional JK flip-flop circuit.

FIG. 8 is a circuit diagram of a JK flip-flop circuit showing still another modification of the first embodiment.

FIG. 9 is a circuit diagram of a JK flip-flop circuit showing still another modification of the second embodiment.

[Explanation of symbols]

 1, 2, 3 P-MOS 4, 5, 6 N-MOS 11, 12 Inverter (first level holding unit) 13 Clocked inverter 14, 15 Inverter (second level holding unit) VDD Power supply potential GND Ground N1 Output node CP Clock signal BCP Inversion signal of clock signal CP JJ signal BJ Inversion signal of J signal KK signal BK Inversion signal of K signal Q Output signal BQ Inversion signal of output signal Q 11A, 14A Two-input NAND gate 11B, 14B 2-input NOR gate

Claims (4)

(57) [Claims] 1. A JK flip-flop circuit,
At least three first conductivity type MOS transistors are connected in series between a first power supply node and an output node, and a clock signal, an inverted signal of a K signal, An inverted Q output signal is input, at least three second conductivity type MOS transistors are connected in series between a second power supply node and the output node , and a gate of each of the second conductivity type MOS transistors is connected. Wherein the inverted signal of the clock signal, the J signal, and the inverted signal of the Q output are input to the JK flip- flop circuit. 2. A JK flip-flop circuit,
At least three first conductive type MOS transistors are connected in series between a first power supply node and an output node , and a clock signal, an inverted signal of a J signal, A Q output signal is input, at least three second conductivity type MOS transistors are connected in series between a second power supply node and the output node , and the gate of each of the second conductivity type MOS transistors is connected to the gate of the second conductivity type MOS transistor. A JK flip-flop circuit to which an inverted clock signal, a K signal, and a Q output signal are input. 3. At least three first conductivity type MOS transistors connected in series between a first power supply node and an output node, and connected in series between the output node and a second power supply node. At least three second conductivity type MOS transistors, a first level holding unit for holding a voltage level corresponding to an output from the output node, and a clocked transistor connected to an output side of the first level holding unit. An inverter; and a second level holding unit for holding a voltage level corresponding to the output of the clocked inverter.
A JK flip-flop circuit that uses the output of the level holding unit as output data, wherein the gate of each of the first conductivity type MOS transistors is:
At least a clock signal, an inverted signal of a K signal, and an inverted signal of the output data are supplied, respectively, and at least a inverted signal of the clock signal, a J signal, and the output data are supplied to each gate of the second conductivity type MOS transistor. JK flip-flop circuit for supplying inverted signals of 4. At least three first conductivity type MOS transistors connected in series between a first power supply node and an output node, and connected in series between the output node and a second power supply node. At least three second conductivity type MOS transistors, a first level holding unit for holding a voltage level corresponding to an output from the output node, and a clocked transistor connected to an output side of the first level holding unit. A JK flip-flop circuit comprising: an inverter; and a second level holding unit that holds a voltage level corresponding to an output of the clocked inverter, wherein the JK flip-flop circuit uses an output of the clocked inverter as output data. In each gate of the one conductivity type MOS transistor,
At least a clock signal, an inverted signal of the J signal, and the output data are supplied, respectively, and at least an inverted signal of the clock signal, the K signal, and the output data are supplied to each gate of the second conductivity type MOS transistor. A JK flip-flop circuit.