JP3024397B2 - Double edge trigger flip-flop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D-type flip-flop composed of a CMOS circuit, and more particularly to a double edge-triggered flip-flop capable of inputting data at both rising and falling edges of a clock signal.

[0002]

2. Description of the Related Art Most digital LSIs use clock pulses as data processing timing. Usually, a sequential circuit is configured by inserting a combinational circuit between flip-flops (latches). When a commonly used edge trigger flip-flop is used as such a flip-flop, data is updated each time the clock rises. However, since the CMOS circuit consumes power every time a signal changes, the falling transition of the clock signal wastefully consumes power.

As the scale of an LSI increases, the power consumption of the clock signal itself becomes several tens of the power consumption of the entire LSI.
%. For example, Dobberpuh
l, D. Et al., “A 200 MHz 64b D
ual-Issue CMOS Microproceses
sor "(ISSCC digest of technology
nip. 106-107, F
eb. , 1992), the load capacitance of the clock driver of this processor is 3250 pF.

The power consumption P of a CMOS circuit is given by f = clock frequency, C = load capacity, and Vdd = power supply voltage.
Since P = f × C × (Vdd) ² , this alone consumes 7 W of power (3.3 V, clock frequency = 200 MHz).

In view of the above, several double edge trigger flip-flops capable of capturing data at both the rising and falling edges of a clock signal have been recently proposed. The present invention relates to speeding up and reducing power consumption of the double edge trigger flip-flop.

Afghahi, M .; "Do
double Edge-Triggered D-Fli
p-Flops for High-Speed CM
OSCircuits ”(IEEE Journal
of Solid-State Circuits, v
ol. 26, no. 8, Aug. , 1991). Hereinafter, two conventional examples will be described with reference to the drawings.

FIG. 4 is a circuit diagram of a first conventional double edge trigger flip-flop. According to FIG.
A data input (D) signal line 10, a clock input (C) signal line 11, a data output (Q) signal line 14, and a gate circuit of a dynamic circuit composed of CMOS transistors
21, 22, 31, 32, 33, 3)
4, a gate 22 includes a dynamic inverter having a precharge potential of a high level, a gate 31 includes a dynamic inverter having a precharge potential of a low level, and a CMOS static inverter 35, and gates 21, 22, and 31 include The gates 32, 33, and 34 are D-type edge-triggered flip-flops synchronized with the rising edge of the clock signal C and synchronized with the falling edge of the clock signal C.

In this double edge trigger flip-flop, the clock signal line 11 and the data signal line 10 are connected to the input terminal of a gate 21, and the output terminal of the gate 21 and the clock signal line 11 are connected to the input terminal of a gate 22. Then, the output terminal of the gate 22 and the clock signal line 11 are connected to the input terminal of the gate 31. Clock signal line 11 and data signal line 1
0 is connected to the input terminal of the gate 32, the output terminal of the gate 32 and the clock signal line 11 are connected to the input terminal of the gate 33, and the output signal of the gate 33 and the clock signal C are connected to the input terminal of the gate 34. Connecting.

Further, the output terminals of the gate 31 and the gate 34 are commonly connected to the input terminal of the inverter 35,
5 is configured to be the data output signal Q.

Next, the operation will be described.

When the clock signal C is at a low level,
Gate 21 operates as an inverter. The gate 22 is precharged to a high level by the low level of the clock signal C, and the gate 31 enters a high impedance state.

Consider a case where the clock signal C rises to a high level.

When data input D is low level,
The gate 21 holds the previous value (bi-level) in the high impedance state, the gate 22 goes to the low level, and the gate 31 outputs the low level.

When the clock signal C is at a high level,
Gate 32 operates as an inverter. Gate 33 is precharged to a low level, and gate 34 is
It becomes an impedance state.

Consider a case where the clock signal C falls and goes to a low level.

When data input D is high,
The gate 32 holds the previous value (low level) in the high impedance state, the gate 33 goes high, and the gate 34 outputs the low level.

When the data input D is at a low level,
Gate 32 goes high and gate 33 goes high.
In the impedance state, the previous value (low level) is held, and the gate 34 outputs a high level.

FIG. 5 shows a timing chart of the operation of FIG.

Reference numerals 31 and 34 in FIG. 5 represent output levels of the gates 31 and 34, respectively. Actually, as shown in FIG. 4, since the output terminals are wired-connected to each other, when one is in a high impedance state, the other value is a logical value. Therefore, data sampled at both the falling edge and the rising edge of the clock signal C appears on the Q output signal line 14.

The features of this circuit are as follows: (1) The number of transistors is twenty.

(2) The power consumption due to the clock load capacity is Pc = f × (8 × Cg) × (Vdd) ² .

(3) The power consumption by the flip-flop itself is Pf = (１ ／ × f) × (12 × Cg + 14 × C)
d) × (Vdd) ² . Where f = clock frequency, Cg = gate capacitance, Cd = drain capacitance, Vdd =
Power supply voltage.

(4) f = 40 MHz, Cg = 0.010
Assuming that pF, Cd = 0.005 pF, Vdd = 5.0 V, Pc = 80 μW, Pf = 48 μW, Pc + Pf = 1
28 μW.

Next, FIG. 6 shows a second conventional example of a double edge trigger flip-flop.

A data input (D) signal line 10, a clock input (C) signal line 11, a data output (Q) signal line 14, and gates 21, 22, 32, 33 are the same as those in the first conventional example (FIG. 4). It is.

Inverters 36 and 37 using a CMOS static circuit, NAN using a CMOS static circuit
A D gate 38 is provided.

In this double edge trigger flip-flop, the output terminal of the inverter 36 connecting the data signal line 10 to the input terminal and the clock signal line 11 are connected to the input terminal of the gate circuit 22, and the output terminal of the gate 22 is connected to 2 Input NAND
38 to one input terminal. Clock signal line 11
And the data signal line 10 are connected to the input terminal of the gate 32, and the output terminal of the gate 32 and the clock signal 4 line 11 are connected to the gate 33.
Connect to The output terminal of the gate 33 is connected to the input terminal of the inverter 37, and the output signal of the two-input NAND 38 is configured as the data signal Q.

Next, the operation will be described.

In the first conventional example, attention is paid to two points that the gates 31 and 34 operate as selectors by the clock input C and that one of the gates 22 and 33 is in the precharge period.

In the second conventional example, the precharge is adjusted to a high level by the inverter 37, so that N
The AND gate 38 plays the role of a selector.

The inverter 38 is necessary for aligning the rising and falling logics. By using such a circuit, the number of gates connected to the clock signal line 11 is reduced, thereby reducing the load capacitance.

The features of this circuit are as follows: (1) The number of transistors is twenty. (2) The power consumption due to the load capacity of the clock is Pc = f
× (6 × Cg) × (Vdd) ² . (3) The power consumption due to the flip-flop itself is Pf =
(1/4 × f) × (14 × Cg + 15 × Cd) × (Vd
d) ² . Here, f = clock frequency, Cg = gate capacitance, Cd = drain capacitance, and Vdd = power supply voltage. (4) f = 40 MHz, Cg = 0.010 pF, Cd =
Assuming 0.005 pF and Vdd = 5.0 V, Pc = 6
0 μW, Pf = 54 μW, Pc + Pf = 114 μW.

[0033]

SUMMARY OF THE INVENTION Microprocessor L
The method of setting the mode register in the SI has the following disadvantages. (1) There are many transistors. (20Tr) Although it is smaller as a double edge trigger flip-flop, it is more than a normal edge trigger flip-flop. Therefore, the layout area increases. (2) Large power consumption.

Since the number of transistors is large, both the power consumption due to the load capacitance of the clock signal and the power consumption due to the flip-flop itself are large. In the second conventional example, the power consumption due to the load capacitance of the clock signal has been reduced, but the power consumption due to the flip-flop itself has increased.

An object of the present invention is to provide a method for reducing the number of transistors constituting a double edge trigger flip-flop and reducing the power consumption thereof by eliminating the above-mentioned disadvantages. .

[0036]

A feature of the present invention is that a first gate circuit for inputting a clock signal and a data signal;
A second gate circuit for inputting an output signal of the first gate circuit and the clock signal, a third gate circuit for inputting an inverted clock signal and the data signal, and an output of the third gate circuit A fourth gate circuit that inputs a signal and the inverted clock signal; and a two-input NAND that receives an output signal of the second gate circuit and an output signal of the fourth gate circuit. The output signal of the input NAND is a data output signal, and the first gate circuit and the third gate circuit are a first P-channel field-effect transistor, a second P-channel field-effect transistor, and a first N-channel. A first P-channel field-effect transistor and a first N-channel field-effect transistor connected in series between a power supply potential and a ground potential. The clock signal is input to the gate, the data signal is input to the gate of the second P-channel field-effect transistor, the second P-channel field-effect transistor and the first N-channel field-effect transistor An output signal is output from a connection point with the second gate circuit and the fourth gate circuit, and the second gate circuit and the fourth gate circuit are connected to a third P-channel type field effect transistor, a second N-channel type field effect transistor, and a third N-channel type. -Type field-effect transistor is connected in series between the power supply potential and the ground potential, and the gate of the third P-channel type field-effect transistor and the third N-channel type field-effect transistor is connected to the clock signal or the inverted clock. And the first gate circuit or the gate of the second N-channel type field effect transistor. The output signal of the third gate circuit is input, and an output signal is output from a connection point between the third P-channel field-effect transistor and the second N-channel field-effect transistor. It is in.

Another characteristic is that a first gate circuit for inputting a clock signal and a data signal, a second gate circuit for inputting an output signal of the first gate circuit and the clock signal, A third gate circuit for inputting a clock signal and the data signal; a fourth gate circuit for inputting an output signal of the third gate circuit and the inverted clock signal; and an output of the second gate circuit A two-input NOR for inputting a signal and an output signal of the fourth gate circuit, wherein the output signal of the two-input NOR is a data output signal, and the first gate circuit and the third gate circuit are A first P-channel field effect transistor and a first N
A channel type field effect transistor and a second N channel type field effect transistor are connected in series between a power supply potential and a ground potential, and the first P channel type field effect transistor and the second N channel type field effect transistor are connected to each other. The clock signal is input to the gate of the first N-channel field-effect transistor, and the data signal is input to the gate of the first N-channel field-effect transistor. An output signal is output from a connection point with the transistor, and the second gate circuit and the fourth gate circuit are connected to a second P-channel field-effect transistor, a third P-channel field-effect transistor, and a third N-channel field-effect transistor. A second P-channel field-effect transistor connected in series between the power supply potential and the ground potential; The clock signal or the inverted clock signal is input to the gates of the transistor and the third P-channel field-effect transistor, and the first gate circuit or the third gate is connected to the gate of the third P-channel field-effect transistor. And the output signal is output from a connection point between the third P-channel field-effect transistor and the third N-channel field-effect transistor.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The point of view of the present invention is to eliminate the inverters 36 and 37 of the second conventional example by using the clock input C and the inverted signal of the clock input C.

FIG. 1 shows a first embodiment of a double edge triggered flip-flop according to the present invention.

The data input (D) signal line 10, the clock input (C) signal line 11, the inverted (CB) signal line 12 of the clock signal C, and the inverted output (QB) signal line 1 of the data input D
3. Gates 21, 22, 23, 24 of a dynamic circuit composed of CMOS transistors, gates 21, 23 having a clock input on the P channel side, and dynamic inverters 22, 24 having a precharge potential of a high level. , NAND by CMOS static circuit
A gate 25 is provided.

The gates 21 and 22 constitute a D-type edge trigger flip-flop synchronized with the rising edge of the clock signal C.

This double edge trigger flip-flop comprises an output terminal of a gate 21 having a clock signal line 11 and a date signal line 10 connected to input terminals, and a clock signal line 1.
1 is connected to the input terminal of the gate 22, and the output terminal of the gate 22 is connected to one input terminal of the two-input NAND 25. The output terminal of the gate 23 where the inverted clock signal line 12 and the data signal line 10 are connected to the input terminals and the inverted clock signal line 12 are connected to the input terminal of the gate 24, and the output terminal of the gate 24 is connected to the two-input NAND 25. Connected to the other input terminal, the output signal line 13 of the two-input NAND 25 is configured as an inverted data output signal QB.

The gates 21 and 23 are connected between a power supply potential and a ground potential by a P-channel insulated gate field effect transistor (hereinafter referred to as a PMOS transistor, P ₁ , P ₂ and N).
Channel-type gate-effect transistor (hereinafter referred to as NM)
N ₁ ) are connected in series. PM
The gate of the OS transistor P ₁ to the input terminal of the clock input C or the inverted clock input CB, an input terminal of the data signal D by commonly connecting the gates of the PMOS transistor P ₁ and the NMOS transistor N _1. The signal output terminal is PMO
The connection point of the S transistor P ₂ and the NMOS transistor N _1.

The gate circuits 22 and 24 connect a PMOS transistor P ₃ and NMOS transistors N ₂ and N ₃ in series between a power supply potential and a ground potential. PMOS transistor P
₃ and the gate of the NMOS transistor N ₃ are connected in common to serve as an input terminal of a clock input C or an inverted clock input CB, and the gate of the NMOS transistor N ₂ serves as an input terminal of an output signal of the gate 21 or 23. The signal output terminal is PMO
The connection point of the S transistor P ₃ and the NMOS transistor N _2.

When the clock input C is at a low level,
Gate 21 operates as an inverter. Gate 22 is precharged to a high level.

Consider the case where the clock input C rises and goes high.

When the data input D is at a low level,
The gate 21 holds the previous value (high level) in the high impedance state, and the gate 22 outputs the low level.

If data input D is high,
Gate 21 goes low and gate 22 goes high.
The previous value (high level) is maintained in the impedance state.

The gates 23 and 24 have the same circuit configuration except that the clock input C of the gates 21 and 22 is changed to the inverted clock input CB.

FIG. 2 shows a timing chart of the operation of FIG.

Gates 22 and 24 are alternately precharged to a high level. Therefore, the NAND gate 25 is made to function as a selector.

It is assumed that the clock input C and the inverted clock input CB in FIG. 2 change at the same timing. Therefore, the inverted value of the data sampled at both the falling edge and the rising edge of the clock input C appears on the QB output line 13.

The features of this circuit are as follows: (1) The number of transistors is 16. (2) The power consumption due to the load capacity of the clock is Pc = f
× (6 × Cg) × (Vdd) ² . (3) The power consumption by the flip-flop itself is Pf =
(１ ／ × f) × (10 × Cg + 11 × Cd) × (Vd
d) ² . Here, f = clock frequency, Cg = gate capacitance, Cd = drain capacitance, and Vdd = power supply voltage. (4) f = 40 MHz, Cg = 0.010 pF, Cd =
Assuming 0.005 pF and Vdd = 5.0 V, Pc = 6
0 μW, Pf = 39 μW, Pc + Pf = 99 μW.

According to the present invention, a double edge trigger flip-flop can be formed with a small number of transistors, and power consumption is low.

Next, a second embodiment will be described.

FIG. 3 shows a hardware configuration of the second embodiment of the present invention. This circuit is obtained by exchanging the logic of the P-channel transistor and the logic of the N-channel transistor of the circuit of the first embodiment, and has the same function as that of the double edge trigger flip-flop of the first embodiment. It is. Therefore, the gate circuit 21 connects the PMOS transistor P ₃₁ and the NMOS transistors N ₃₁ and N ₃₂ in series between the power supply potential and the ground potential, and uses the NMOS transistor N ₃₁ as a clock signal or inverted clock signal input terminal. PM
And the data signal input to the gate of the OS transistor P ₃₁ and the NMOS transistor N ₃₂ are connected in common. Signal output terminal is configured as a connecting point of the PMOS transistor P ₃₁ and the NMOS transistor N _31.

The gates 27 and 29 connect the PMOS transistors P ₃₂ and P ₃₃ and the NMOS transistor N ₃₃ in series between the power supply potential and the ground potential. A clock signal input terminal of the gate of the PMOS transistor P ₃₂ and the NMOS transistor N ₃₃ and commonly connected to the gate of the PMOS transistor P ₃₃ and the input terminal of the gate 26 or 28. . Signal output terminal is configured as a connecting point of the PMOS transistor P _33.

The data input (D) signal line 10, the clock input (C) signal line 11, the inverted (CB) signal line 12 of the clock input C, and the inverted data (QB) signal line 13 of FIG.
Is the same as

Gates 26 to 30 of a dynamic circuit composed of CMOS transistors, gates 26 and 28 having a clock input on the N channel side, and a dynamic inverter 2 having a precharge potential of a low level.
7, 30, a NOR gate 30 using a CMOS static circuit.

The gates 26 and 27 constitute a D-type edge trigger flip-flop synchronized with the falling edge of the clock input C.

Consider the case where the clock input C falls and goes low.

When the data input D is at a high level,
The gate 26 holds the previous value (low level) in the high impedance state, and the gate 27 goes to the high level. If data input D is low, gate 2
6 becomes high level, and the gate 27 holds the previous value (low level) in the high impedance state.

The gates 28 and 29 have the same circuit configuration except that the clock input C of the gates 26 and 27 is changed to the inverted clock signal CB. That is, the gates 28 and 29
Constitutes a D-type edge trigger flip-flop synchronized with the falling edge of the inverted clock input CB.

Gates 27 and 29 are alternately precharged to a low level. Therefore, the NOR gate 30 functions as a selector. Therefore, the inverted value of the data sampled at both the falling edge and the rising edge of the clock input C appears on the QB output line 13.

The equations for the number of transistors and the power consumption in the second embodiment are the same as those in the first embodiment.

[0066]

From the above description, the number of transistors and the power consumption of the conventional example and the present invention are summarized as follows.

[0067]

[Table 1]

(F = 40 MHz, Cg = 0.010 p
(F, Cd = 0.005 pF, Vdd = 5.0 V) Therefore, the following effects can be obtained by using the present invention. (1) Less hardware.

The number of transistors is reduced to 80% of the conventional example.
Since the area on the LSI is almost proportional to the number of transistors, the area of the flip-flop is 80% of that of the conventional example. (2) Low power consumption.

77% of the first conventional example, 8% of the second conventional example
Only 7% power consumption is required.

According to the present invention, there is an effect that a double edge triggered flip-flop with low hardware cost and low power consumption can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a double edge triggered flip-flop according to a first embodiment.

FIG. 2 is a timing chart for explaining the first embodiment.

FIG. 3 is a circuit diagram of a double edge triggered flip-flop according to a second embodiment.

FIG. 4 is a circuit diagram of a first conventional double edge trigger flip-flop.

FIG. 5 is a timing chart for explaining a first conventional example.

FIG. 6 is a circuit diagram of a second conventional double edge trigger flip-flop.

[Explanation of symbols]

Reference Signs List 1 power supply potential 2 ground potential 10 data input (D) signal line 11 clock input (C) signal line 12 inverted clock input (CB) signal line 13 inverted data output (QB) signal line 14 data output (Q) signal line 21, 23, 34 Gate circuits 26, 28, 31, 32 with clock input on P channel side Gate circuits 22, 24 with clock input on N channel side Dynamic inverters 27, 29 with precharge potential at high level , 31 Dynamic inverter whose precharge potential is low level 30 Two-input NOR 35, 36, 37 inverter with CMOS static circuit 38 Two-input NAN with CMOS static circuit
D

Claims (2)

(57) [Claims] A first gate circuit for inputting a clock signal and a data signal; a second gate circuit for inputting an output signal of the first gate circuit and the clock signal;
A third gate circuit for inputting an inverted clock signal and the data signal; a fourth gate circuit for inputting the output signal of the third gate circuit and the inverted clock signal; A two-input NAND circuit for inputting an output signal and an output signal of the fourth gate circuit, wherein the output signal of the two-input NAND is used as a data output signal, and the first gate circuit and the third gate circuit Is the first P
A channel-type field effect transistor, a second P-channel type field-effect transistor, and a first N-channel type field-effect transistor connected in series between a power supply potential and a ground potential; First
Inputting the clock signal to the gate of the N-channel field-effect transistor, inputting the data signal to the gate of the second P-channel field-effect transistor, and inputting the data signal to the gate of the second P-channel field-effect transistor. First
An output signal is output from a connection point with the N-channel field-effect transistor, and the second gate circuit and the fourth gate circuit are connected to a third P-channel field-effect transistor and a second N-channel field-effect transistor. Transistor and third N
A channel type field effect transistor is connected in series between the power supply potential and the ground potential, and a gate of the third P channel type field effect transistor and a gate of the third N channel type field effect transistor have the clock signal or the inverted signal. A clock signal is input, and the output signal of the first gate circuit or the third gate circuit is input to a gate of the second N-channel field effect transistor, and the third P-channel field effect transistor is input. And the second N
Characterized in that an output signal is outputted from a connection point with a channel type field effect transistor.
Edge-triggered flip-flop. 2. A first gate circuit for inputting a clock signal and a data signal, a second gate circuit for inputting an output signal of the first gate circuit and the clock signal,
A third gate circuit for inputting an inverted clock signal and the data signal; a fourth gate circuit for inputting the output signal of the third gate circuit and the inverted clock signal; A two-input NOR for inputting an output signal and an output signal of the fourth gate circuit;
The output signal of the input NOR is used as a data output signal,
And the third gate circuit include a first P-channel field-effect transistor, a first N-channel field-effect transistor, and a second N-channel field-effect transistor connected in series between a power supply potential and a ground potential. Connecting the first P-channel field effect transistor and the second N
The clock signal is input to the gate of the channel-type field effect transistor, the data signal is input to the gate of the first N-channel field-effect transistor, and the first P-channel field-effect transistor and the first N
An output signal is output from a connection point with the channel-type field effect transistor, and the second gate circuit and the fourth gate circuit are connected to a second P-channel field-effect transistor and a third P-channel field-effect transistor. A third N-channel field-effect transistor is connected in series between the power supply potential and the ground potential, and the gates of the second P-channel field-effect transistor and the third P-channel field-effect transistor are A clock signal or an inverted clock signal is input, and the output signal of the first gate circuit or the third gate circuit is input to a gate of the third P-channel field-effect transistor, and the third P-channel field-effect transistor is input. An output signal is output from a connection point between the field-effect transistor and the third N-channel field-effect transistor. Double-edge-triggered flip-flop, characterized in that it was.