JPH10335992A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the operating speed of a logic integrated circuit device, which incorporates a flip flop and constitutes the cache memory of a superhigh- speed computer, etc., and decrease the power consumption of the device by preventing erroneous inversions of the flip flop due to α-ray noise, while the increase of the node capacity of a latch is being suppressed. SOLUTION: In a logic integrated circuit device, etc., constituting a cache memory, etc., of a superhigh-speed computer, a flip flop for holding data is constituted of inverters V3 and V4, etc., which are cross-connected to each other for constituting a main latch LT1 and an odd number of serially connected inverters V5-V7, which are cross-connected with the inverter V4 to constitute a sub-latch LT3 or the transmission delaying time of the sub-latch LT3 is made longer, by providing a capacitor between the output terminal of the inverter V5 and a grounding potential. At the same time, the drive ability of the inverter V7 is made higher than that of the inverter V3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a logic integrated circuit device which operates synchronously in accordance with a single-phase clock signal to constitute a high-speed cache memory, and a technique particularly effective for use in speeding up the logic integrated circuit device It is about.

[0002]

2. Description of the Related Art P-channel and N-channel MOSFs
There is a CMOS (complementary MOS) logic gate composed of an ET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is a general term for an insulated gate type field effect transistor). There is also a flip-flop including a latch in which CMOS logic gates are cross-coupled. There is a logic integrated circuit device including such a flip-flop as a register and constituting, for example, a cache memory of an ultra-high-speed computer.

On the other hand, there has been a remarkable progress in the technology for high integration and miniaturization of semiconductor integrated circuit devices in recent years. On the other hand, with miniaturization of MOSFETs, the capacity of latch input / output nodes has become smaller, A so-called soft error in which the retained data is inverted by α-rays emitted from a package material or the like has been viewed as a problem. Also, as one means for dealing with this, for example, a method of connecting a predetermined capacitor to the input / output node of the latch to increase the node capacitance, and preventing inversion of the latch even when spike noise due to α rays occurs. Has been adopted.

[0004]

Prior to the present invention, the present inventors attempted to develop a logic integrated circuit device which operates synchronously in accordance with a single-phase clock signal and constitutes a cache memory of an ultra-high-speed computer. Faced the problem. That is, the logic integrated circuit device includes a register for holding data, and flip-flops constituting each bit of the register are cross-coupled to each other via a transfer gate G2 as illustrated in FIG. Are used as the basic components. Inverting input / output node of latch LT1 including inverters V3 and V4 (here, input data D
The input / output node corresponding to the inverted signal of in is referred to as the inverted input / output node of the latch, and the input / output node corresponding to the non-inverted signal is referred to as the non-inverted input / output node. The same applies hereinafter) to the input data Din via the transfer gate G1.
Is supplied. The transfer gate G1 is selectively turned on in response to the high level of the non-inverted clock signal CKT, and the transfer gate G2 is selectively turned on in response to the high level of the inverted clock signal CKB.

As a result, the input data Din input from the preceding circuit (not shown) of the logic integrated circuit device receives the high level of the non-inverted clock signal CKT and receives the latch LT
1 and held by the latch LT1 while the inverted clock signal CKB is at a high level.
The level at the inverted input / output node na of the latch LT1 becomes the output signal Dout after passing through the inverter V2.

However, as the integration and miniaturization of integrated circuits advance and the node capacitance of the non-inverting input / output node na and the inverting input / output node nb of the latch LT1 decreases, the data held in the latch LT1 is inverted due to α-ray noise. However, the reliability of the logic integrated circuit device decreases. In order to cope with this, there is a method of adding the capacitor between each input / output node and the ground potential. However, the operation speed of the flip-flop is reduced due to an increase in the node capacitance due to the addition of the capacitor, and the flip-flop is connected to the register. As a result, the speed of the computer is hindered.

An object of the present invention is to realize a flip-flop capable of preventing erroneous inversion due to α-ray noise while suppressing an increase in node capacitance of a latch. It is another object of the present invention to increase the speed of a logic integrated circuit device or the like including a flip-flop and constituting a cache memory of an ultra-high-speed computer or the like.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a logic integrated circuit device constituting a cache memory or the like of an ultra-high-speed computer,
The first and second logic gates forming the first latch are substantially cross-coupled with the data holding flip-flop, and the second latch is substantially cross-coupled with the first logic gate. The third logic gate or the fourth logic gate which substantially cross-couples with the second logic gate to constitute the third latch is basically configured. Further, the third and fourth logic gates are constituted by an odd number of logic gates connected in series, or a capacitor is provided between the output terminal of the third or fourth logic gate and the ground potential, The substantial transmission delay time of the second and third latches is increased, and the driving capability of the third and fourth logic gates is made greater than that of the first and second logic gates.

According to the above-described means, even when α-ray noise is generated at the non-inverted or inverted input / output node of the first latch, it is absorbed by the transmission delay time of the second and third latches, and A decrease in the level of each node can be suppressed.
As a result, it is possible to prevent erroneous inversion of the flip-flop including the first latch while suppressing an increase in the node capacitance of the first latch, and to further promote high integration and miniaturization of the element correspondingly, thereby improving the operation of the flip-flop. By increasing the speed, it is possible to increase the speed of a logic integrated circuit device or the like including a flip-flop and constituting a cache memory of an ultra-high-speed computer or the like.

[0011]

FIG. 1 is a circuit diagram of a first embodiment of a flip-flop included in a logic integrated circuit device to which the present invention is applied, and FIG. 2 is a circuit diagram of the first embodiment. A signal waveform diagram is shown. The configuration, operation, and characteristics of the flip-flop of this embodiment will be described with reference to FIGS. The flip-flop of this embodiment is mounted on a logic integrated circuit device constituting a cache memory of an ultra-high-speed computer together with a large number of similar flip-flops not shown. Each circuit element in FIG.
Together with a number of circuit elements (not shown) of the logic integrated circuit device, they are formed on one semiconductor substrate such as single crystal silicon. In the following circuit diagram, the MOSFET with an arrow at the channel (back gate) portion is a P-channel type, and an N-channel MOS without an arrow is added.
It is shown separately from the FET.

In FIG. 1, the flip-flop of this embodiment includes an inverter V3 (first logic gate) comprising a P-channel MOSFET P1 and an N-channel MOSFET N1, and an inverter V4 (second inverter) comprising a P-channel MOSFET P2 and an N-channel MOSFET N2. Logic gate). These inverters are cross-coupled to each other via a transfer gate G2 to form a main latch LT1 (first latch) for holding data. Input data Din is supplied to the inverting input / output node na of the main latch LT1, that is, the input terminal of the inverter V3 from the preceding circuit (not shown) of the logic integrated circuit device via the inverter V1 and the transfer gate G1, and the inverting input / output node na, After being inverted by the inverter V2, the output signal of the inverter V4 is supplied as flip-flop output data Dout to a subsequent circuit (not shown) of the logic integrated circuit device.

Although not particularly limited, the inverter V1 is
Designed to have standard drive capability, inverter V2
Is designed to have a driving capacity about twice as large as that of the inverter V1. Further, the inverter V3 constituting the main latch LT1 is designed to have the same driving capability as the inverter V1, and the inverter V4 is designed to have a sufficiently small size and has, for example, a driving capability of about one third of the inverter V1. Only have. The transfer gate G1 is selectively turned on in response to the high level of the non-inverted clock signal CKT, and the transfer gate G2 is selectively turned on in response to the high level of the inverted clock signal CKB.

Here, the non-inverted clock signal CKT is not particularly limited, but as shown by a thick solid line in FIG.
Duty 1 that is repeatedly set to high level in a predetermined cycle
It is a single-phase clock signal of about 0%, and the inverted clock signal CKB is a complementary signal of the non-inverted clock signal CKT as shown by a thin solid line in FIG. The level of the input data Din changes just before the non-inverted clock signal CKT is set to the high level and the inverted clock signal CKB is set to the low level.

As a result, the input data Din supplied from the preceding circuit (not shown) of the logic integrated circuit device is selectively supplied to the main latch by the non-inverted clock signal CKT being set to the high level and the transfer gate G1 being turned on. The signal is transmitted to the inverted input / output node na of LT1. At this time, the inverted clock signal CKB is at the low level, and the transfer gate G2 is turned off. The inverter V3 is connected to the inverter V1 as described above.
And the inverter V4 has only about one third of the driving ability. Therefore, the data held in the main latch LT1 is rewritten at high speed in accordance with the logic level of the input data Din transmitted to the inverted input / output node na. The change in the level of the inverting input / output node na of the main latch LT1 is transmitted at a high speed to the output terminal of the flip-flop via the inverter V2 having a large driving capability, and the level of the output data Dout is changed at a high speed. When the non-inverted clock signal CKT is returned to a low level and the inverted clock signal CKB is changed to a high level, the main latch LT1 enters a data holding state, and holds the logic level of the immediately preceding input data Din.

The flip-flop of this embodiment is further substantially cross-coupled to an inverter V4 via a transfer gate G3 to thereby provide a sub-latch LT for countermeasures against α rays.
3 (third latch), and three inverters V5 to V5 acting as delay means by being connected in series.
V7 (fourth logic gate). Among them, the inverters V5 and V6 are designed to have a small driving capability like the inverter V4, and the inverter V7 has a driving capability larger than the inverters V3 and V4, that is, a driving capability approximately twice as large as that of the inverter V1, for example. Designed for The transfer gate G3 is selectively turned on in response to the high level of the inverted clock signal CKLB, and the inverted clock signal CKLB has a pulse slightly larger than the inverted clock signal CKB as shown by a thin solid line in FIG. Have a width.

As a result, the inverters V4 and V5
Sub-latch LT3 of the flip-flop consisting of
Captures the logical level of the input data Din at the non-inverting input / output node nb of the main latch LT1 when the inverted clock signal CKLB is at a low level, and holds the logic level while the inverted clock signal CKLB is at a high level. As described above, the inverter V7 is connected to the inverter V
3, the inverted clock signal CKLB has a pulse width larger than that of the inverted clock signal CKB, and the transfer gate G3 is turned on later than the transfer gate G2.
No contention issues arise.

By the way, as the integration and miniaturization of integrated circuits progress, MOSFET Ps constituting the main latch LT1
1 to P2, N1 to N2, and the like are also reduced in size, and the node capacitances at the inverting input / output node na and the non-inverting input / output node nb of the main latch LT1 are also decreasing. In addition, MOSFET P1 to P1
When α rays enter the diffusion layers 2 and N1 to N2,
As is well-known, an electron-hole pair is generated by the energy, and as shown by a thick dotted line in FIG. 2, the charge of these electrons or holes is received to invert an input / output node na or a non-inverted input / output node. The potential of nb rises or falls temporarily. Therefore, when the node capacitance of the inverting input / output node na and the non-inverting input / output node nb decreases, the data held in the main latch LT1 is inverted due to the α-ray noise,
A soft error results.

However, in the flip-flop of this embodiment, as described above, the sub-latch LT3 is formed by being substantially cross-coupled with one of the inverters V4 forming the main latch LT1, and the flip-flop has a series form which also functions as delay means. Inverters V5 to V7 are provided, of which inverter V7 has about twice the driving ability as compared to inverter V3 forming main latch LT1. For this reason,
Inverted clock signal CKB and inverted clock signal CKLB
Is at a high level and spike noise due to α rays occurs while both main latch LT1 and sub-latch LT3 are in a data holding state, the delay time of at least the delay means including inverters V5 to V7, that is, the transmission delay of sub-latch LT3. During the time corresponding to the time, the α-ray noise is absorbed by the large driving ability of the inverter V7. As a result, the logic level of the non-inverting input / output node nb of the main latch LT1 is held, and erroneous inversion of the main latch LT1 and the flip-flop including the same can be prevented.

As is apparent from the above description, by adding the sub-latch LT3 including the inverters V5 to V7, the capacitances of the inverting input / output node na and the non-inverting input / output node nb of the main latch LT1 do not largely change. The high-speed operation of the flip-flop including the main latch LT1 is maintained. In other words, when the present invention is adopted, α
It is possible to promote the miniaturization of the element without being restricted by the soft error due to the line and to reduce the voltage, and accordingly to increase the speed and power consumption of the logic integrated circuit device accordingly, A cache memory including a logic integrated circuit device, and thus a high-speed computer and the like can be operated at high speed and with low power consumption.

FIG. 3 is a circuit diagram showing a second embodiment of the flip-flop included in the logic integrated circuit device to which the present invention is applied. The flip-flop according to this embodiment basically follows the embodiment shown in FIGS. 1 and 2, and therefore, a description will be added only for parts different from this.

In FIG. 3, the flip-flop of this embodiment is a capacitor provided between the output terminal of inverter V5 (fourth logic gate) and the ground potential of the circuit instead of inverters V6 and V7 in FIG. C1 is included.

In this embodiment, the inverter V5 is
It is designed to have a driving capability about twice that of the inverter V3. The capacitor C1 is connected to the inverter V
5, and acts as delay means to delay the level change at the output terminal of the inverter V5 by a time corresponding to the time constant.

As a result, also in the case of this embodiment, FIG.
The same operation and effects as those of the embodiment can be obtained, whereby the speed and power consumption of the logic integrated circuit device can be increased, and the speed and power consumption of a cache memory including the logic integrated circuit device, and thus an ultra-high-speed computer can be increased. Can be achieved. Note that the capacitor C1 is used when the state of the main latch LT1 transitions, that is, the non-inverted clock signal CK.
T is set to a high level and inverted clock signals CKB and CK
While LB is at the low level, the main latch LT1 is disconnected from the non-inverting input / output node nb. Therefore, the provision of the capacitor C1 does not hinder the high-speed operation of the flip-flop.

FIG. 4 is a circuit diagram showing a third embodiment of the flip-flop included in the logic integrated circuit device to which the present invention is applied. The flip-flop according to this embodiment basically follows the embodiment shown in FIGS. 1 and 2, and therefore, a description will be added only for parts different from this.

Referring to FIG. 4, the flip-flop of this embodiment includes a main latch LT1 and a sub-latch LT shown in FIG.
In addition to the three inverters V8, which are substantially cross-coupled with the inverter V3 (first logic gate) of the main latch LT1 to form another sub-latch LT2 (second latch) for countermeasures against α rays. To VA (third logic gate). Among them, the inverters V8 and V9 are designed to have a relatively small driving ability similar to the inverter V4, and the inverter VA is designed to have a driving ability about twice as large as that of the inverter V3.

From these, the sub-latch LT2 including the inverters V3 and V8 to VA is connected to the sub-latch L with respect to the inverting input / output node na of the main latch LT1.
Acts similarly and complementarily to T3, and prevents erroneous inversion due to α-ray noise with its transmission delay time. As a result, also in this embodiment, the same operation and effect as those of the embodiment of FIG. 1 can be obtained, whereby the speed and power consumption of the logic integrated circuit device can be increased, and the cache including the logic integrated circuit device can be obtained. It is possible to increase the speed and reduce the power consumption of a memory and ultimately an ultra-high-speed computer.

FIG. 5 is a circuit diagram showing a fourth embodiment of the flip-flop included in the logic integrated circuit device to which the present invention is applied. The flip-flop according to this embodiment basically follows the embodiment shown in FIGS. 1 and 2, and therefore, a description will be added only for parts different from this.

In FIG. 5, the flip-flop of this embodiment is substantially cross-coupled to inverter V3 via transfer gates G2, G6 and G5 in addition to main latch LT1 including inverters V3 and V4. Inverter VC (third logic gate) constituting sub-latch LT5 (second latch) and transfer gates G6, G5 and G with respect to inverter V4.
2 are substantially cross-coupled through sub-latch LT6.
(Third latch) and an inverter VB (fourth logic gate). These inverters VB and VC
Are latched by being directly cross-coupled to each other. Further, the inverter VB further includes a P-channel MO
The inverter VC is cross-coupled with an inverter VD composed of an SFET3 and an N-channel MOSFET N3 to form a latch. The inverter VC further includes a P-channel MOSFET.
A latch mode is obtained by cross-coupled with an inverter VE composed of T4 and an N-channel MOSFET N4.
These inverters VD and VE are directly cross-coupled to each other to form a latch.

In this embodiment, the inverters VB and VC are designed to have about twice the driving ability as compared to the inverter V3 of the main latch LT1. Further, the transfer gates G5 and G6 are selectively turned on in response to the high level of the inverted clock signal CKLB having a pulse width larger than the inverted clock signal CKB. Further, inverters V3 to V4 and VB
The VEs function as delay means by being formed in a latch form in a different combination, and their holding ability is also enhanced. As a result, also in this embodiment, the same operation and effect as those of the embodiment of FIG. 1 can be obtained, whereby the speed and power consumption of the logic integrated circuit device can be increased, and the cache including the logic integrated circuit device can be obtained. This makes it possible to increase the speed and reduce the power consumption of a memory and ultimately an ultra-high-speed computer.

FIG. 6 is a circuit diagram of a fifth embodiment of a flip-flop included in a logic integrated circuit device to which the present invention is applied. The flip-flop according to this embodiment basically follows the embodiment shown in FIGS. 1 and 2, and therefore, a description will be added only for parts different from this.

Referring to FIG. 6, the flip-flop of this embodiment includes P-channel MOSFETs P5 and N in addition to a main latch LT1 comprising inverters V3 and V4.
A single input gate type inverter VF (third logic gate) composed of a channel MOSFET N5, a P-channel MOSFET P6 and an N-channel MOSFET N6
And a single input gate type inverter VG (fourth logic gate). Inverters VF and VG are directly cross-coupled to each other via their N-channel MOSFETs N5 and N6, and are in a latch form. The inverter VF is composed of a paired inverter VG and a P-channel M
The sub-latch LT7 (third latch) is substantially cross-coupled to the inverter V3 of the main latch LT1 via an inverter VH including an OSFET P7 and an N-channel MOSFET N7 and a transfer gate G7, and the inverter VG is a pair of inverters VF And P
Channel MOSFETP8 and N-channel MOSFET
Sub-latch LT8 (fourth latch) is formed by being substantially cross-coupled to inverter V4 via inverter VI including ETN8 and transfer gate G8.

In this embodiment, the transfer gates G7 and G8 are selectively turned on in response to the high level of the inverted clock signal CKLB having a pulse width larger than the inverted clock signal CKB. Inverter VF is cross-coupled with inverter VI via transfer gate G8 to form a latch, and inverter VG is cross-coupled with inverter VH via transfer gate G7 to form a latch. further,
Inverters V3 to V4 and VF to VI are each configured as a latch in a different combination to act as a delay unit, and the holding capacity thereof is also increased. As a result, also in this embodiment, the same operation and effect as those of the embodiment of FIG. 1 can be obtained, whereby the speed and power consumption of the logic integrated circuit device can be increased, and the cache including the logic integrated circuit device can be obtained. This makes it possible to increase the speed and reduce the power consumption of a memory and ultimately an ultra-high-speed computer.

In the case of this embodiment, the number of required elements can be reduced in spite of the complicated latch connection, so that the required layout area of the flip-flop is reduced, and the cost of the dynamic RAM is reduced. Is achieved.

The operational effects obtained from the above embodiment are as follows. That is, (1) In a logic integrated circuit device or the like constituting a cache memory or the like of an ultra-high-speed computer, the first and second flip-flops for holding data are substantially cross-coupled to constitute a first latch. A logic gate and a third logic gate substantially cross-coupled to the first logic gate to form a second latch, or a third latch substantially cross-coupled to the second logic gate to form a third latch And a fourth logic gate. Further, the third and fourth logic gates are constituted by an odd number of logic gates coupled in series, or a capacitor is provided between the output terminal of the third or fourth logic gate and the ground potential, The substantial transmission delay time of the second and third latches is increased, and the substantial driving capability of the third and fourth logic gates is made greater than that of the first and second logic gates. As a result, α is applied to the non-inverted or inverted
Even if the line noise occurs, the line noise can be absorbed by the transmission delay time of the second and third latches, and the effect of preventing the level inversion of the non-inversion or inversion input / output node can be obtained.

(2) According to the above item (1), an effect is obtained that erroneous inversion of the flip-flop including the first latch can be prevented while suppressing an increase in the node capacitance of the first latch. (3) According to the above items (1) and (2), the integration and miniaturization of the element are further promoted, the operation of the flip-flop is accelerated, and the cache of the ultra-high-speed computer including the flip-flop is used. This has the effect of increasing the speed and lowering the power consumption of the logic integrated circuit device and the like constituting the memory.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIGS. 1 and 4, the inverters V5 to V7 and V8 to VA serving as delay means can be constituted by an arbitrary number of inverters. Further, in the embodiment of FIG. 3, the capacitor C1 serving as the delay means can be replaced with a plurality of capacitors arranged in parallel. In each embodiment, each inverter including the inverters V3 and V4 of the main latch LT1 is, for example, a multi-input NAND (NAN).
D) Various logic gates such as gates can be used, and various embodiments can be adopted for the specific configuration of the flip-flop, the polarity of the power supply voltage, and the conductivity type of the MOSFET.

In FIG. 2, the specific time relationship among input data Din, non-inverted clock signal CKT, inverted clock signal CKB and inverted clock signal CKLB does not affect the gist of the present invention. The duty of the clock signal can also be set arbitrarily. Further, in the present embodiment, the logic integrated circuit device is operated synchronously according to a single-phase clock signal, but may be operated synchronously according to a plurality of phase clock signals.

In the above description, mainly the case where the invention made by the present inventor is applied to a logic integrated circuit device constituting a cache memory of an ultra-high-speed computer, which is a field of application as a background, has been described. For example, the present invention can be widely applied to various semiconductor integrated circuit devices including similar flip-flops or latches and devices or systems including the same.

[0040]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a logic integrated circuit device or the like constituting a cache memory or the like of an ultra-high speed computer, a flip-flop for holding data is substantially cross-coupled with first and second logic gates constituting a first latch. A third logic gate substantially cross-coupled with the first logic gate to form a second latch, or a fourth logic gate substantially cross-coupled to the second logic gate to form a third latch Logic gates. Further, the third and fourth logic gates are constituted by an odd number of logic gates coupled in series, or a capacitor is provided between the output terminal of the third or fourth logic gate and the ground potential, The substantial transmission delay time of the second and third latches is increased, and the driving capability of the third and fourth logic gates is made larger than that of the first and second logic gates. Thereby, even when α-ray noise occurs at the non-inverted or inverted input / output node of the first latch, the second latch
This is absorbed by the transmission delay time of the third latch and the level inversion of each node is prevented. As a result, it is possible to prevent erroneous inversion of the flip-flop including the first latch while suppressing an increase in the node capacitance of the first latch, and to further promote high integration and miniaturization of the element correspondingly, thereby improving the operation of the flip-flop. By increasing the speed, it is possible to increase the speed and reduce the power consumption of a logic integrated circuit device or the like that constitutes a cache memory such as an ultra-high-speed computer including a flip-flop.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a flip-flop included in a logic integrated circuit device to which the present invention is applied.

FIG. 2 is a signal waveform diagram showing one embodiment of the flip-flop of FIG. 1;

FIG. 3 is a circuit diagram showing a second embodiment of the flip-flop included in the logic integrated circuit device to which the present invention is applied;

FIG. 4 is a circuit diagram showing a third embodiment of a flip-flop included in a logic integrated circuit device to which the present invention has been applied.

FIG. 5 is a circuit diagram showing a fourth embodiment of a flip-flop included in a logic integrated circuit device to which the present invention is applied.

FIG. 6 is a circuit diagram showing a fifth embodiment of a flip-flop included in a logic integrated circuit device to which the present invention has been applied.

FIG. 7 is a circuit diagram showing an example of a flip-flop included in a logic integrated circuit device developed by the present inventors prior to the present invention.

[Explanation of symbols]

Din: input data, Dout: output data, CK
T: Non-inverted clock signal, CKB, CKLB: Inverted clock signal. LT1 ... Main latch, LT2 to LT
8 ... sub-latch, V1-VI ... inverter, G1-
G8 transfer gate, P1 to P8 P channel MOSFET, N1 to N8 N channel MOS
FET, C1 ... capacitor, na ... inverting input / output node, nb ... non-inverting input / output node.

Claims (6)

[Claims] 1. A first latch and a second logic gate which are substantially cross-coupled to form a first latch, and a second latch which is substantially cross-coupled to the first logic gate. A semiconductor integrated circuit device comprising: a flip-flop including a third logic gate or a fourth logic gate substantially cross-coupled with the second logic gate to form a third latch. . 2. The semiconductor integrated circuit device according to claim 1, wherein said second and third latches include delay means for increasing a transmission delay time. 3. The semiconductor integrated circuit device according to claim 2, wherein said delay means includes an odd number of logic gates which are connected in series and substantially become said third or fourth logic gates. 4. The circuit according to claim 2, wherein said delay means is provided between an output terminal of said third or fourth logic gate and a ground potential of a circuit, and said input node is provided when said first latch changes state. A semiconductor integrated circuit device including a capacitor separated from the semiconductor integrated circuit. 5. The logic circuit according to claim 1, wherein the third and fourth logic gates or the odd number of logic gates serving as the third or fourth logic gates are provided. A semiconductor integrated circuit device, wherein the logic gate provided at the last stage is designed to have a larger driving ability than the first and second logic gates. 6. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a logic integrated circuit device that operates synchronously in accordance with a single-phase clock signal. A semiconductor integrated circuit device characterized by the above-mentioned.