JPH03117020A - Output buffer circuit for integrated circuit - Google Patents
Output buffer circuit for integrated circuitInfo
- Publication number
- JPH03117020A JPH03117020A JP1254275A JP25427589A JPH03117020A JP H03117020 A JPH03117020 A JP H03117020A JP 1254275 A JP1254275 A JP 1254275A JP 25427589 A JP25427589 A JP 25427589A JP H03117020 A JPH03117020 A JP H03117020A
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- Prior art keywords
- output
- output unit
- circuit
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- 230000000295 complement effect Effects 0.000 claims description 2
- 238000005265 energy consumption Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 11
- MZAGXDHQGXUDDX-JSRXJHBZSA-N (e,2z)-4-ethyl-2-hydroxyimino-5-nitrohex-3-enamide Chemical compound [O-][N+](=O)C(C)C(/CC)=C/C(=N/O)/C(N)=O MZAGXDHQGXUDDX-JSRXJHBZSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
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- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
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- Logic Circuits (AREA)
- Dram (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路の出カバ・７７７回路に関し、特にＭ
Ｏ８集積回路の出力回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an output cover/777 circuit of an integrated circuit, and in particular to an M
This invention relates to an output circuit of an O8 integrated circuit.
従来のこの種の出力バッファ回路について図面を参照し
そ説明する。第４図は従来の出カッく・ンファ回路の回
路図で、第５図はレイアウト図である。この種の出力バ
ッファ回路では、入力信号１が′Ｈ°゛のとき、インバ
ータ１１の出力がＩＩ Ｌ ＩＩとなり、ｐＭＯＳトラ
ンジスタＭ ｐ １をオン、ｎ Ｍ ＯＳ ）ランジメ
タＭｎ工をオフすることにより、゛′Ｈルベルを出力す
る。また、入力信号がＩＩ Ｌ ＩＩのときは、インバ
ータ出力が”Ｈ”となるため、ｐＭＯＳトランジスタＭ
ｐ １がオフ、ｎＭ○ＳトランジスタＭｎｌがオンと
なり“′Ｌ′°レベルを出力する。A conventional output buffer circuit of this type will be explained with reference to the drawings. FIG. 4 is a circuit diagram of a conventional output/input amplifier circuit, and FIG. 5 is a layout diagram. In this type of output buffer circuit, when the input signal 1 is 'H°', the output of the inverter 11 becomes II L II, and by turning on the pMOS transistor Mp1 and turning off the range metal Mn (nMOS),゛′H level is output. Also, when the input signal is II L II, the inverter output becomes "H", so the pMOS transistor M
p1 is turned off, and the nM○S transistor Mnl is turned on, outputting the "'L'° level.
またこの回路のレイアウトの概略は第５図のようになる
。従って“Ｈ”を出力するときの電流能力はｐＭＯＳト
ランジスタＭｐ１のゲート幅で、“Ｌ ”を出力すると
きの電流能力は、ｎＭＯ３）ランジスタのＭｎ１のゲー
ト幅で決定される。The layout of this circuit is schematically shown in FIG. Therefore, the current capability when outputting "H" is determined by the gate width of the pMOS transistor Mp1, and the current capability when outputting "L" is determined by the gate width of Mn1 of the nMO3) transistor.
上述した従来の出力バッファ回路では、出力電流が回路
設計時に決定され、変化させることができないため、異
なる外部負荷それぞれに対し最適な電流を供給すること
ができないため、集積回路の動作速度などの特性又は消
費電力の少なくとも一方を犠牲にしなければならないと
いう欠点がある。In the conventional output buffer circuits mentioned above, the output current is determined at the time of circuit design and cannot be changed, so it is not possible to supply the optimal current for each different external load, which affects characteristics such as the operating speed of the integrated circuit. However, there is a drawback that at least one of power consumption must be sacrificed.
本発明の集積回路の出力バッファ回路は、相補型インバ
ータからなる第１の出力ユニットと、前記第１の出力ユ
ニットと並列に設けられ、ｐＭ。The output buffer circuit of the integrated circuit of the present invention includes a first output unit consisting of a complementary inverter, and is provided in parallel with the first output unit, and has a pM.
Ｓトランジスタ及びｎＭＯＳトランジスタの直列接続構
成を含む第２の出力ユニットと、制御信号の論理レベル
に応じて入力信号を反転して前記ｐＭＯＳトランジスタ
及びｎＭＯＳトランジスタのゲートに印加するか又は前
記第２の出力ユニットをハイインピーダンス状態にする
信号を発生する制御回路とを有するというものである。a second output unit including a series connection configuration of an S transistor and an nMOS transistor; and a second output unit that inverts an input signal and applies it to the gates of the pMOS transistor and nMOS transistor depending on the logic level of the control signal; The device also includes a control circuit that generates a signal that puts the unit in a high impedance state.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の回路図である。FIG. 1 is a circuit diagram of a first embodiment of the present invention.
この実施例はＣＭＯＳインバータからなる第１の出力ユ
ニット４１と、第１の出力ユニット４１と並列に設けら
れ、ｐＭＯＳトランジスタＭ Ｐ ２及びｎ Ｍ ＯＳ
）ランジスタＭｎ２の直列接続構成を含む第２の出力
ユニット４２と、制御信号の論理レベルに応じて入力信
号を反転して９ＭＯ８）ランジスタＭ ］） ２及びｎ
ＭＯ３）ランジスタＭｎ２のゲートに印加するか又は第
２の出力ユニット４２をハイインピータンス状態にする
信号を発生する制御回路３とを有するというものである
。In this embodiment, a first output unit 41 consisting of a CMOS inverter is provided in parallel with the first output unit 41, and pMOS transistors M P 2 and n MOS transistors are provided.
) a second output unit 42 comprising a series connection configuration of transistors Mn2 and inverting the input signal depending on the logic level of the control signal 9MO8) transistors M ]) 2 and n
MO3) The control circuit 3 generates a signal to be applied to the gate of the transistor Mn2 or to bring the second output unit 42 into a high impedance state.
第３の出力ユニット４３は第２の出力ユニット４２と同
一構成を有している。制御回路は否定論理積ゲートＮＡ
ＮＤ１ 、・・・と否定論理和ゲートＮ。The third output unit 43 has the same configuration as the second output unit 42. The control circuit is a NAND gate NA
ND1, . . . and a negative OR gate N.
Ｒ１、・・・よりなり、入力信号端１はＮＡＮＤ １゜
ＮＡＮＤ２．Ｎ０ＲＩ、Ｎ０Ｒ２に接続され、第１の制
御信号端２１はそのままＮＡＮＤ １に又インバータを
介してＮ０ＲＩに接続されている。R1, . . . and the input signal end 1 is NAND 1°NAND2. The first control signal end 21 is directly connected to NAND 1 and to N0RI via an inverter.
次にこの実施例の動作について説明する。Next, the operation of this embodiment will be explained.
この回路では制御信号が“Ｌ”（例えば制御信号端を接
地端に接続すればよい）のとき出力ユニットの９ＭＯ８
）ランジスタに接続された制御回路中の２人力否定論理
積ゲートは” Ｈ”を出力し、出力ユニットのｎＭＯＳ
トランジスタに接続された制御回路中の２人力否定論理
ゲートは” Ｌ ”を出力する。従って、トランジスタ
・ペアで構成される出力ユニットはハイインピーダンス
状態となる。また、制御信号が“Ｈ′° （制御信号端
を電源端に接続すればよい）のとき、第２、第３の出力
ユニットのトランジスタには入力信号の反転信号が入力
され、それらの出力ユニットからは入力信号に従った出
力信号を出力する。In this circuit, when the control signal is "L" (for example, the control signal terminal should be connected to the ground terminal), the output unit 9MO8
) The two-manual NAND gate in the control circuit connected to the transistor outputs "H", and the nMOS of the output unit
A two-way negative logic gate in the control circuit connected to the transistor outputs "L". Therefore, the output unit consisting of the transistor pair is in a high impedance state. Furthermore, when the control signal is "H'°" (the control signal end should be connected to the power supply end), the inverted signal of the input signal is input to the transistors of the second and third output units, and these output units outputs an output signal according to the input signal.
従って第２、第３の出力ユニットはそれぞれに対応した
第１、第２の制御信号がＨ”のときに限り入力信号に従
った出力を出し、ＩＩ Ｌ Ｉｌのときはハイインピー
ダンス状態となる。Therefore, the second and third output units output an output according to the input signal only when the corresponding first and second control signals are H'', and enter a high impedance state when II L Il.
一
次に、第１図の出力回路をレイアウト図に置きかえた図
を第２図に示す。この図では例として制御信号は２本と
する。First, FIG. 2 shows a diagram in which the output circuit in FIG. 1 is replaced with a layout diagram. In this figure, two control signals are used as an example.
この場合第１、第２の制御信号端２１．２２の電位がＨ
”の場合、制御回路３を介して、入力信号の反転信号が
それぞれの出力ユニットに入力される。このとき、外部
から内部を見込んだインピーダンスは各トランジスタの
ゲート幅の和で決定される。一方、ｎ Ｍ ＯＳ ）ラ
ンジスタＭｎ３のゲート電極ＧＰ３には“Ｈ″’ 、ｎ
ＭＯＳトランジスタＭｎ３のゲート電極Ｇｎ３にはＬ°
”が入力される。従ってこのときの外部から見込んだイ
ンピーダンスは、第１の出力ユニット４１、第２の出力
ユニット４２のトランジスタのゲート幅の相で決定され
、第２の制御信号がＩｌ、 Ｈ”′の場合よりも大きく
なり、消費電流を小さくすることができる。In this case, the potential of the first and second control signal terminals 21.22 is H.
”, an inverted signal of the input signal is input to each output unit via the control circuit 3. At this time, the impedance looking inside from the outside is determined by the sum of the gate widths of each transistor. , n MOS) "H"', n to the gate electrode GP3 of the transistor Mn3.
L° is applied to the gate electrode Gn3 of the MOS transistor Mn3.
" is input. Therefore, the impedance seen from the outside at this time is determined by the phase of the gate width of the transistors of the first output unit 41 and the second output unit 42, and the second control signal is Il, H This is larger than in the case of ``'', and the current consumption can be reduced.
このように、この実施例の場合、出力バッファ回路の電
流能力を３通りに設定可能である。In this way, in this embodiment, the current capacity of the output buffer circuit can be set in three ways.
第３図は本発明の第２の実施例の回路図である。FIG. 3 is a circuit diagram of a second embodiment of the present invention.
この実施例では制御信号を出力端５から取っている。制
御回路２は、２人力否定論理積ゲートＮＡＮＤ３．２人
力否定論理和ゲートＮＯＲ３、インバータＩ２よりなっ
ている。In this embodiment, the control signal is taken from the output terminal 5. The control circuit 2 is composed of two manually operated NAND gates NAND3, two manually operated NOR gates NOR3, and an inverter I2.
本実施例では、入力信号（１）と出力信号（５）が一致
しているとき、第２の出力ユニット４２はハイインピー
ダンス状態となり、消費電流は第１の出力ユニット４１
を構成するトランジスタのゲート幅だけで決まる。一方
過渡状態において、入力信号がＩＩ ＨＩＩ、出力信号
がＬ“のときは第１の出力ユニット４１、第２の出力ユ
ニット４２の両方のｐＭＯＳトランジスタがＯＮＬ、入
力信号が“’Ｌ”、出力信号が“Ｈ”のときは第１の出
力ユニット４１、第２の出力ユニット４２の両方の０Ｍ
Ｏ３）ランジスタがＯＮする。In this embodiment, when the input signal (1) and the output signal (5) match, the second output unit 42 is in a high impedance state, and the current consumption is lower than that of the first output unit 41.
It is determined only by the gate width of the transistors that make up the circuit. On the other hand, in a transient state, when the input signal is II HII and the output signal is L, both the PMOS transistors of the first output unit 41 and the second output unit 42 are ONL, the input signal is "'L", and the output signal is is “H”, both the first output unit 41 and the second output unit 42 are 0M.
O3) The transistor turns on.
従って入力信号と出力信号が一致していないときは、第
１の出力ユニットを構成するトランジスタのゲート幅と
第２の出力ユニットを構成するトランジスタのゲート幅
の和で、電流能力が決定され、第１の出力ユニットだけ
で決まるときよりもその能力が向上する。言い替えると
、信号の立上り又は立下りの過渡状態において電流能力
が大きくなるので、動作速度が速い割には消費電力は小
さい出力バッファ回路が得られる。Therefore, when the input signal and the output signal do not match, the current capacity is determined by the sum of the gate width of the transistor that makes up the first output unit and the gate width of the transistor that makes up the second output unit. Its ability is improved compared to when it is determined by only one output unit. In other words, since the current capacity increases in the transient state of rising or falling signals, an output buffer circuit that operates at high speed but consumes little power can be obtained.
以上説明したように本発明は、複数の出力ユニットを並
列に設け、制御信号により前述の出力ユニットのうちい
くつかをハイインピーダンス状態にすることにより、出
力バッファ回路の電流能力を選択することができるので
集積回路の特性向上又は消費電力の低減化を図ることか
できる効果がある。As explained above, in the present invention, the current capacity of the output buffer circuit can be selected by providing a plurality of output units in parallel and placing some of the output units in a high impedance state using a control signal. Therefore, there is an effect that the characteristics of the integrated circuit can be improved or the power consumption can be reduced.
第１図は本発明の第１の実施例の回路図、第２図は第１
の実施例のレイアウト図、第３図は本発明の第２の実施
例の回路図、第４図は従来例の回路図、第５図は従来例
のレイアウト図である。
１・・・入力信号、２１・・・第１の制御信号端、２２
・・・第２の制御信号端、３・・・制御回路、４・・・
出力回路、４１・・・第１の出力ユニット、４２・・・
第２の出力ユニット、４３・・・第３の出力ユニット、
５・・・出力信号端、Ｄｎ・・・ｎＭＯＳトランジスタ
のドレイン、ＤＰ・・・９ＭＯ８）ランジスタのトレイ
ン電極、Ｇｎｌ、Ｇｎ２．Ｇｎ３−・−ｎＭＯＳトラン
ジスタのゲート電極、ＧＮＤ・・・接地配線、ＧＰＩ。
ＧＰ２．ＧＰ３・・・９ＭＯ８）ランジスタのゲート電
極、■１・・・インバータ、ＮＡＮＤ １〜ＮＡＮＤ３
・・・否定論理積ゲート、Ｎ０ＲＩ〜ＮＯＲ３・・・否
定論理和ゲート、Ｍｎ１ 、Ｍｎ２ 、Ｍｎｇ −・ｎ
Ｍ○Ｓトランジスタ、Ｍｐ、、Ｍｐ２．Ｍｐ、・・・９
ＭＯ８）ランジスタ、Ｐ・・・パッド（出力信号端）、
Ｓｎ・・・ｎＭＯＳトランジスタのソース電極、ＳＰ・
・・９ＭＯ８）ランジスタのソース電極、ｖｃｃ・・・
電源配線。FIG. 1 is a circuit diagram of a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a first embodiment of the present invention.
FIG. 3 is a circuit diagram of the second embodiment of the present invention, FIG. 4 is a circuit diagram of a conventional example, and FIG. 5 is a layout diagram of a conventional example. 1... Input signal, 21... First control signal end, 22
...Second control signal end, 3...Control circuit, 4...
Output circuit, 41... first output unit, 42...
second output unit, 43... third output unit,
5... Output signal terminal, Dn... Drain of nMOS transistor, DP...9MO8) Train electrode of transistor, Gnl, Gn2. Gn3-.-nMOS transistor gate electrode, GND...ground wiring, GPI. GP2. GP3...9MO8) Gate electrode of transistor, ■1... Inverter, NAND 1 to NAND3
...NOR gate, N0RI~NOR3...NOR gate, Mn1, Mn2, Mng -・n
M○S transistor, Mp, , Mp2. Mp...9
MO8) transistor, P... pad (output signal end),
Sn... Source electrode of nMOS transistor, SP
...9MO8) Source electrode of transistor, vcc...
Power wiring.
Claims (2)
、前記第１の出力ユニットと並列に設けられ、ｐＭＯＳ
トランジスタ及びｎＭＯＳトランジスタの直列接続構成
を含む第２の出力ユニットと、制御信号の論理レベルに
応じて入力信号を反転して前記ｐＭＯＳトランジスタ及
びｎＭＯＳトランジスタのゲートに印加するか、又は前
記第２の出力ユニットをハイインピーダンス状態にする
信号を発生する制御回路とを有することを特徴とする集
積回路の出力バッファ回路。(1) A first output unit consisting of a complementary inverter, provided in parallel with the first output unit, and a pMOS
a second output unit including a series connection configuration of a transistor and an nMOS transistor; and an input signal inverted depending on a logic level of a control signal and applied to the gates of the pMOS transistor and nMOS transistor, or the second output unit; 1. An output buffer circuit for an integrated circuit, comprising: a control circuit that generates a signal that puts the unit in a high impedance state.
記載の集積回路の出力バッファ回路。(2) Claim (1) in which the output signal is used as a control signal
Output buffer circuit of the integrated circuit described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1254275A JPH03117020A (en) | 1989-09-28 | 1989-09-28 | Output buffer circuit for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1254275A JPH03117020A (en) | 1989-09-28 | 1989-09-28 | Output buffer circuit for integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03117020A true JPH03117020A (en) | 1991-05-17 |
Family
ID=17262708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1254275A Pending JPH03117020A (en) | 1989-09-28 | 1989-09-28 | Output buffer circuit for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03117020A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0520687A1 (en) * | 1991-06-28 | 1992-12-30 | AT&T Corp. | Digitally controlled element sizing |
| EP0523833A1 (en) * | 1991-07-16 | 1993-01-20 | Samsung Semiconductor, Inc. | Programmable output drive circuit |
| EP0608615A2 (en) * | 1993-01-29 | 1994-08-03 | Advanced Micro Devices, Inc. | Clock driver circuits |
| EP0717501A1 (en) * | 1994-12-15 | 1996-06-19 | Advanced Micro Devices, Inc. | Programmable drive buffer |
| US5742832A (en) * | 1996-02-09 | 1998-04-21 | Advanced Micro Devices | Computer system with programmable driver output's strengths responsive to control signal matching preassigned address range |
| WO1998047230A1 (en) * | 1997-04-11 | 1998-10-22 | Xilinx, Inc. | Input/output buffer supporting multiple i/o standards |
| JPH10308096A (en) * | 1997-04-30 | 1998-11-17 | Samsung Electron Co Ltd | Operation period adaptive type data output buffer |
| US5877632A (en) * | 1997-04-11 | 1999-03-02 | Xilinx, Inc. | FPGA with a plurality of I/O voltage levels |
| EP0913937A2 (en) * | 1997-10-29 | 1999-05-06 | Hewlett-Packard Company | Clock driver apparatus with programmable output characteristics |
| US5991908A (en) * | 1997-09-29 | 1999-11-23 | Xilinx, Inc. | Boundary scan chain with dedicated programmable routing |
| US6071314A (en) * | 1997-09-29 | 2000-06-06 | Xilinx, Inc. | Programmable I/O cell with dual boundary scan |
| US6120551A (en) * | 1997-09-29 | 2000-09-19 | Xilinx, Inc. | Hardwire logic device emulating an FPGA |
| US6625788B1 (en) | 1998-06-26 | 2003-09-23 | Xilinx, Inc. | Method for verifying timing in a hard-wired IC device modeled from an FPGA |
-
1989
- 1989-09-28 JP JP1254275A patent/JPH03117020A/en active Pending
Cited By (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0520687A1 (en) * | 1991-06-28 | 1992-12-30 | AT&T Corp. | Digitally controlled element sizing |
| EP0523833A1 (en) * | 1991-07-16 | 1993-01-20 | Samsung Semiconductor, Inc. | Programmable output drive circuit |
| US5319258A (en) * | 1991-07-16 | 1994-06-07 | Samsung Semiconductor, Inc. | Programmable output drive circuit |
| EP0608615A2 (en) * | 1993-01-29 | 1994-08-03 | Advanced Micro Devices, Inc. | Clock driver circuits |
| EP0608615A3 (en) * | 1993-01-29 | 1995-01-25 | Advanced Micro Devices Inc | Clock driver circuits. |
| EP0717501A1 (en) * | 1994-12-15 | 1996-06-19 | Advanced Micro Devices, Inc. | Programmable drive buffer |
| US5663664A (en) * | 1994-12-15 | 1997-09-02 | Advanced Micro Devices, Inc. | Programmable drive strength output buffer with slew rate control |
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