JPH04127466A - Complementary mos output circuit - Google Patents

Abstract

PURPOSE:To gradually turn on transistors to suppress the occurrence of glitch caused by a transient current flowing to a power source by making a constant current to flow for turning on the first or second transistor by means of a constant-current source and a current miller circuit and charging and discharging a capacity with this constant current. CONSTITUTION:The sources of transistors P1 and N1 are respectively connected to power sources VCC and VSS and the commonly connected drain of the transistors P1 and N1 is connected not only to an output terminals 25, but also to the input terminal of an inverter 26. The output of the inverter 26 is supplied to the gate of a transistor P3. The gate and drain of the transistor N1 are connected to each other through a capacity C1. When data inputted to a terminal 20 change in level from a high level to a low level, the output level of an inverter 24 changes from a low level to a high level and a transistor P2 is turned off from a turned on state, with a transistor N2 being turned on from a turned off state. In addition, as far as the output terminal is maintained at a high level, the transistor P3 is turned on by means of the Low- level output of the inverter 26.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a complementary MOS output circuit that outputs signals that change simultaneously from a plurality of output terminals, which prevents the occurrence of glitches due to the inflow of excessive current into the power supply, eliminates the risk of malfunction, and The purpose is to ensure that the slew rate of the output terminal is not affected by fluctuations in the power supply voltage. A complementary type M that outputs a signal from the output terminal by turning on either one of a second power supply on the potential side and a second output stage P-channel MOS transistor connected between the second power supply on the potential side and the output terminal.
In the OS output circuit, a constant current source that flows a constant current from the first or second power supply and an on-drive instruction of the first or second transistor are operated, and the constant current of the constant current source is used as a reference. a current mirror circuit that causes a constant current to flow from the second or first power source to turn on the first or second transistor; and a current mirror circuit that is provided between the output terminal and the current mirror circuit; It has a capacity that is charged and discharged by a constant current output from the circuit.

[Industrial application field]

The present invention relates to a complementary MOS output circuit, and more particularly to a complementary MOS output circuit that outputs signals that change simultaneously from a plurality of output terminals.

An integrated circuit having a complementary MOS (CMOS) configuration has a large number of output terminals, and outputs signals of multiple bits such as data and addresses that are changed simultaneously.

It is desired that the power supply voltage of the integrated circuit will not change even if a plurality of signals change simultaneously in this way.

[Conventional technology]

FIG. 3 shows a circuit diagram of an example of an output circuit of a conventional CMOS output circuit.

In the figure, when the data input to terminal IO is at H level, I
The P-channel MOS transistor PI is turned on by the L-level output of the P circuit 11, and the N-channel MOS transistor N1 is turned off by the L-level output of the NAND circuit 12, so that H-level data is output from the output terminal 14.

[Problem to be solved by the invention]

In the conventional circuit, when a large capacity load is connected to the output terminal, transistor P1 is turned on and transistor Nl is turned off. From the H level data output state, transistor Pi is turned off, and when transistor N1 is turned on, power is transferred from the load through transistor Nl. A transient current flows into the power source on the constant potential side, that is, the ground, and if the driving ability of the transistors Pi and Nl is large, the current flowing into the ground also becomes large. When outputting an address or data from the output terminal 14, for example, 32
When the bit address changes to the upper level or L level for all bits, an overcurrent flows from the 32 output circuits to the ground, causing a glitch in which the ground potential rises, and this causes the L level output signals of other output terminals to There was a problem in that the circuit could mistake it for an H level and cause malfunction.

The present invention has been developed in view of the above points, and it prevents the occurrence of glitches due to the inflow of excessive current into the power supply, eliminates the risk of malfunction, and makes the slew rate of the output terminal unaffected by fluctuations in the power supply voltage. The purpose is to provide a complementary MOS output circuit.

[Means to solve the problem]

The phase correction type MOS output circuit of the present invention includes a first output stage N-channel MOS) transistor connected between a first power supply on the low potential side and an output terminal, and a second power supply on the high potential side. A complementary MO that outputs a signal from the output terminal by turning on one of the second output stage P-channel MOS+- transistors connected between the output terminal and the second output stage P-channel MOS+- transistor.
In the S output circuit, a constant current source that flows a constant current from a first or second power supply, and a constant current that operates according to an on-drive instruction of the first or second transistor, and a constant current that is based on the constant current of the constant current source. A current mirror circuit is provided between the output terminal and the current mirror circuit, and is charged by the constant current output from the current mirror circuit. It has a discharge capacity.

[Effect]

In the present invention, a constant current is passed through a constant current source and a current mirror circuit to turn on the first or second transistor, and this constant current charges and discharges the capacitance, so that the transistor is gradually turned on. Therefore, the occurrence of glitches due to the inflow of transient current into the power supply is suppressed, and the slew rate of the output terminal is not affected by fluctuations in the voltage of the first power supply.

〔Example〕 FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention.

In the figure, data DATA input to a terminal 20 is supplied to a NAND circuit 21 and a NOR circuit 22.

The output of the NAND circuit 21 is inverted by the inverter 23 and supplied to the NOR circuit 22, and the output of the NAND circuit 22 is inverted by the inverter 23 and supplied to the NOR circuit 22.
4 and is inverted and supplied to the NAND circuit 21.

The inverted signal of the data DATA output from the inverter 24 is the P channel MOSI transistor P2 and the N channel M
A non-inverted signal of data DATA, which is supplied to each gate of the OS transistor N2 and outputted from the NOR circuit 22, is supplied to the gate of an N-channel MOS transistor N3.

The source of the transistor P2 is connected to the power supply Vcc, and the drain is connected to the drain of the transistor N2. The drain of the transistor N2 is connected to the train of the P-channel MOS transistor P3 and the gate of the P-channel MOS transistor P4, the source of the transistor P3 is connected to the drain and gate of the P-channel MOS transistor P5, and the source of the transistor P5 is connected to the power supply. V
connected to cc. Further, the source of the transistor N2 is connected to the drain of a depletion type N-channel MOS transistor N4, and the source and gate of the L transistor N4 are connected to the power supply Vss.

The source of the transistor P4 is connected to the power supply Vcc, the drain is connected to the drain of the transistor N3, and the source of the transistor N3 is connected to the power supply Vss.

Transistor P4. The drain of N3 is an N-channel MOS
) is connected to the gate of transistor Nl. The output of NAND circuit 21 is supplied to the gate of P-channel MOS transistor P1. The sources of the transistors PI and Nl are connected to the power supplies Vcc and Vss, and the output terminal 25 and the input terminal of the inverter 26 are connected to their commonly connected drains, and the output of the inverter 26 is connected to the transistor. Supplied to the gate of P3.

Also, the capacitance CI between the gate and drain of the transistor N1 is
connected via.

Here, the DATA entering the terminal 20 changes from H level to L level.
When the level changes, the output of the inverter 24 changes from L level to H level, transistor P2 changes from on to off, and transistor N2 changes from off to on. Also,
While the output terminal 25 is at the H level, the inverter 26 is at the L level.
Transistor P3 is turned on by the level output.

The transistor N4 is a depletion type and constitutes a constant current source, and the constant current [std
or transistor P5. P3. It flows through N2.

The threshold voltage of transistor P5 is set to Vtp (for example -0:9
V), the transistor P is connected to the gate of the transistor P4.
A constant current amplification factor of 5 is applied to the transistor P4, and a constant current amplification factor of 5 flows through the transistor P4 regardless of changes in the power supply voltage Vcc. In other words, transistor P5. P4 constitutes a current mirror circuit.

Further, the transistor N3 is turned off due to DATA changing from the H level to the L level, and the gate current of the transistor Nl increases due to the constant current of the transistor P4.

However, due to the discharge of the capacitor ff1c1 charged in the H level data output state, the rise in the gate potential of the transistor N1 is suppressed, and as the capacitor fllcl is discharged, it gradually rises and the transistor N1 starts to turn on. This accelerates the discharge of the capacitor CI (MOS) transistor N1.
is turned on, and the output terminal 14 becomes an L level data output state.

In this way, the feedback of the capacitor CI suppresses the increase in the gate potential of the transistor N1, and the capacitor C1 is connected to the power supply Vc.
Since the gate potential of the transistor Nl is charged by the transistor P4, which is not affected by fluctuations in Vcc, the rise in the gate potential of the transistor Nl is stable, and the slew rate of the output terminal 25 is not affected by fluctuations in the power supply Vcc. Since the discharge current does not flow suddenly, the occurrence of glitches is suppressed.

FIG. 2 shows a circuit diagram of another embodiment of the circuit according to the invention. In the figure, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

The non-inverted signal of the data DATA output from the inverter 34 is connected to the P-channel MOS transistor P2 and the N-channel MOS transistor M.
The inverted signal of the data DATA supplied to each gate of the OSt-run raster N12 and output from the NAND circuit 21 is P.
It is supplied to the gate of channel MOS transistor P13.

The drain of the transistor N12 is connected to the drain of the N-channel MOS transistor N13 and the gate of the N-channel MOS transistor N14.
The source of transistor N15 is connected to the drain and gate of N-channel MOS transistor NI5, and the source of transistor N15 is connected to power supply Vss. Further, the source of the transistor N12 is a P-channel MOS transistor P14.
The source of the transistor P14 is connected to the power supply Vcc.

The source of transistor N14 is connected to power supply Vss,
The drain is connected to the drain of transistor P13,
The source of transistor PI3 is connected to power supply Vcc. The drain of transistor N14°Pl3 is connected to the gate of P-channel MOS transistor Pl.

The output terminal 25 is connected to the input terminal of an inverter 36, and the output of the inverter 36 is supplied to the gate of the transistor NI3. Transistor P again! The gate and drain of are connected through a capacitor fiC2.

In addition, a P-channel MOS transistor P20 and a depletion type N-channel MOS transistor M are connected between the power supplies Vcc and Vss.
OS) transistor N20. N21 is connected, the gate and drain of transistor P20 and the gate of transistor P14 are commonly connected, and transistor N21
The output of the inverter 34 is supplied to the gate of the transistor N20, and the gate of the transistor N20 is connected to the source.

Here too, transistor P14 constitutes a constant current source, and transistors N14. N15 constitutes a current mirror circuit.

In this embodiment, when the output terminal 25 changes from H level to L level, the transistor N
The increase in the gate potential of transistor PI is suppressed, and the slew rate of the output terminal 25 is not affected by fluctuations in the power supply Vcc.In addition, due to the same operation, the decrease in the gate potential of transistor PI is suppressed by feedback of the capacitor C2. Since the capacitor C2 is charged by the transistor N14 which is not affected by fluctuations in the power supply Vss, the rise in the gate potential of the transistor Pl is stable and the slew rate of the output terminal 25 is not affected by fluctuations in the power supply Vss. Since the charging current of the load at the output terminal 25 does not flow suddenly, the occurrence of glitches is suppressed.

Note that as the capacitor CI, a MOS capacitor or a capacitor between polysilicon and polysilicon or metal may be used, and furthermore, the transistor N1. By using a conventional transistor with a large gate-drain capacitance as opposed to a lightly doped drain (LDD) type transistor for Pl, or by using a transistor with diffusion on the drain side to prevent electrostatic discharge damage, Gate-drain capacitance may also be used.

In addition, in the embodiments shown in FIGS. 1 and 2, P-channel MOS
) transistor is replaced with N-channel MOS) transistor, N-channel MOS) transistor is replaced with P-channel MOS)
It may be replaced with a transistor and the power supplies Vcc and Vss may be interchanged, and the present invention is not limited to the above embodiment.

〔Effect of the invention〕

As described above, according to the complementary MOS output circuit of the present invention,
It prevents the occurrence of glitches due to the inflow of transient current into the power supply, eliminating the risk of malfunction, and the slew rate of the output terminal is not affected by fluctuations in the power supply voltage, making it extremely useful in practice.

[Brief explanation of drawings]

1 and 2 are circuit diagrams of respective embodiments of the circuit of the present invention, and FIG. 3 is a circuit diagram of an example of a conventional circuit. In the figure, 21 is a NAND circuit, 22 is a NOR circuit, 24.26, 34.36 are inverters, PI-P21 is a P-channel MOS transistor, and N1 to N21 are N-channel MOS transistors. Figure 1: 奎艷明%iJIIwy Eye Bathing Agony Figure 2

Claims (1)

[Claims] A first output stage N-channel MOS transistor (N
1) and the second output stage P-channel MOS transistor (P1) connected between the second power supply on the high potential side and the output terminal (25), the output terminal is turned on. (25) In a complementary MOS output circuit that outputs a signal, a constant current source (N4
), and operates according to an on-drive instruction of the first or second transistor (N1, P1), and supplies a constant current based on the constant current of the constant current source (N4) from the second or first power source. Between a current mirror circuit (P4, P5) that flows to turn on the first or second transistor (N1, P1), and the output terminal (25) and the current mirror circuit (P4, P5). A complementary MOS output circuit characterized in that it has a capacitor (C1) that is provided and charged and discharged by a constant current output from the current mirror circuit (P4, P5).