JPH07154235A - Output circuit - Google Patents

Abstract

PURPOSE:To obtain an open drain output with a desired logic with respect to an input signal by providing a CMOS inverter and an NMOS transistor(TR) whose drain provides an output of signal to the output circuit. CONSTITUTION:When an input signal VIN is set to an L level, a PMOS transistor (TR) MP1 is turned on and an output of a CMOS inverter 1 reaches a high potential power supply VDD. Then the high potential power supply VDD is applied to a gate of a NMOS TR MN3 and the high potential power supply VDD is applied also to the source, then the NMOS TR MN3 is turned off and an output signal VOUT reaches a high impedance state. Furthermore, with the input signal VIN set to an H level, an NMOS TR MN1 is turned on and an output of the CMOS inverter 1 reaches a low potential power supply VSS. Thus, the high potential power supply VDD is applied to a gate of an NMOS TR MN3 and a low potential power supply VSS is applied to the source, then the NMOS TR MN3 is turned on and the output signal VOUT reaches an L level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS output circuit. In recent years, CMOS semiconductor integrated circuit devices are required to be able to supply a plurality of power supplies of 5 V or 3 V, for example. Therefore, it is required that the interface of the semiconductor integrated circuit device can be easily changed to each power source. When transferring from a semiconductor integrated circuit device compatible with 5V to a semiconductor integrated circuit device compatible with 3V, a protection diode may be provided between the input terminal of the interface and the power supply in the device compatible with 3V. Then, current flows from the 5 volt power supply to the 3 volt power supply. To prevent this current from flowing, it is necessary to make the output of the device compatible with 5 volts an open drain type.

[0002]

2. Description of the Related Art FIG. 6 shows an open drain type output circuit 20 in a conventional CMOS semiconductor integrated circuit device. PMOS and NMOS transistors MP5 and MN5 are connected in series between the high-potential power supply VDD and the low-potential power supply VSS.
A MOS inverter 21 is formed. A common input signal VIN is applied to the gates of both transistors MP5 and MN5. The output NMOS transistor MN6 has a gate connected to the node n0 between the transistors MP5 and MN5, and a source connected to the low potential power supply VSS.
The drain of the transistor MN6 is not connected to the power supply, and the output signal VOUT is output from the drain by controlling the gate voltage of the transistor MN6.

Therefore, when the input signal VIN is at the H level, the transistor MN5 turns on and the node n0 goes to the L level, and the transistor MN6 turns off and the output signal VOU.
T becomes the Z state (high impedance state). When the input signal VIN is at L level, the transistor MP5 is turned on, the node n0 becomes H level, and the transistor MN6.
Turns on and the output signal VOUT becomes L level.

[0004]

However, in the above output circuit 20, in order to output the output signal VOUT in the L level and the Z state with respect to the H level and the L level of the input signal VIN, respectively, another The inverter must be provided before the inverter 21. Therefore, there is a problem that the circuit becomes large and the delay time also increases accordingly.

The present invention has been made to solve the above problems, and an object thereof is to obtain an open drain output of a desired logic for an input signal while suppressing an increase in the size of the circuit. It is to provide an output circuit that can.

Another object of the present invention is to provide an output circuit capable of increasing the switching speed of the output transistor.

[0007]

FIG. 1 is a diagram for explaining the principle of the present invention. The CMOS inverter 1 includes a PMOS and an N connected in series between a high potential power supply VDD and a low potential power supply VSS.
It is composed of MOS transistors MP1 and MN1. CMOS
The inverter 1 inverts the input signal VIN and outputs it.

The output NMOS transistor MN3 has a gate to which the high potential power source VDD is applied, a source to which the output of the CMOS inverter 1 is applied, and a drain to output an output signal VOUT.

[0009]

When the input signal VIN is at L level, the PMOS transistor MP1 is turned on and the output of the CMOS inverter 1 becomes the high potential power supply VDD. NMOS transistor MN
Although the high potential power supply VDD is applied to the gate of 3, the NMOS transistor MN3 is turned off and the output signal VOUT is in the high impedance state because the high potential power supply VDD is also applied to the source. When the input signal VIN is at H level, the NMOS transistor MN1 is turned on and the CM
The output of the OS inverter 1 becomes the low potential power supply VSS. NM
Since the high potential power supply VDD is applied to the gate of the OS transistor MN3 and the low potential power supply VSS is applied to the source thereof, the NMOS transistor MN3 is turned on and the output signal V
OUT becomes L level.

[0010]

An embodiment of an output circuit embodying the present invention will be described below with reference to FIG. For convenience of explanation, the same components as those in FIG. 1 will be described with the same reference numerals.

The output circuit 2 includes a CMOS inverter 1, an output NMOS transistor MN3, and an electrostatic breakdown prevention NMOS transistor MN4. The inverter 1 includes PMOS and NMOS transistors MP1 and MP1 connected in series between the high potential power supply VDD and the low potential power supply VSS.
It consists of MN1. The inverter 1 inverts the input signal VIN and outputs it.

In the transistor MN3, the power supply VDD is applied to the gate and the output of the inverter 1 is applied to the source. The drain of the transistor MN3 is connected to the output terminal 3, and the transistor MN3 outputs the output signal VOUT to the outside through the output terminal 3.

The drain of the transistor MN4 is connected to the output terminal 3, and the gate and source thereof are connected to the power supply VSS. When negative static electricity is applied to the output terminal 3 from the outside, the transistor MN4 is turned on to allow a current to flow from the power supply VSS to the output terminal 3, thereby preventing the transistor MN3 from being destroyed by the negative static electricity.

In the output circuit 2 configured as described above, when the input signal VIN is at L level, the transistor M
When P1 is turned on, the output of the inverter 1 becomes the power supply VDD.
The power supply VDD is applied to the gate of the transistor MN3, but the power supply VDD is also applied to the source. for that reason,
The transistor MN3 is turned off and the output signal VOUT is in a high impedance state.

When the input signal VIN is at H level,
The transistor MN1 is turned on and the output of the inverter 1 becomes the power supply VSS. A power supply V is applied to the gate of the transistor MN3.
Since DD is applied and the power supply VSS is applied to the source,
The NMOS transistor MN3 turns on, and the output signal VOUT
Becomes L level.

As described above, the output circuit 2 of the present embodiment does not make the circuit larger than the conventional output circuit 20, but the L level and the Z state with respect to the H level and the L level of the input signal VIN. Output signals VOUT can be output.

FIG. 3 shows an output circuit 4 according to another embodiment of the present invention.
It is shown. The output circuit 4 differs from the output circuit 2 in that it includes a CMOS inverter 5. The inverter 5 includes PMOS and NMOS transistors MP2 and MP2 connected in series between the power source VDD and the power source VSS.
It consists of MN2. The output signal of the inverter 1 is applied to the gates of the transistors MP2 and MN2, and the gate of the transistor MN3 is connected between the transistors MP2 and MN2. The inverter 5 outputs a voltage signal VG which is the inverted output signal of the inverter 1 to the transistor M.
Output to the gate of N3.

In the output circuit 4 configured as described above, when the input signal VIN changes from H level to L level, the output of the inverter 1 and the source voltage of the transistor MN3 change from L level to H level. As a result, the output of the inverter 5 and the gate voltage of the transistor MN3 are H
Change from level to L level. Therefore, since the change in the potential difference between the gate and the source of the transistor MN3 with respect to time is larger than that in the output circuit 2, the switching speed of the transistor MN3 is faster, and the output signal VOUT becomes a high impedance state faster than the output circuit 2. .

When the input signal VIN changes from the L level to the H level, the output of the inverter 1 and the transistor MN
The source voltage of 3 changes from H level to L level. As a result, the output of the inverter 5 and the gate voltage of the transistor MN3 change from L level to H level. Therefore, since the change in the potential difference between the gate and the source of the transistor MN3 with respect to time is larger than that in the output circuit 2, the switching speed of the transistor MN3 is faster, and the output signal VOUT is faster than the output circuit 2 by L.
It becomes a level.

As described above, the output circuit 4 of this embodiment has the same effects as the output circuit 2 and can increase the switching speed of the output transistor MN3.

FIG. 4 shows an output circuit 6 of still another embodiment. In this output circuit 6, the output MOS transistor is the PMOS transistor MP3, and
The MOS transistor for preventing electrostatic breakdown is the PMOS transistor MP4. Other configurations are the same as those of the output circuit 2.

The power source VSS is applied to the gate of the transistor MP3, and the output of the inverter 1 is applied to the source of the transistor MP3. The drain of the transistor MP3 is connected to the output terminal 3, and the transistor MP3 is connected to the output terminal 3
The output signal VOUT is output to the outside via.

The drain of the transistor MP4 is connected to the output terminal 3, and the gate and source are connected to the power supply VDD. When positive static electricity is applied to the output terminal 3 from the outside, the transistor MP4 is turned on and the output terminal 3 is turned on.
Current is supplied to the power supply VDD to prevent the transistor MP3 from being damaged by positive static electricity.

In the output circuit 6 configured as described above, when the input signal VIN is at L level, the transistor M
When P1 is turned on, the output of the inverter 1 becomes the power supply VDD.
The power supply VSS is applied to the gate of the transistor MP3,
Since the power supply VDD is applied to the source, the transistor M
P3 is turned on and the output signal VOUT becomes H level.

When the input signal VIN is at H level,
The transistor MN1 is turned on and the output of the inverter 1 becomes the power supply VSS. Power supply V is applied to the gate of transistor MP3
Although SS is applied, the power supply VSS is also applied to the source. Therefore, the transistor MP3 is turned off and the output signal VOUT is in a high impedance state.

As described above, also in the output circuit 6 of this embodiment, it is possible to obtain an open drain output having a desired logic with respect to the input signal VIN while suppressing the increase in size of the circuit. FIG. 5 shows an output circuit 7 of another embodiment.
The output circuit 7 is different from the output circuit 6 in that it includes a CMOS inverter 5. Inverter 5
Is a PMO connected in series between the power supply VDD and the power supply VSS
S and NMOS transistors MP2 and MN2.
The output signal of the inverter 1 is applied to the gates of the transistors MP2 and MN2,
The gate of the transistor MP3 is connected between the two. The inverter 5 inverts the output signal of the inverter 1 and outputs a voltage signal VG to the gate of the transistor MP3.

In the output circuit 7 configured as described above, when the input signal VIN changes from H level to L level, the output of the inverter 1 and the source voltage of the transistor MP3 change from L level to H level. As a result, the output of the inverter 5 and the gate voltage of the transistor MP3 are H
Change from level to L level. Therefore, since the change in the potential difference between the gate and the source of the transistor MP3 with respect to time is larger than that in the output circuit 6, the switching speed of the transistor MP3 is faster and the output signal VOUT becomes the H level faster than the output circuit 6.

When the input signal VIN changes from L level to H level, the output of the inverter 1 and the transistor MP
The source voltage of 3 changes from H level to L level. As a result, the output of the inverter 5 and the gate voltage of the transistor MP3 change from L level to H level. Therefore, the change in the potential difference between the gate and the source of the transistor MP3 with respect to time is larger than that in the output circuit 6, so that the switching speed of the transistor MP3 is faster and the output signal VOUT is in a high impedance state faster than the output circuit 6. .

As described above, the output circuit 7 of this embodiment has the same effects as the output circuit 6, and the output circuit 7 can be operated at high speed by increasing the switching speed of the output transistor MP3. .

[0030]

As described above in detail, according to the present invention, it is possible to obtain an open drain output having a desired logic with respect to an input signal while suppressing an increase in the size of the circuit.

Further, according to the present invention, the switching speed of the output transistor can be increased to speed up the operation of the output circuit.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an output circuit of an embodiment.

FIG. 3 is a circuit diagram showing an output circuit of another embodiment.

FIG. 4 is a circuit diagram showing an output circuit of another embodiment.

FIG. 5 is a circuit diagram showing an output circuit of another embodiment.

FIG. 6 is a circuit diagram showing a conventional output circuit.

[Explanation of symbols]

 1,5 CMOS inverter MN1, MN2 NMOS transistor MN3 NMOS transistor for output MP1, MP2 PMOS transistor MP3 PMOS transistor for output VDD High potential power supply VG Voltage signal VIN input signal VOUT output signal VSS Low potential power supply

Claims (3)

[Claims] 1. A high potential power supply (VDD) and a low potential power supply (V)
CMOS inverter (1) consisting of PMOS and NMOS transistors (MP1, MN1) connected in series between SS) and inverting and outputting the input signal (VIN)
The high potential power supply (VDD) is applied to the gate, the output of the CMOS inverter (1) is applied to the source, and the output NMOS transistor (MN3) that outputs the output signal (VOUT) from the drain An output circuit comprising: 2. A high potential power source (VDD) and a low potential power source (V)
CMOS inverter (1) consisting of PMOS and NMOS transistors (MP1, MN1) connected in series between SS) and inverting and outputting the input signal (VIN)
The low potential power supply (VSS) is applied to the gate, the output of the CMOS inverter (1) is applied to the source, and the output PMOS transistor (MP3) for outputting the output signal (VOUT) from the drain An output circuit comprising: 3. A high potential power supply (VDD) and a low potential power supply (V
A first CMOS inverter (1) composed of PMOS and NMOS transistors (MP1, MN1) connected in series between SS) and inverting and outputting an input signal (VIN); and the high potential power supply (VDD) ) And a low-potential power supply (VSS) connected in series between PMOS and NMOS transistors (M
P2, MN2), and a second CMOS inverter (5) that generates a voltage signal (VG) by inverting the output of the first CMOS inverter (1), and the voltage signal (VG) at the gate Is applied,
An output MOS transistor (MN3, MP3) to which the output of the first CMOS inverter (1) is applied to the source and which further outputs an output signal (VOUT) from the drain
An output circuit comprising: