KR100465872B1 - Open Drain and Pull-Up Circuitry - Google Patents

Abstract

The present invention discloses an open drain and pull up circuit. The circuit includes first and second transistors connected in series between a power supply voltage and a ground voltage to generate a predetermined voltage, a pullup transistor having a drain electrode connected to the power supply voltage and a gate electrode to which the predetermined voltage is applied, and the pullup transistor. The first and pull-up transistors, when used for open drain, having a data input / output pad connected to a source electrode of a and a pull-down transistor connected between the data input / output pad and a ground voltage and controlled by an input signal. In an incremental manner, when the second transistor is configured as a depletion type and used for a pullup, the first and pullup transistors are configured as a depletion type and the second transistor is configured as an incremental type. Therefore, the operator does not have to open or access the metal according to the request of the orderer, thereby making it easy to manage, improve productivity, and reduce process accidents.

Description

Open Drain and Pullup Circuit

FIELD OF THE INVENTION The present invention relates to open drain and pull up circuits, and more particularly to open drain and pull up circuits with simple configurations of open drain and pull up options.

As the design rules of the process become stricter, parts that have not been a problem in the past become a problem, leading to weak competitiveness in the field and instability of the company's mass production.

Among the semiconductor chips that are essential for electronic products, there are many microcomputer products whose functions vary depending on the type of electronic products.

Among the microcomputer products, the metal drain option has been selectively applied as a pull-up used for resistance by turning on the open drain and the transistor using the internal resistor by blocking the internal transistor when using an external resistor at the request of a customer. .

In the related art, one open drain and one pull up mask were manufactured using the metal 1 option to separately manage and operate the mask. In this way, the ROM coding option and the Metal 1 option required by the purchaser are different, so that various combinations can be produced by using the Metal 1 option for open drain and pull-up as well as the option used for ROM coding. As a result, there was a possibility of confusion and misapplication, and the risk of accident was high.

Accordingly, it is an object of the present invention to provide an off-drain and pull-up circuit that can eliminate the metall option and operate with open drain and pullup.

The open-drain and pull-up circuits of the present invention for achieving the above object are connected in series between a power supply voltage and a ground voltage, and the first and second transistors for generating a predetermined voltage in common with each gate electrode and a source electrode. For example, a drain electrode is connected to the power supply voltage and a gate electrode is connected to a gate electrode and a source electrode of the first transistor to receive the predetermined voltage, a data input / output pad connected to a source electrode of the pull-up transistor, And a pull-down transistor connected between the data input / output pad and a ground voltage and controlled by an input signal, wherein the first and pull-up transistors are incremental when the open drain is used, and the second transistor is depleted. If configured as a pull-up and the first and pull-up Tran It is characterized by the configuration of the depletion type of the resistor and the second transistor of the increase type.

In addition, the chip employing the same has a plurality of data input / output pins, each of the plurality of data input / output pins are connected in series between a power supply voltage and a ground voltage, and each gate electrode and source electrode are connected to each other. First and second transistors for generating a predetermined voltage in common, a drain electrode connected to the power supply voltage, and a gate electrode connected to the gate electrode and the source electrode of the first transistor to receive the predetermined voltage; A data input / output pad connected to a source electrode of the pull-up transistor, and a pull-down transistor connected between the data input / output pad and a ground voltage and controlled by an input signal, wherein the pin is used for open drain. The first and pull-up transistors are increased and the second transistor is depleted. In the case of using the pull-up transistor, the first and pull-up transistors are depleted and the second transistor is increased.

Hereinafter, a description will be given of a conventional open drain and pull-up circuit before explaining the open drain and pull-up circuit of the present invention with reference to the accompanying drawings.

1 is a circuit diagram of a conventional open drain and pull-up circuit, in which an NMOS transistor M1 having a gate electrode and a source electrode commonly connected to a drain electrode connected to a power supply voltage Vdd, and a drain connected to a source electrode of an NMOS transistor M1 are shown in FIG. NMOS transistor M2 having a source electrode and a gate electrode connected to the electrode and the ground voltage, an NMOS transistor M3 having a drain electrode connected to the power supply voltage and a gate electrode connected to the gate electrode of the NMOS transistor M1, and an NMOS transistor M3. Metal 1 (12), a data input / output pad 10 connected to the metal 1 (12), and a gate electrode and a data input / output pad (10) to which a signal generated from the inside is applied. NMOS transistor (M4) having a drain electrode connected to the () and a source electrode connected to the ground voltage.

In the case where the circuit shown in FIG. 1 is to be used for open drain, the NMOS transistor M4 is generated by a signal generated from the inside by opening the metal 1 12 that electrically connects the pad 10 and the NMOS transistor M3. ) On and off. At this time, data of "1" or "0" is output to the pad 10.

In addition, when using for a pull-up, the metal 1 12 which electrically connects the pad 10 and the NMOS transistor M3 is connected. At this time, the NMOS transistors M1 and M3 are depletion NMOS transistors, and the NMOS transistors M2 and M4 are enhancement NMOS transistors. Thus, in the conventional open drain and pullup circuit, two metal 1 options are used and managed to configure for the open drain and pullup.

FIG. 2 is a circuit diagram of the open drain and pull-up circuit of the present invention, which has the same configuration as the circuit shown in FIG. 1 and is not intended to operate for open drain and pull-up by electrically opening and shorting the metal 1; In this case, NMOS transistors M1 and M3 are configured as incremental NMOS transistors and NMOS transistor M2 is configured as a depletion NMOS transistor. This can be easily implemented by impurity implantation in the manufacturing process. In the case of using the pull-up, the NMOS transistors M1 and M3 are configured as a depletion type NMOS transistor and the NMOS transistor M2 is configured as an incremental NMOS transistor. It can likewise be easily configured in incremental or depleted form upon impurity injection in the manufacturing process.

That is, the open-drain and pull-up circuit of the present invention can be selectively configured as an open-drain and pull-up circuit at the request of the orderer, but transistors constituting the pull-up circuit in the manufacturing process without electrically opening or connecting the metal 1 like the conventional circuit. By configuring the form of these as described above, it can be used for open drain and pull-up.

Therefore, the open drain and pull-up circuit of the present invention is easy to manage, improve productivity and reduce process accidents because the operator does not have to open or connect the metal according to the request of the orderer.

1 is a circuit diagram of a conventional open drain and pull-up circuit.

Figure 2 is a circuit diagram of an open drain and pull up circuit of the present invention.

Claims (10)

First and second transistors connected in series between a power supply voltage and a ground voltage, and configured to generate predetermined voltages in common with each gate electrode and a source electrode; A pull-up transistor having a drain electrode connected to the power supply voltage and a gate electrode connected to the gate electrode and the source electrode of the first transistor to receive the predetermined voltage; A data input / output pad connected to a source electrode of the pull-up transistor; And A pull-down transistor connected between the data input / output pad and a ground voltage and receiving an input signal as a gate; and in the case of using open drain, the first and pull-up transistors are configured in an incremental manner and the second transistor is An open drain and pull-up circuit comprising a depletion type and a depletion type of the first and pull-up transistors and an incremental type of the second transistor when used for a pull-up type. The open drain and pull-up circuit of claim 1, wherein the first transistor is an NMOS transistor. The open drain and pull-up circuit of claim 1, wherein the second transistor is an NMOS transistor. The open drain and pull-up circuit of claim 1, wherein the pull-up transistor is an NMOS transistor. The open drain and pull-up circuit of claim 1, wherein the pull-down transistor is an NMOS transistor. In a chip having a plurality of data input / output pins, Each of the plurality of data input / output pins First and second transistors connected in series between a power supply voltage and a ground voltage, and configured to generate predetermined voltages in common with each gate electrode and a source electrode; A pull-up transistor having a drain electrode connected to the power supply voltage and a gate electrode connected to the gate electrode and the source electrode of the first transistor to receive the predetermined voltage; A data input / output pad connected to a source electrode of the pull-up transistor; And A pull-down transistor connected between the data input / output pad and a ground voltage and controlled by an input signal, and when the pin is used for open drain, the first and pull-up transistors are incremented and the second transistor is increased. When the depletion type is used and the pull-up is used, the first and pull-up transistors are depleted and the second transistor is configured to be increased. 7. The chip of claim 6, wherein the first transistor is an NMOS transistor. 7. The chip of claim 6, wherein the second transistor is an NMOS transistor. 7. The chip of claim 6, wherein the pull-up transistor is an NMOS transistor. 7. The chip of claim 6, wherein the pull-down transistor is an NMOS transistor.

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