EP0442618A1 - CMOS clamp circuits - Google Patents
CMOS clamp circuits Download PDFInfo
- Publication number
- EP0442618A1 EP0442618A1 EP91300444A EP91300444A EP0442618A1 EP 0442618 A1 EP0442618 A1 EP 0442618A1 EP 91300444 A EP91300444 A EP 91300444A EP 91300444 A EP91300444 A EP 91300444A EP 0442618 A1 EP0442618 A1 EP 0442618A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- transistor
- input node
- channel
- cmos
- inverter means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
- H03K19/018521—Interface arrangements of complementary type, e.g. CMOS
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
Definitions
- This invention relates generally to CMOS semi-conductor integrated circuits and more particularly, it relates to improved CMOS clamp circuits
- CMOS digital integrated circuits normal logic levels are (1) a low or "0 ⁇ " logic state which is represented by a lower power supply potential VSS and (2) a high or “1" logic state which is represented by an upper power supply potential VCC.
- the lower power potential VSS is usually connected to an external ground or 0 ⁇ volts and upper potential VCC is typically connected to a voltage source referenced above ground, i.e., +5.0 ⁇ volts. It is often desirable to limit the voltage swings of CMOS circuits so as to improve their performance. By so limiting the voltage swing at a particular node, less charge will be required to be charged up and discharged at a particular node in a given circuit, thereby permitting a faster speed of operation.
- CMOS technology due to the complementary structure is generally considered to be a low power technology since standard logic circuits consume virtually no quiescent power and consumes power only during switching. However, this is true only if the voltage on the clamped node is at a true logic state of VSS or VCC.
- the clamp circuit by itself does not dissipate excess power but results in power consumption of circuits whose gate logic is connected to the clamp circuit.
- V Tn and V Tp are the respective body-effect enhanced thresholds of an N-channel transistor and a P-channel transistor.
- CMOS clamp circuits which consume less power than has been traditionally available. Further, it would be expedient to provide CMOS clamp circuits which include a power down mode of operation in which the clamping transistor is deactivated, thereby reducing power consumption.
- CMOS clamp circuit which is formed of a sense inverter, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor.
- CMOS clamp circuit which includes a power-down mode of operation in which the clamping transistor is deactivated, thereby further reducing power consumption when the output of the sense inverter is not being used.
- CMOS clamp circuit which includes a sense inverter, an N-channel MOS clamping transistor, a P-channel MOS clamping transistor, an enabling transistor, and a power-down transistor.
- an improved CMOS clamp circuit which includes a sense inverter having an input node for receiving a sense current signal and an output node for generating a voltage output, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor.
- the N-channel transistor has its drain connected to an upper power supply potential and its source connected to the input node of the inverter.
- the P-channel transistor has its drain connected to a lower power supply potential and its source connected to the input node of the inverter.
- the gates of the N-channel and P-channel transistors are connected to the output node of the inverter.
- an improved CMOS clamp circuit which further includes a P-channel MOS enabling transistor and an N-channel MOS pull-down transistor.
- an improved CMOS clamp circuit which further includes an N-channel MOS enabling transistor and a P-channel MOS pull-up transistor.
- the clamp circuit 10a consists of a sense inverter I1 and a pair of N-channel MOS clamping transistors N1 and N2.
- the sense inverter I1 has its input connected to an input node 12 for receiving a sense current signal and has its output connected to an output node 14 for generating a voltage output.
- the gate and drain electrodes of the transistor N1 are connected together and to the output node 14.
- the source electrode of the transistor N1 is connected to the input node 12.
- the gate and drain electrodes of the transistor N2 are connected together and to the input node 12.
- the source electrode of the transistor N2 is connected to the output node 14.
- the clamp circuit 10b consists of a sense amplifier I2, a P-channel MOS clamping transistor P1, and an N-channel MOS clamping transistor N3.
- the sense inverter I2 has its input connected to an input node 16 for receiving a sense current signal and has its output connected to an output node 18 for generating a voltage output.
- the gate and source electrodes of the transistor P1 are joined together and to the input node 16.
- the drain electrode of the transistor P1 is connected to the output node 18.
- the gate and drain electrodes of the transistor N3 are connected together and to the input node 16.
- the source electrode of the transistor N3 is connected to the output node 18.
- the clamp circuit 10c is comprised of a sense inverter I3 and a pair of P-channel MOS clamping transistor P2 and P3.
- the sense inverter I3 has its input connected to an input node 20 for receiving a sense current signal and its output connected to an output node 22 for generating a voltage output.
- the gate and source electrodes of the transistor P2 are connected together and to the output node 22.
- the drain electrode of the transistor P2 is connected to the input node 20.
- the gate and source electrodes of the transistor P3 are connected together and to the input node 20.
- the drain electrode of the transistor P3 is connected to the output node 22.
- the clamp circuit 10d is comprised of a sense inverter I4, a P-channel MOS clamping transistor P4, and an N-channel MOS clamping transistor N4.
- the sense inverter I4 has its input connected to an input node 24 for receiving a current sense signal and its output connected to an output node 26 for generating a voltage output.
- the gate and source electrodes of the transistor P4 are connected together and to the output node 26.
- the drain electrode of the transistor P4 is connected to the input node 24.
- the gate and drain electrodes of the transistor N4 are connected together and to the output node 26.
- the source electrode of the transistor N4 is connected to the input node 24.
- each of the sense inverters I1-I4 is a conventional CMOS inverter formed of a P-channel transistor and an N-channel transistor whose gate electrodes are connected together defining an input of the inverter and whose drain electrodes are connected together defining an output of the inverter.
- the source electrode of the P-channel transistor is connected to a first power supply potential VCC, which is typically +5.0 ⁇ volts.
- the source of the N-channel transistor is connected to a second power supply potential VSS, which is typically at 0 ⁇ volts.
- a CMOS clamp circuit 28 is illustrated in Figure 2 which is comprised of a sense inverter I5, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor P5.
- the sense inverter I5 has its input connected to an input node 30 for receiving a sense current signal and its output connected to an output node 32 for generating a voltage output.
- the inputs to the clamping transistors N5 and P5 are not connected to the output of the sense inverter I5 but are connected to the respective upper and lower power supply potentials VCC and VSS.
- the transistor N5 has its drain electrode connected to the upper power supply potential VCC, which is typically at +5.0 ⁇ volts, and its source electrode connected to the input node 30.
- the transistor P5 has its drain connected to the lower power supply potential VSS, which is typically at 0 ⁇ volts, and its source electrode connected to the input node 30.
- the output of the sense inverter I5 at the output node 32 is connected to the gates of the clamping transistors N5 and P5. Since the sense inverter I5 does not have to supply current to the clamping transistors N5 and P5, the sizes of the N-channel and P-channel transistors of the sense inverter I5 can be made smaller so as to reduce power consumption.
- FIG. 3a A second embodiment of a CMOS clamp circuit 34 of the present invention with a "power-down to logic zero state" mode of operation is depicted in Figure 3a.
- the clamp circuit 34 is comprised of a sense inverter I6, an N-channel MOS clamping transistor N6, a P-channel MOS clamping transistor P6, a P-channel MOS enabling transistor P7, and an N-channel MOS pull-down transistor N7.
- the sense inverter I6 has its input connected to an input node 36 for receiving a sense current signal and its output connected to an output node 38 for generating a voltage output.
- the clamping transistor N6 has its gate connected to the output of the sense inverter I6 at the output node 38 and its source connected to the input of the sense inverter at the input node 36.
- the clamping transistor P6 has its gate connected to the output node 38, its source connected to the input node 36, and its drain connected to the lower power supply potential VSS.
- the enabling transistor P7 has its source connected to the upper power supply potential VCC, its drain connected to the drain of the clamping transistor N6, and its gate connected to an input node 40 for receiving a complementary activate clamp signal CL .
- the enable transistor P7 serves to isolate the clamping transistor N6 from the upper power supply potential so as to allow deactivation of the clamping transistor N6.
- the pull-down transistor N7 has its drain connected to the input node 36, its source connected to the lower supply potential VSS, and its gate connected also to the input node 40.
- the enable transistor P7 is rendered conductive and the clamping transistors N6 and P6 are allowed to function normally. It will be noted that in this case, the pull-down transistor N7 is turned off.
- the activate clamp signal CL is set to a high logic level which turns off the enabling transistor P7.
- the pull-down transistor N7 is turned on which pulls down the input of the inverter I6 at the input node 36 to approximately the VSS voltage level. As a result, the sense inverter I6 will be powered down so as to have no current flow when the output node 38 is not being used.
- FIG. 3b A third embodiment of a CMOS clamp circuit 42 of the present invention with a "power-down to logic one state" mode of operation is depicted in Figure 3b.
- the clamp circuit 42 is comprised of a sense inverter I7, an N-channel MOS clamping transistor N8, a P-channel MOS clamping transistor P8, an N-channel MOS enabling transistor N9, and a P-channel MOS pull-up transistor P9.
- the sense inverter I7 has its input connected to an input node 44 for receiving a sense current signal and its output connected to an output node 46 for generating a voltage output.
- the clamping transistor N8 has its gate connected to the output node 46, its drain connected to the upper power supply potential VCC, and its source connected to the input of the sense inverter I7 at the input node 44.
- the clamping transistor P8 has its gate connected to the output node 46 and its source connected to the input node 44.
- the enabling transistor N9 has its drain connected to the drain of the clamping transistor P8, its source connected to the lower power supply potential VSS, and its gate connected to an input node 48 for receiving a true activate clamp signal CL.
- the enable transistor N9 serves to isolate the clamping transistor P8 from the lower power supply potential so as to allow deactivation of the clamping transistor P8.
- the pull-up transistor P9 has its drain connected to the input node 44, its source connected to the upper power supply potential VCC, and its gate connected also to the input node 48.
- the activate clamp signal CL when the activate clamp signal CL is at a high logic level the enabling transistor N9 is rendered conductive and the clamping transistors N8 and P8 are allowed to function normally. It will again be noted that the pull-up transistor P9 is turned off. When it is desired to operate in a power-down mode so as to conserve power dissipation, the activate clamp signal CL is set to a low logic level which turns off the enabling transistor N9. Further, the pull-up transistor P9 is turned on which pulls the input of the inverter I7 at the input node 44 to approximately the VCC voltage level. Consequently, the sense inverter I7 will be powered down so as to have no current flow when the output node 46 is not being used.
- the CMOS clamping circuit of the present invention is comprised of a sense inverter, an K-channel MOS clamping transistor, and a P-channel MOS clamping transistor. Further, there may be provided an enabling transistor and a power-down transistor so as to power-down the sense inverter, thereby reducing power dissipation when its output is not being used.
Abstract
Description
- This invention relates generally to CMOS semi-conductor integrated circuits and more particularly, it relates to improved CMOS clamp circuits
- As is generally well known in CMOS digital integrated circuits normal logic levels are (1) a low or "0̸" logic state which is represented by a lower power supply potential VSS and (2) a high or "1" logic state which is represented by an upper power supply potential VCC. The lower power potential VSS is usually connected to an external ground or 0̸ volts and upper potential VCC is typically connected to a voltage source referenced above ground, i.e., +5.0̸ volts. It is often desirable to limit the voltage swings of CMOS circuits so as to improve their performance. By so limiting the voltage swing at a particular node, less charge will be required to be charged up and discharged at a particular node in a given circuit, thereby permitting a faster speed of operation.
- While clamp circuits in CMOS technology are usually adequate to perform the function of limiting the voltage, they suffer from the disadvantage of consuming quiescent power. Thus, the problems of excessive power dissipation have limited the use of clamp circuits to critical areas of the design. Ideally, CMOS technology due to the complementary structure is generally considered to be a low power technology since standard logic circuits consume virtually no quiescent power and consumes power only during switching. However, this is true only if the voltage on the clamped node is at a true logic state of VSS or VCC. Typically, the clamp circuit by itself does not dissipate excess power but results in power consumption of circuits whose gate logic is connected to the clamp circuit. In practice, when the clamped node is not at one of the true logic states the logic gates connected thereto will not be completely turned off. If the actual logic voltages are above the (VSS + VTn) voltage level or below the (VCC - VTp) voltage level, then some amount of quiescent power will be dissipated. VTn and VTp are the respective body-effect enhanced thresholds of an N-channel transistor and a P-channel transistor.
- All of the prior art clamp circuits in CMOS technology have generally resulted in an excessive amount of power being consumed when used to limit the voltage swings. Therefore, it would be desirable to provide improved CMOS clamp circuits which consume less power than has been traditionally available. Further, it would be expedient to provide CMOS clamp circuits which include a power down mode of operation in which the clamping transistor is deactivated, thereby reducing power consumption.
- We will describe improved CMOS clamp circuits which consume less power than has been traditionally available.
- We will describe improved CMOS clamp circuit which is formed of a sense inverter, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor.
- We will describe improved CMOS clamp circuit which includes a power-down mode of operation in which the clamping transistor is deactivated, thereby further reducing power consumption when the output of the sense inverter is not being used.
- We will describe an improved CMOS clamp circuit which includes a sense inverter, an N-channel MOS clamping transistor, a P-channel MOS clamping transistor, an enabling transistor, and a power-down transistor.
- In one embodiment of the present invention, there is provided an improved CMOS clamp circuit which includes a sense inverter having an input node for receiving a sense current signal and an output node for generating a voltage output, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor. The N-channel transistor has its drain connected to an upper power supply potential and its source connected to the input node of the inverter. The P-channel transistor has its drain connected to a lower power supply potential and its source connected to the input node of the inverter. The gates of the N-channel and P-channel transistors are connected to the output node of the inverter.
- In another embodiment of the present invention, there is provided an improved CMOS clamp circuit which further includes a P-channel MOS enabling transistor and an N-channel MOS pull-down transistor. In still another embodiment, there is provided an improved CMOS clamp circuit which further includes an N-channel MOS enabling transistor and a P-channel MOS pull-up transistor.
- These and other advantages of the present invention will become more fully apparent from the following detailed description when read in conjunction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein:
- Figures 1a-1d illustrate various prior art clamping circuits which are constructed with a sense inverter and an N-channel and/or P-channel transistors;
- Figure 2 is a schematic circuit diagram of a CMOS clamping circuit, constructed in accordance with the principles of the present invention;
- Figure 3a is a schematic circuit diagram of a second embodiment of a CMOS clamping circuit having a power-down mode, constructed in accordance with the principles of the present invention; and
- Figure 3b is a schematic circuit diagram of a third embodiment of a CMOS clamping circuit having a power-down mode, constructed in accordance with the principles of the present invention.
- Referring now in detail to the drawings, there are shown in Figures 1a through 1d various prior art clamp circuits. In Figure 1a, the clamp circuit 10a consists of a sense inverter I1 and a pair of N-channel MOS clamping transistors N1 and N2. The sense inverter I1 has its input connected to an
input node 12 for receiving a sense current signal and has its output connected to anoutput node 14 for generating a voltage output. The gate and drain electrodes of the transistor N1 are connected together and to theoutput node 14. The source electrode of the transistor N1 is connected to theinput node 12. The gate and drain electrodes of the transistor N2 are connected together and to theinput node 12. The source electrode of the transistor N2 is connected to theoutput node 14. - In Figure 1b, the clamp circuit 10b consists of a sense amplifier I2, a P-channel MOS clamping transistor P1, and an N-channel MOS clamping transistor N3. The sense inverter I2 has its input connected to an
input node 16 for receiving a sense current signal and has its output connected to anoutput node 18 for generating a voltage output. The gate and source electrodes of the transistor P1 are joined together and to theinput node 16. The drain electrode of the transistor P1 is connected to theoutput node 18. The gate and drain electrodes of the transistor N3 are connected together and to theinput node 16. The source electrode of the transistor N3 is connected to theoutput node 18. - In Figure 1c, the clamp circuit 10c is comprised of a sense inverter I3 and a pair of P-channel MOS clamping transistor P2 and P3. The sense inverter I3 has its input connected to an
input node 20 for receiving a sense current signal and its output connected to anoutput node 22 for generating a voltage output. The gate and source electrodes of the transistor P2 are connected together and to theoutput node 22. The drain electrode of the transistor P2 is connected to theinput node 20. The gate and source electrodes of the transistor P3 are connected together and to theinput node 20. The drain electrode of the transistor P3 is connected to theoutput node 22. - In Figure 1d, the clamp circuit 10d is comprised of a sense inverter I4, a P-channel MOS clamping transistor P4, and an N-channel MOS clamping transistor N4. The sense inverter I4 has its input connected to an
input node 24 for receiving a current sense signal and its output connected to anoutput node 26 for generating a voltage output. The gate and source electrodes of the transistor P4 are connected together and to theoutput node 26. The drain electrode of the transistor P4 is connected to theinput node 24. The gate and drain electrodes of the transistor N4 are connected together and to theoutput node 26. The source electrode of the transistor N4 is connected to theinput node 24. - In the Figures 1a through 1d, each of the sense inverters I1-I4 is a conventional CMOS inverter formed of a P-channel transistor and an N-channel transistor whose gate electrodes are connected together defining an input of the inverter and whose drain electrodes are connected together defining an output of the inverter. The source electrode of the P-channel transistor is connected to a first power supply potential VCC, which is typically +5.0̸ volts. The source of the N-channel transistor is connected to a second power supply potential VSS, which is typically at 0̸ volts. It will be noted that if the actual logic levels at the
respective input nodes - A
CMOS clamp circuit 28 is illustrated in Figure 2 which is comprised of a sense inverter I5, an N-channel MOS clamping transistor, and a P-channel MOS clamping transistor P5. The sense inverter I5 has its input connected to aninput node 30 for receiving a sense current signal and its output connected to anoutput node 32 for generating a voltage output. In contrast to the prior art clamping circuits 10a-10d, the inputs to the clamping transistors N5 and P5 are not connected to the output of the sense inverter I5 but are connected to the respective upper and lower power supply potentials VCC and VSS. In particular, the transistor N5 has its drain electrode connected to the upper power supply potential VCC, which is typically at +5.0̸ volts, and its source electrode connected to theinput node 30. The transistor P5 has its drain connected to the lower power supply potential VSS, which is typically at 0̸ volts, and its source electrode connected to theinput node 30. The output of the sense inverter I5 at theoutput node 32 is connected to the gates of the clamping transistors N5 and P5. Since the sense inverter I5 does not have to supply current to the clamping transistors N5 and P5, the sizes of the N-channel and P-channel transistors of the sense inverter I5 can be made smaller so as to reduce power consumption. - A second embodiment of a
CMOS clamp circuit 34 of the present invention with a "power-down to logic zero state" mode of operation is depicted in Figure 3a. Theclamp circuit 34 is comprised of a sense inverter I6, an N-channel MOS clamping transistor N6, a P-channel MOS clamping transistor P6, a P-channel MOS enabling transistor P7, and an N-channel MOS pull-down transistor N7. The sense inverter I6 has its input connected to aninput node 36 for receiving a sense current signal and its output connected to an output node 38 for generating a voltage output. The clamping transistor N6 has its gate connected to the output of the sense inverter I6 at the output node 38 and its source connected to the input of the sense inverter at theinput node 36. The clamping transistor P6 has its gate connected to the output node 38, its source connected to theinput node 36, and its drain connected to the lower power supply potential VSS. - The enabling transistor P7 has its source connected to the upper power supply potential VCC, its drain connected to the drain of the clamping transistor N6, and its gate connected to an
input node 40 for receiving a complementary activate clamp signalCL . The enable transistor P7 serves to isolate the clamping transistor N6 from the upper power supply potential so as to allow deactivation of the clamping transistor N6. The pull-down transistor N7 has its drain connected to theinput node 36, its source connected to the lower supply potential VSS, and its gate connected also to theinput node 40. - In operation, when the activate clamp signal
CL is at an active low logic level the enable transistor P7 is rendered conductive and the clamping transistors N6 and P6 are allowed to function normally. It will be noted that in this case, the pull-down transistor N7 is turned off. When it is desired to operate in a power-down mode so as to reduce power consumption, the activate clamp signalCL is set to a high logic level which turns off the enabling transistor P7. Further, the pull-down transistor N7 is turned on which pulls down the input of the inverter I6 at theinput node 36 to approximately the VSS voltage level. As a result, the sense inverter I6 will be powered down so as to have no current flow when the output node 38 is not being used. - A third embodiment of a CMOS clamp circuit 42 of the present invention with a "power-down to logic one state" mode of operation is depicted in Figure 3b. The clamp circuit 42 is comprised of a sense inverter I7, an N-channel MOS clamping transistor N8, a P-channel MOS clamping transistor P8, an N-channel MOS enabling transistor N9, and a P-channel MOS pull-up transistor P9. The sense inverter I7 has its input connected to an
input node 44 for receiving a sense current signal and its output connected to anoutput node 46 for generating a voltage output. The clamping transistor N8 has its gate connected to theoutput node 46, its drain connected to the upper power supply potential VCC, and its source connected to the input of the sense inverter I7 at theinput node 44. The clamping transistor P8 has its gate connected to theoutput node 46 and its source connected to theinput node 44. - The enabling transistor N9 has its drain connected to the drain of the clamping transistor P8, its source connected to the lower power supply potential VSS, and its gate connected to an
input node 48 for receiving a true activate clamp signal CL. The enable transistor N9 serves to isolate the clamping transistor P8 from the lower power supply potential so as to allow deactivation of the clamping transistor P8. The pull-up transistor P9 has its drain connected to theinput node 44, its source connected to the upper power supply potential VCC, and its gate connected also to theinput node 48. - In operation, when the activate clamp signal CL is at a high logic level the enabling transistor N9 is rendered conductive and the clamping transistors N8 and P8 are allowed to function normally. It will again be noted that the pull-up transistor P9 is turned off. When it is desired to operate in a power-down mode so as to conserve power dissipation, the activate clamp signal CL is set to a low logic level which turns off the enabling transistor N9. Further, the pull-up transistor P9 is turned on which pulls the input of the inverter I7 at the
input node 44 to approximately the VCC voltage level. Consequently, the sense inverter I7 will be powered down so as to have no current flow when theoutput node 46 is not being used. - From the foregoing detailed description, it can thus be seen that the present invention provides improved clamping circuits which consume less power than has been traditionally available. The CMOS clamping circuit of the present invention is comprised of a sense inverter, an K-channel MOS clamping transistor, and a P-channel MOS clamping transistor. Further, there may be provided an enabling transistor and a power-down transistor so as to power-down the sense inverter, thereby reducing power dissipation when its output is not being used.
- While there has been illustrated and described what is at present considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodiments disclosed as the best modes contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims.
Claims (13)
- A CMOS clamp circuit comprising:
sense inverter means (I5) having an input node for receiving a sense current signal and an output node for generating a voltage output;
an N-channel MOS clamping transistor (N5) having its drain connected to an upper power supply potential (VCC) and its source connected to the input node of said inverter means;
a P-channel MOS clamping transistor (P5) having its drain connected to a lower power supply potential (VSS) and it source connected to the input node of said inverter means; and
the gates of said N-channel and P-channel transistors (N5, P5) being connected to the output node of said inverter means. - A CMOS clamping circuit comprising:
sense inverter means (I6) having an input node for receiving a sense current signal and an output node for generating a voltage output;
an N-channel MOS clamping transistor (N6) having its gate connected to the output node of said inverter means and it source connected to the input node of said inverter means;
a P-channel MOS clamping transistor (P6) having its gate connected to the output of said inverter means, its source connected to the input node of said inverter means, and its drain connected to a lower power supply potential (VSS); and
enabling means responsive to a complementary activate clamp signal for deactivating said N-channel clamping transistor (N6) so as to reduce power consumption when the output node of said inverter means is not being used. - A CMOS clamping circuit as claimed in Claim 2, wherein said enabling means comprises a P-channel MOS enabling transistor (P7) having its source connected to an upper power supply potential (VCC) and its drain connected to the drain of said N-channel clamping transistor (N6), the gate of said enabling transistor (P7) being connected to a second input node for receiving the complementary activate clamp signal.
- A CMOS clamp circuit as claimed in Claim 3, further comprising power-down means responsive to the complementary activate clamp signal for pulling down the input node of said inverter means to the lower power supply potential (VSS) so as to have no current flow in said inverter means.
- A CMOS clamp circuit as claimed in Claim 4, wherein said power-down means comprises an N-channel MOS pull-down transistor (N7) having its drain connected to the input node of said inverter means, its source connected to the lower power supply potential (VSS), and its gate connected to the second input node for receiving the complementary activate clamp signal.
- A CMOS clamp circuit as claimed in Claim 5, wherein said inverter means comprises a CMOS inverter formed of a P-channel MOS transistor and an N-channel MOS transistor, the gates of said P-channel and N-channel transistors being connected together defining the input node, the drains of said P-channel and N-channel transistors being connected together defining the output node.
- A CMOS clamp circuit as claimed in Claim 6, wherein said enabling transistor (P7) is turned off and said pull-down transistor (N7) is turned on when said complementary activate clamp signal is at a high logic level.
- A CMOS clamping circuit comprising:
sense inverter means (I7) having an input node for receiving a sense current signal and an output node for generating a voltage output;
a P-channel MOS clamping transistor (P8) having its gate connected to the output node of said inverter means and it source connected to the input node of said inverter means;
an N-channel MOS clamping transistor (N8) having its gate connected to the output of said inverter means, its source connected to the input node of said inverter means, and its drain connected to an upper power supply potential (VCC); and
enabling means responsive to a true activate clamp signal for deactivating said P-channel clamping transistor (P8) so as to reduce power consumption when the output node of said inverter means is not being used. - A CMOS clamping circuit as claimed in Claim 8, wherein said enabling means comprises an N-channel MOS enabling transistor (N9) having its source connected to a lower power supply potential (VSS) and its drain connected to the drain of said P-channel clamping transistor (P8), the gate of said enabling transistor (N9) being connected to a second input node for receiving the true activate clamp signal.
- A CMOS clamp circuit as claimed in Claim 9, further comprising power-down means responsive to the true activate clamp signal for pulling up the input node of said inverter means to the upper power supply potential (VCC) so as to have no current flow in said inverter means.
- A CMOS clamp circuit as claimed in Claim 10, wherein said power-down means comprises a P-channel MOS pull-up transistor (P9) having its drain connected to the input node of said inverter means, its source connected to the upper power supply potential (VCC), and its gate connected to the second input node for receiving the true activate clamp signal.
- A CMOS clamp circuit as claimed in Claim 11, wherein said inverter means comprises a CMOS inverter formed of a P-channel MOS transistor and an N-channel MOS transistor, the gates of said P-channel and N-channel transistors being connected together defining the input node, the drains of said P-channel and N-channel transistors being connected together defining the output node.
- A CMOS clamp circuit as claimed in Claim 12, wherein said enabling transistor (N9) is turned off and said pull-up transistor (P9) is turned on when said true activate clamp signal is at a low logic level.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/480,400 US5027008A (en) | 1990-02-15 | 1990-02-15 | CMOS clamp circuits |
US480400 | 2000-01-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP0442618A1 true EP0442618A1 (en) | 1991-08-21 |
EP0442618B1 EP0442618B1 (en) | 1996-06-05 |
Family
ID=23907818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP91300444A Expired - Lifetime EP0442618B1 (en) | 1990-02-15 | 1991-01-21 | CMOS clamp circuits |
Country Status (5)
Country | Link |
---|---|
US (1) | US5027008A (en) |
EP (1) | EP0442618B1 (en) |
JP (1) | JPH06216725A (en) |
AT (1) | ATE139070T1 (en) |
DE (1) | DE69119926T2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996027252A2 (en) * | 1995-02-21 | 1996-09-06 | Advanced Micro Devices, Inc. | Line driver and receiver cells for ethernet applications |
CN101571928B (en) * | 2008-04-28 | 2011-12-21 | 软控股份有限公司 | Method for alternating current logic power supply for electronic tag chip |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5619066A (en) * | 1990-05-15 | 1997-04-08 | Dallas Semiconductor Corporation | Memory for an electronic token |
US5245583A (en) * | 1991-04-02 | 1993-09-14 | Vitelic Corporation | Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method |
US5994770A (en) | 1991-07-09 | 1999-11-30 | Dallas Semiconductor Corporation | Portable electronic data carrier |
US5166545A (en) * | 1991-07-10 | 1992-11-24 | Dallas Semiconductor Corporation | Power-on-reset circuit including integration capacitor |
US5297099A (en) * | 1991-07-10 | 1994-03-22 | Dallas Semiconductor Corp. | Integrated circuit with both battery-powered and signal-line-powered areas |
US5325338A (en) * | 1991-09-04 | 1994-06-28 | Advanced Micro Devices, Inc. | Dual port memory, such as used in color lookup tables for video systems |
FR2684206B1 (en) * | 1991-11-25 | 1994-01-07 | Sgs Thomson Microelectronics Sa | REDUNDANCY FUSE READING CIRCUIT FOR INTEGRATED MEMORY. |
JPH0685653A (en) * | 1992-05-06 | 1994-03-25 | Sgs Thomson Microelectron Inc | Receiver circuit provided with bus keeper feature |
US5387826A (en) * | 1993-02-10 | 1995-02-07 | National Semiconductor Corporation | Overvoltage protection against charge leakage in an output driver |
US5486778A (en) * | 1993-03-10 | 1996-01-23 | Brooktree Corporation | Input buffer for translating TTL levels to CMOS levels |
US5469088A (en) * | 1993-03-19 | 1995-11-21 | Advanced Micro Devices, Inc. | Cascade array cell partitioning for a sense amplifier of a programmable logic device |
US5406140A (en) * | 1993-06-07 | 1995-04-11 | National Semiconductor Corporation | Voltage translation and overvoltage protection |
WO1994029961A1 (en) * | 1993-06-07 | 1994-12-22 | National Semiconductor Corporation | Overvoltage protection |
US5534811A (en) * | 1993-06-18 | 1996-07-09 | Digital Equipment Corporation | Integrated I/O bus circuit protection for multiple-driven system bus signals |
US5848541A (en) | 1994-03-30 | 1998-12-15 | Dallas Semiconductor Corporation | Electrical/mechanical access control systems |
US5831827A (en) | 1994-04-28 | 1998-11-03 | Dallas Semiconductor Corporation | Token shaped module for housing an electronic circuit |
US5604343A (en) | 1994-05-24 | 1997-02-18 | Dallas Semiconductor Corporation | Secure storage of monetary equivalent data systems and processes |
US5679944A (en) | 1994-06-15 | 1997-10-21 | Dallas Semiconductor Corporation | Portable electronic module having EPROM memory, systems and processes |
US5528190A (en) * | 1994-10-03 | 1996-06-18 | Delco Electronics Corporation | CMOS input voltage clamp |
US5471188A (en) * | 1994-10-07 | 1995-11-28 | International Business Machines Corporation | Fast comparator circuit |
US5615130A (en) * | 1994-12-14 | 1997-03-25 | Dallas Semiconductor Corp. | Systems and methods to gather, store and transfer information from electro/mechanical tools and instruments |
US5546016A (en) * | 1995-07-03 | 1996-08-13 | Intel Corporation | MOS termination for low power signaling |
US5933021A (en) * | 1996-06-18 | 1999-08-03 | Sun Microsystems, Inc | Noise suppression method and circuits for sensitive circuits |
US5828233A (en) * | 1996-09-12 | 1998-10-27 | Quality Semiconductor, Inc. | Mixed mode CMOS input buffer with bus hold |
IT1296427B1 (en) * | 1997-11-14 | 1999-06-25 | Sgs Thomson Microelectronics | BUS-HOLD INPUT CIRCUIT ABLE TO RECEIVE INPUT SIGNALS WITH VOLTAGE LEVELS HIGHER THAN ITS OWN VOLTAGE |
US6127840A (en) * | 1998-03-17 | 2000-10-03 | International Business Machines Corporation | Dynamic line termination clamping circuit |
US6426905B1 (en) * | 2001-02-07 | 2002-07-30 | International Business Machines Corporation | High speed DRAM local bit line sense amplifier |
US20090219076A1 (en) * | 2008-02-28 | 2009-09-03 | Wenwei Wang | Apparatus, system, and method for grounding integrated circuit outputs |
US20230253398A1 (en) * | 2022-02-10 | 2023-08-10 | Renesas Electronics Corporation | Semiconductor device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4464590A (en) * | 1982-06-23 | 1984-08-07 | National Semiconductor Corporation | Memory system current sense amplifier circuit |
EP0383009A2 (en) * | 1989-01-27 | 1990-08-22 | Kabushiki Kaisha Toshiba | Sense amplifier in use with a semiconductor memory device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3728556A (en) * | 1971-11-24 | 1973-04-17 | United Aircraft Corp | Regenerative fet converter circuitry |
US4140930A (en) * | 1976-07-30 | 1979-02-20 | Sharp Kabushiki Kaisha | Voltage detection circuit composed of at least two MOS transistors |
US4216390A (en) * | 1978-10-04 | 1980-08-05 | Rca Corporation | Level shift circuit |
US4490633A (en) * | 1981-12-28 | 1984-12-25 | Motorola, Inc. | TTL to CMOS input buffer |
-
1990
- 1990-02-15 US US07/480,400 patent/US5027008A/en not_active Expired - Lifetime
-
1991
- 1991-01-21 EP EP91300444A patent/EP0442618B1/en not_active Expired - Lifetime
- 1991-01-21 AT AT91300444T patent/ATE139070T1/en not_active IP Right Cessation
- 1991-01-21 DE DE69119926T patent/DE69119926T2/en not_active Expired - Fee Related
- 1991-02-14 JP JP3021026A patent/JPH06216725A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4464590A (en) * | 1982-06-23 | 1984-08-07 | National Semiconductor Corporation | Memory system current sense amplifier circuit |
EP0383009A2 (en) * | 1989-01-27 | 1990-08-22 | Kabushiki Kaisha Toshiba | Sense amplifier in use with a semiconductor memory device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996027252A2 (en) * | 1995-02-21 | 1996-09-06 | Advanced Micro Devices, Inc. | Line driver and receiver cells for ethernet applications |
WO1996027252A3 (en) * | 1995-02-21 | 1997-02-06 | Advanced Micro Devices Inc | Line driver and receiver cells for ethernet applications |
US5694427A (en) * | 1995-02-21 | 1997-12-02 | Advanced Micro Devices Inc. | Pseudo-AUI line driver and receiver cells for ethernet applications |
CN101571928B (en) * | 2008-04-28 | 2011-12-21 | 软控股份有限公司 | Method for alternating current logic power supply for electronic tag chip |
Also Published As
Publication number | Publication date |
---|---|
DE69119926T2 (en) | 1997-02-06 |
ATE139070T1 (en) | 1996-06-15 |
JPH06216725A (en) | 1994-08-05 |
DE69119926D1 (en) | 1996-07-11 |
EP0442618B1 (en) | 1996-06-05 |
US5027008A (en) | 1991-06-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5027008A (en) | CMOS clamp circuits | |
US5708608A (en) | High-speed and low-noise output buffer | |
US6448812B1 (en) | Pull up/pull down logic for holding a defined value during power down mode | |
JPH0720060B2 (en) | Output circuit device | |
US5877635A (en) | Full-swing buffer circuit with charge pump | |
EP0709964B1 (en) | Programmable pull-up buffer | |
JP3465493B2 (en) | Semiconductor integrated circuit | |
US5894227A (en) | Level restoration circuit for pass logic devices | |
JPH0677804A (en) | Output circuit | |
US4467455A (en) | Buffer circuit | |
US5619153A (en) | Fast swing-limited pullup circuit | |
GB2270598A (en) | BiCMOS circuit with negative VBE protection | |
JPH10135818A (en) | Input circuit | |
JP2758735B2 (en) | Logic circuit | |
JPH0720061B2 (en) | Semiconductor integrated circuit | |
JP3080718B2 (en) | Output buffer circuit | |
JPS6218993B2 (en) | ||
JP3170923B2 (en) | Semiconductor integrated circuit | |
JPS63258115A (en) | Ttl compatible sell for cmos integrated circuit | |
JPS63119323A (en) | Insulated gate type output buffer circuit | |
JP2991743B2 (en) | Substrate potential adjusting device for semiconductor memory device | |
JPH1174772A (en) | Power supply voltage switching circuit | |
JP2836128B2 (en) | Semiconductor storage device | |
KR100318428B1 (en) | Input buffer of semiconductor memory device reduces current consumption | |
JP2934265B2 (en) | Complementary MOS output circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
AK | Designated contracting states |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FR GB GR IT LI LU NL SE |
|
17P | Request for examination filed |
Effective date: 19911125 |
|
17Q | First examination report despatched |
Effective date: 19940715 |
|
GRAH | Despatch of communication of intention to grant a patent |
Free format text: ORIGINAL CODE: EPIDOS IGRA |
|
GRAA | (expected) grant |
Free format text: ORIGINAL CODE: 0009210 |
|
AK | Designated contracting states |
Kind code of ref document: B1 Designated state(s): AT BE CH DE DK ES FR GB GR IT LI LU NL SE |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: IT Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRE;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.SCRIBED TIME-LIMIT Effective date: 19960605 Ref country code: ES Free format text: THE PATENT HAS BEEN ANNULLED BY A DECISION OF A NATIONAL AUTHORITY Effective date: 19960605 Ref country code: LI Effective date: 19960605 Ref country code: DK Effective date: 19960605 Ref country code: CH Effective date: 19960605 Ref country code: NL Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 19960605 Ref country code: GR Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT Effective date: 19960605 Ref country code: BE Effective date: 19960605 Ref country code: AT Effective date: 19960605 |
|
REF | Corresponds to: |
Ref document number: 139070 Country of ref document: AT Date of ref document: 19960615 Kind code of ref document: T |
|
REF | Corresponds to: |
Ref document number: 69119926 Country of ref document: DE Date of ref document: 19960711 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: SE Effective date: 19960905 |
|
ET | Fr: translation filed | ||
NLV1 | Nl: lapsed or annulled due to failure to fulfill the requirements of art. 29p and 29m of the patents act | ||
REG | Reference to a national code |
Ref country code: CH Ref legal event code: PL |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: LU Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 19970131 |
|
PLBE | No opposition filed within time limit |
Free format text: ORIGINAL CODE: 0009261 |
|
STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT |
|
26N | No opposition filed | ||
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: GB Payment date: 20001211 Year of fee payment: 11 |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: FR Payment date: 20010103 Year of fee payment: 11 |
|
REG | Reference to a national code |
Ref country code: GB Ref legal event code: IF02 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: GB Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20020121 |
|
GBPC | Gb: european patent ceased through non-payment of renewal fee |
Effective date: 20020121 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: FR Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20020930 |
|
REG | Reference to a national code |
Ref country code: FR Ref legal event code: ST |
|
PGFP | Annual fee paid to national office [announced via postgrant information from national office to epo] |
Ref country code: DE Payment date: 20030131 Year of fee payment: 13 |
|
PG25 | Lapsed in a contracting state [announced via postgrant information from national office to epo] |
Ref country code: DE Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES Effective date: 20040803 |