JPH0492292A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH0492292A
JPH0492292A JP2209898A JP20989890A JPH0492292A JP H0492292 A JPH0492292 A JP H0492292A JP 2209898 A JP2209898 A JP 2209898A JP 20989890 A JP20989890 A JP 20989890A JP H0492292 A JPH0492292 A JP H0492292A
Authority
JP
Japan
Prior art keywords
data
outputted
pad
state
moss
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2209898A
Other languages
Japanese (ja)
Inventor
Hiroyuki Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2209898A priority Critical patent/JPH0492292A/en
Publication of JPH0492292A publication Critical patent/JPH0492292A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To attain evaluation and sorting with a conventional memory tester even when output bits are many by providing a control signal input part and an output terminal switching part to switch an output terminal by a control signal.
CONSTITUTION: Since an internal signal SWI becomes a low level and MOSs P1,N1,P4 and N4 become a conducting state in the condition that nothing is inputted to an external input pad SW or that the low level is given, the data of data bus lines DB8 and DB9 are outputted to output terminals O8 and O9 through NOR gates 18 and 19 respectively. On the other hand, when a high level is given to the pad SW, since the SWI becomes the high level and MOSs P2,N2,P3 and N3 become the conducting state, the data of the bus lines DB8 and DB9 are outputted to the terminals O9 and O8 through gates 18 and 19 respectively. That is, the data of the DB8 are outputted when the pad is a low state and the data of the DB9 are outputted when the SW is a high state to the terminal O8.
COPYRIGHT: (C)1992,JPO&Japio
JP2209898A 1990-08-08 1990-08-08 Semiconductor integrated circuit device Pending JPH0492292A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2209898A JPH0492292A (en) 1990-08-08 1990-08-08 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2209898A JPH0492292A (en) 1990-08-08 1990-08-08 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH0492292A true JPH0492292A (en) 1992-03-25

Family

ID=16580475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2209898A Pending JPH0492292A (en) 1990-08-08 1990-08-08 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0492292A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006334569A (en) * 2005-06-06 2006-12-14 Nippon Sheet Glass Co Ltd Aqueous solution for separating composite material, method for separating composite material, and constituent materials separated by the method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006334569A (en) * 2005-06-06 2006-12-14 Nippon Sheet Glass Co Ltd Aqueous solution for separating composite material, method for separating composite material, and constituent materials separated by the method

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