JPH0492292A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To attain evaluation and sorting with a conventional memory tester even when output bits are many by providing a control signal input part and an output terminal switching part to switch an output terminal by a control signal. CONSTITUTION:Since an internal signal SWI becomes a low level and MOSs P1,N1,P4 and N4 become a conducting state in the condition that nothing is inputted to an external input pad SW or that the low level is given, the data of data bus lines DB8 and DB9 are outputted to output terminals O8 and O9 through NOR gates 18 and 19 respectively. On the other hand, when a high level is given to the pad SW, since the SWI becomes the high level and MOSs P2,N2,P3 and N3 become the conducting state, the data of the bus lines DB8 and DB9 are outputted to the terminals O9 and O8 through gates 18 and 19 respectively. That is, the data of the DB8 are outputted when the pad is a low state and the data of the DB9 are outputted when the SW is a high state to the terminal O8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated memory circuit device, and more particularly, to a semiconductor integrated memory circuit device having a special number multi-bit output.

[Conventional technology]

Conventionally, as shown in FIG. 2, a semiconductor integrated memory circuit device having a multi-bit output of this type has been configured to input signals from data bus lines DBI to DB9 from an internal circuit to NOR gates 11 to 19.
output terminals 01-o according to the output control signal DOE via
The structure was such that the information was communicated directly to 9.

[Problem to be solved by the invention]

As shown in FIG. 3, some of the above-mentioned conventional semiconductor integrated memory circuit devices having multi-bit output have a ninth output terminal. However, memory testers that are widely used for the evaluation and selection of semiconductor integrated memory circuits usually only have a function that supports 8-bit output. Therefore, such a semiconductor integrated memory circuit device having an output terminal of 8 bits or more has the disadvantage that it cannot be evaluated by a normal memory tester and a special memory tester must be used.

An object of the present invention is to provide a semiconductor integrated circuit that can perform evaluation 1 selection using a conventional memory tester even when there are many output bits.

[Means to solve the problem]

A semiconductor integrated memory circuit device having a multi-bit output according to the present invention includes a control signal input section and an output terminal switching section that switches output terminals according to the control signal.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention. D.B.I.
~DB9 is a data bus line from the internal circuit, and DBI~D
B7 is connected to one input of NOR gates 11-17. Data bus lines DBS and DB9 are P-channel MOS
Transistor P1 and N-channel MOS transistor Nl
, P2 and N2P3 and N3. N through the CMO3) transfer gate constituted by P4 and N4 respectively.
Connected to the input of OR gate 18.19. The other input of the NOR gates 11 to 19 is the output control signal DOE.
are connected, and data is transmitted to output terminals 01-09 when DOE is at low level.

The control signal input section 100 is composed of an external input pad 101 and a high resistance R1 for fixing the external manual SW to a low level in normal use. First, external input pad S
When nothing is input to W or a low level is applied, the internal signal SWI becomes low level.
MOS) transistor PI, N1. P4. Since N4 becomes conductive, the data on data bus lines DBS and DB9 are
The signals are outputted to output terminals 08 and 09 via a NOR gate 1819, respectively.

On the other hand, when a high level is applied to external input pad SW, internal signal SWI becomes high level, and MOS transistor P2. N2. P3. Since N3 becomes conductive, the data on data bus lines DBS and DB9 is transferred to NOR gate 1.
The signals are output to output terminals 09 and 08 via terminals 9 and 18, respectively.

That is, the data of DBS is output to the output terminal 08 when the external input pad SW is in the low state, and the data of DB9 is output when the external input pad SW is in the high state.

As described above, in the semiconductor integrated memory circuit device according to the present invention, by controlling the input level of the external input pad SW, a 9-bit output semiconductor integrated memory circuit device can be operated using only eight output terminals (01 to 08). Evaluation 9 can be selected.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. This embodiment differs from the first embodiment shown in FIG. 1 in the control signal input section. In this embodiment, σ" is applied to the terminal 301 with Vcc + V1 (
V) (However, Vcc is the power supply potential.

The output terminal can be switched by applying a level (vl is a certain specified potential). Here, 302.303
is an electrostatic discharge protection element, and 304 and 305 are CMOS inverters forming a flip-flop.

The gate width of the P-channel transistor of inverter 304 is set to be sufficiently larger than that of the N-channel transistor, and the gate width of the P-channel transistor of inverter 305 is set to be sufficiently smaller than that of the N-channel transistor. moreover,
A capacitor 3 is connected between the output terminal of the inverter 304 and Vcc.
A capacitor 306 is connected between the output terminal of the inverter 305 and GND. Therefore, when the power is turned on, that is, when VCC rises from 0 to a predetermined potential, for example, 5V, the output terminal of the inverter 304 is at a high level.
Since the output terminal of the inverter 305 is always fixed at a low level6, the output signal SWI of the control signal input section 300 is at a high level in the normal state after power is turned on, so that the CMOS transfer gates Pl, Nl and P4
．． N4 is conductive and DBS and DB9 are input terminals 30 and 30.
V on 1. o+V, (V) or more is input, the flip-flop composed of inverters 304 and 305 is inverted, and SWI becomes low, so that the CMOS transfer gate) P2. N2 and P3. N3 conducts and D
BS data is output to 09, and DB9 data is output to 08. Note that the value of Vl is, for example, about 5 to 6V.

In this embodiment, since no new control signal input terminal is required, there are no special restrictions for application to products, and there is an advantage that it is more versatile.

〔Effect of the invention〕

As explained above, the present invention is equipped with an output bit switching function, so that semiconductor integrated memory circuit devices with a large number of output bits can be evaluated and screened using a conventional memory tester. This has the effect of being able to be carried out efficiently without any special investment or constraints.

MO3) transistors, 304, 305...CMOS inverters forming flip-flops, 306.30
7...Capacitor.

Claims (1)

[Scope of Claims] 1. A semiconductor integrated memory circuit device comprising switching means for switching output terminals in accordance with a control signal. 2. The semiconductor integrated memory circuit device according to claim 1, further comprising means for generating said control signal in accordance with a voltage level of an internal signal.