JP2786463B2 - Flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a flip-flop circuit having a set / reset function (hereinafter, referred to as a digital integrated circuit).
FF).

(Conventional technology) A delay type FF (hereinafter, referred to as D-FF) which takes in data in synchronization with a clock signal and outputs it at a predetermined timing
FF) and master / slave type FF (MS-FF)
), And the technology related to them is described in the catalog of Texas Instruments Japan, Inc., catalog "High-speed CMOS Logic Data Book" (1985-3) P.6-4.
8. It is described in 1987, 1987 National Institute of Electronics, Information and Communication Engineers Semiconductor and Materials Division National Convention 200, "Study of GaAs DCFL Flip-Flop Circuits" by Shikata, Tanaka and Akiyama, pp. 1-201.

FIG. 2 is a circuit diagram showing one configuration example of a conventional D-FF with set / reset described in the above-mentioned document.

This D-FF includes transfer gates 1, 4, 5, 8, 9, 10, and 2-input NAND gates 2, 3, 6, 7, and inverters 11, 12, 13, and 14. In FIG. 2, CLK is an external clock signal, C is an internal clock signal generated from the clock signal CLK, and its inverted clock signal.
▼ is a clear signal, D is input data, ▼ is a preset signal, Q is output data, and is inverted output data.

 Next, the operation will be described.

When the high-level (hereinafter, referred to as “H”) clock signal CLK is applied, the “H” clock signal C and the opposite low-level (hereinafter, referred to as “L”) are supplied through the inverters 13 and 14.
The inverted clock signal of
1, 8, and 10 are turned on, and the transfer gates 4, 5, and 9 are turned off. At this time, the “H” preset signal ▲
When the input signal D is “H”, the output of the NAND gate 2 becomes “L” and the output of the NAND gate 3 becomes “H” when the input signal D is “H”.

Next, when the clock signal CLK becomes “L”, the transfer gates 1, 8, and 10 are turned off, and the transfer gates 4, 5, and
9 is turned on, the output of the NAND gate 6 becomes “H”,
The output of the gate 7 becomes “L” and the inverter 11 outputs “H”
, And inverted output data of "L" from the inverter 12 are output.

Therefore, in this D-FF, the preset signal ▲ ▼
While the clear signal ▲ ▼ is “H”, the clock signal
An operation of outputting the input data D input while the CLK is “H” and outputting the output data Q when the clock signal CLK becomes “L” is performed.

Here, the “L” preset signal ▲ ▼ and “H”
When the clear signal ▲ ▼ is input, the clock signal
The inverted output data becomes "L" regardless of "H" and "L" of the CLK and the input data D. Also, the preset signal ▲
When ▼ becomes “H” and the clear signal ▲ ▼ becomes “L”, the output data Q becomes “L” regardless of “H” and “L” of the clock signal CLK and the input data D. Thus, the D-FF with set / reset operates by the preset signal ▼ and the clear signal ▼.

(Problems to be solved by the invention) However, the FF with set / reset having the above configuration has the following problems.

The circuit of FIG. 2 requires two-input gates such as two-input NAND gates 2, 3, 6, and 7 to have a set / reset function. Since the operation speed of the two-input gate is lower than that of the one-input gate, there is a problem that the maximum operation speed of the D-FF is lower.

In order to solve this problem,
It is conceivable to add a set / reset function to the MS-FF. That is, the MS-FF described in the above document is composed of a transfer gate for inputting data that is turned on and off by a clock signal, and a latch circuit including an inverter for temporarily holding data input through the transfer gate. The configured unit FF is a circuit in which two stages are cascaded. By adding a set / reset function to this MS-FF, it is possible to solve the problem of the slow operation speed of the circuit shown in FIG. 2, but in order to provide the set / reset function, a gate circuit or the like is required. However, depending on the configuration of the additional circuit, there is a possibility that the operation speed may be reduced, and it is difficult to obtain an accurate FF with set / reset while maintaining high-speed operation.

An object of the present invention is to provide an FF with an accurate set and / or reset that has a high operation speed.
And a FF with a set and / or reset that solves the difficulty in configuring the FF.

(Means for Solving the Problems) In order to solve the above problems, a first aspect of the present invention provides a first transfer gate that performs on / off operations by a clock signal to input input data; A second transfer gate that is turned off to input inverted input data having a phase opposite to that of the input data, an input side connected to a first node on the output side of the first transfer gate, and an output side connected to the second transfer gate A first inverter connected to a second node on the output side of the first inverter, and a second inverter connected on the input side to the output side of the first inverter and the output side connected to the input side of the first inverter, respectively And a third inverter for output connected to the first node, and a fourth inverter for output connected to the second node. Te,
A transfer gate for set or reset, which is turned on / off by a set signal or reset signal, is connected between the first and second nodes and a power supply potential.

According to a second aspect of the present invention, in the FF, a plurality of set and reset transfer gates that are turned on and off by the set signal and the reset signal are provided between the first and second nodes and a power supply potential, respectively. Connected.

(Operation) According to the first and second aspects of the present invention, since the FF is configured as described above, the set or reset transfer gate receives input data and inverted input data according to the set signal or reset signal applied thereto. Regardless of whether the clock signal is "H" or "L", the first and second nodes are forcibly set to the power supply potential to set or reset. Thus, a high-speed flip-flop operation having a set or reset function can be performed. Therefore, the above problem can be solved.

FIG. 1 is a circuit diagram of a D-FF showing an embodiment of the present invention.

This D-FF is a cascade connection of two units FF20, 40 having the same circuit configuration. The unit FF20 in the former stage is composed of first, second, and second field-effect transistors (hereinafter, referred to as FETs).
3, 4th, 5th, 6th transfer gates 21-26 and 1st,
2, and third and fourth transfer gates 31 to 34 are provided. The first and second transfer gates 21 and 22 are turned on and off by a clock signal C. The drain of the first transfer gate 21 is connected to the input data D, and the source is connected to the node N1. . The second transfer gate 22 has a drain for inverted input data,
The sources are respectively connected to the nodes N2. First
Is connected to a first power supply potential (for example, "H" power supply potential V _D ) via a third transfer gate 23 which is turned on and off by a set signal S, and is also reset by a reset signal R. It is connected to a second power supply potential (for example, a ground potential V _G ) via a fourth transfer gate 24 that turns on and off. The second node N2 is set signal on the S, with through fifth transfer gate 25 off operation is connected to the ground potential V _G, a sixth transfer gate 26 to turn on, off operation by the reset signal R It is connected to the power supply potential V _D through. First and second inverters 31 and 32 are connected between the first and second nodes N1 and N2.
Further, a third inverter 33 for output is connected to the first node N1, and a fourth inverter 34 for output is connected to the second node N2.

The unit circuit 40 at the subsequent stage has the same FE as the unit circuit 20 at the previous stage.
It includes first, second, third, fourth, fifth, and sixth transfer gates 41 to 46 made of T, and first, second, third, and fourth inverters 51 to 54. On the output side of the inverters 33 and 34 in the preceding stage,
1st, 2nd on / off operation by inverted clock signal
Of the transfer gates 41 and 42 are connected to each other, and their sources are connected to the nodes N3 and N4, respectively. The node N3 is connected to the ground potential via the third transfer gate 43 which is turned on and off by the set signal S.
In addition to being connected to V _G , it is connected to the power supply potential V _D via a fourth transfer gate 44 that is turned on and off by a reset signal R. Node N4 is turned on by a set signal S, via a fifth transfer gate 45 off operation is connected to the power supply potential V _D, is connected to the ground potential V _G via a transfer gate 46 of the sixth . First and second inverters 51 and 52 are connected between the nodes N3 and N4. A third inverter 53 for outputting output data Q is connected to the node N3, and an inverted output is connected to a node N4. A fourth inverter 54 for data output is connected.

 Next, the operation will be described.

First, when the set signal S and the reset signal R are "L", the transfer gates 23 to 26 and 43 to 46 are turned off. Therefore, when the clock signal C is "H", the input data D and the inverted input data are output. Are held by the inverters 31 and 32 via the transfer gates 21 and 22. When the clock signal C becomes “L” and the inverted clock signal becomes “H”, the transfer gates 41 and 42 are turned on, and the data held in the inverters 31 and 32 is transferred to the transfer gates 41 and 42 and the inverter 5.
The data is output as output data Q and inverted output data through 3, 54, and operates as D-FF.

When the set signal S is “H” and the reset signal R is “L”,
Since the transfer gates 23, 25, 43, and 45 are turned on, regardless of the clock signal C, the inverted clock signal, the input data D, and the “H” and “L” of the inverted input data,
The nodes N1 and N4 become "H", the nodes N2 and N3 become "L", the output data Q becomes "H", and the inverted output data becomes "L".

When the set signal S becomes "L" and the reset signal R becomes "H", the transfer gates 24, 26, 44, 46 are turned on, so that the input data D, the inverted input data, the clock signal C, and the inverted signal are output. Regardless of the clock signal “H” and “L”, the nodes N1 and N4 become “L” and the nodes N2 and N3 become “H”,
The output data Q is reset to "L" and the inverted output data is set to "H".

In this embodiment, an inverter that is a one-input gate is used without using a two-input gate such as a two-input NAND gate.
Since the D-FF with set / reset is constituted only by 31 to 34 and 51 to 54 and the transfer gates 21 to 26 and 41 to 46, high-speed flip-flop operation can be expected. Also, this D
-In terms of the process for manufacturing FETs used in FFs, the noise margin can be reduced compared to the one using multiple input gates because it is composed only of an inverter that is a one-input gate and a transfer gate, An allowable value of variation of each element, that is, a process margin is widened, and a high yield can be expected.

Further, the node N1, N3 and N2, both N4, the power supply potential V _D and the ground potential V _G via a transfer gate 23～26,43～46
Connected to the transfer gates 23 to
Even if the nodes 26 and 43 to 46 are turned on and off, the nodes N1 to N4
The inverters 33, 34, 53, 54 connected to the inverters can greatly reduce the fluctuations in the output level, and can reduce the time difference between the two-phase signals of the output data Q and the inverted output data until the output signal reaches the set or reset level. FF with faster set or reset, which can be almost 0
Can be realized.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example, there are the following modifications.

(A) In FIG. 1, if only the set function is required, the transfer gates 24, 26, 44, 46 for reset may be omitted. At this time, transfer gate for set
Of 23,25,43,45, transfer gate 23 or 25
Even if either one of 43 and 45 is omitted, almost the same set operation can be performed. However, for example, when the transfer gates 25, 45 are omitted, the transfer gates 23, 43
It is conceivable that the operation speed of the nodes N2 and N4 is lower than that of the nodes N1 and N3 connected. However, when only the output data Q is used, the operation of the nodes N2 and N4 is practically The reduction in speed is not a problem.

Similarly, if only the reset function is required, the transfer gates 23, 25, 43, 45 for setting may be omitted.
At this time, as described above, of the transfer gates 24, 26, 44, and 46 for resetting, the transfer gates 24 or 26 are used.
And even if one of 44 and 46 is omitted, almost the same reset operation is possible.

(B) In FIG. 1, another set or reset transfer gate that is turned on and off by another set signal or reset signal is a transfer gate.
By connecting in parallel with 23 to 26 and 43 to 46, it is possible to operate with two or more types of set signals or reset signals. In this case, since a two-input gate is not used, the operation speed can be improved.

(C) In the circuit of FIG. 1, one of the units FF20
Alternatively, only 40 can be used as a latch circuit or the like.

(D) The transfer gates 23 to 26 and 43 to 46 may be constituted by other switching elements such as bipolar transistors.

(Effects of the Invention) As described in detail above, according to the first and second inventions, FFs with set or reset are provided only by one-input inverters and transfer gates without using two-input gates. Thus, an accurate high-speed flip-flop operation with a simple structure can be expected. In addition, since only one input gate and transfer gate are used, a process margin due to device variation is widened, and a high yield can be expected.

Further, since both the first and second nodes are connected to the high or low potential power supply potential via the set or / and reset transfer gate, the transfer gate is turned on. , Even when turned off, the output level variation can be made very small by the output third and fourth inverters connected to the first and second nodes, and the output signal becomes the set or reset level. The time difference between the two-phase signals of the output data up to and the inverted output data can be reduced to almost 0,
Faster FF with set or reset can be realized.

[Brief description of the drawings]

FIG. 1 shows an embodiment of the present invention.
-FF circuit diagram, Figure 2 shows a conventional D with set / reset
It is a circuit diagram of -FF. 20, 40: unit FF, 21 to 26: first to sixth transfer gates, 31 to 34: first to fourth inverters, 41 to 46
...... First to sixth transfer gates, 51 to 54 ... First
To the fourth inverter, C clock signal, inverted clock signal, D input data, inverted input data, N1 / N3, N2 / N4, first and second nodes, R Reset signal, S: Set signal, Q: Output data,
… Inverted output data, V _D … Power supply potential, V _G … Ground potential.

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-63-103511 (JP, A) JP-A-59-188227 (JP, A) JP-A-59-100614 (JP, A) JP-A-59-1984 17719 (JP, A) JP-A-62-252211 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03K 3/037 H03K 3/356

Claims (2)

(57) [Claims] A first transfer gate for inputting input data by performing on / off operations in response to a clock signal; and a first transfer gate for performing on / off operations in response to the clock signal to input inverted input data having a phase opposite to that of the input data. 2 transfer gates, and the input side is a first transfer gate output side of the first transfer gate.
A first inverter whose output side is connected to a second node on the output side of the second transfer gate, an input side being an output side of the first inverter, and an output side being the first inverter. The second connected to the input side of
And a third inverter for output connected to the first node, and a fourth inverter for output connected to the second node. A flip-flop circuit, wherein a set or reset transfer gate that is turned on and off by a reset signal is connected between the first and second nodes and a power supply potential. 2. The flip-flop circuit according to claim 1, wherein a plurality of set and reset transfer gates that are turned on and off by the set signal and the reset signal are connected to the first and second nodes and a power supply potential. And a flip-flop circuit connected between the flip-flop circuits.