JPS63103511A - Flip-flop circuit - Google Patents

Abstract

PURPOSE:To operate the titled circuit by an input clock pulse at a high frequency normally by adding two basic flip-flop circuits comprising two inverter circuits connecting input and output mutually to an amplification inverter circuit and a flip-flop circuit comprising a transfer gate using a FET. CONSTITUTION:A critical pulse of the circuit starts from a data input terminal D through a FET 1, an amplification inverter 5 via a node N11, through a FET 7 via a node N13, through an amplification inverter 11 via a node N15 and reaches an output terminal Q and the highest operating frequency of the circuit depends on the propagation delay time characteristic of the FET 1, the amplification inverter 5, the FET 7 and the amplification inverter 11. The fanout number of the FET and the inverter for the critical pulse is less than that of the NOR gate of a conventional circuit and the propagation delay time is decreased. Thus, the highest operating frequency is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) This invention relates to flip-flops, and particularly to data flip-flops.

(Prior Art) Conventionally, this type of flip-flop circuit has been described in the document "Design of Flip-Flop Circuit and Counting Circuit" (1975).
2003) Tokyo Denki University Press, pages 84 to 89.

FIG. 3 is a circuit diagram for explaining a general D-flip-flop circuit, which is composed of six NOR gates 31-36. CL is a clock pulse signal input terminal (hereinafter referred to as a clock terminal), b is a data pulse input terminal and an opposite phase data pulse input terminal (hereinafter referred to as a data terminal), and Q and d are respectively They are an output terminal and a reverse phase output terminal, respectively.

Figure 4 shows the operation of a T-flip-flop circuit in which the output terminal Q, the data terminal D1, the negative phase output terminal, and the negative phase data terminal are respectively connected as shown by dotted lines in the circuit shown in Figure 3. It is a time chart for explanation. The horizontal axis is time t.

~t5, and the vertical axis is the clock terminal CL shown in FIG.
, the logic levels of the nodes N1 to N4, the output terminal Q, and the negative phase output terminal 6. This will be explained below using the drawings.

As shown in FIGS. 3 and 4, at time to, the black terminal CL is at a high level (hereinafter referred to as H), the output terminal Q is at a low level (hereinafter referred to as "H"), and the negative phase output terminal 6 is at a high level. Suppose that At this time, node N2. N3 is connected because the clock terminal CL is H, and the node N1
is H because the output terminal Q1 and the node N2 are both, and the node N4 is H because the negative phase output terminal d is I().

The circuit is stable in this state. Next, at time 11, when the clock terminal CL changes to L, the node N2 becomes the clock terminal CL.
And since node N3 is L, it is determined by node N1,
Since node N) is H at time 2, node N2 is set. Similarly, node N3 changes to H since node N4 is L at time t1. The node N3 of the negative phase output terminal Q is H.
As a result, the output terminal Q becomes H because the node N2 and the opposite phase output terminal point have changed to L. N1 changes to L because the output terminal Q is H, and the node N
4 is because node N3 is H. The circuit becomes stable in this state. Subsequently, at time t2, when the clock terminal CL becomes H, both nodes N2 and N3 become L, but as a result, the output terminal Q and the negative phase output terminal do not change.

Node N1 remains L, but node N4 becomes node N3
Since the negative phase output terminals are both connected, it becomes H.

The circuit becomes stable in this state. Next, at time t3, when the clock terminal CL becomes L, the node N2 is determined by the node N1, and since the node N1 is set, the node N2 becomes H. Node N3 is determined by node N4, and node N4
is H, so node N3 becomes L. The output terminal Q becomes L because the node N2 becomes H, and the negative phase output terminal d becomes H because the output terminals Q and N3 are both connected. The node N1 remains as if the node N2 were to become H, and the node N4 was as if the negative phase output terminal d had become H. The circuit is stable in this state. Subsequently, at time t4, when the clock terminal CL becomes H, the nodes N2 and N3 become L. As a result, the output terminal Q and the negative phase output terminal d do not change. The node N becomes H because the output terminal Q is L and the node N2 becomes L. The node N4 remains at the negative level since the negative phase output terminal chamber is at H level. At time t4, the circuit becomes stable as it is in the same state as time to.

As described above, the T-flip-flop circuit is used as a frequency dividing circuit that performs a 1/2 frequency dividing operation in which the output terminal Q repeats switching between L and H when the clock terminal CL falls. The critical signal of this circuit is, for example, when the node N1 is H, the NOR dirt 3 is connected from the node N1.
2, passes through node N2, passes through NOR gate 35, passes through NOR gate 36, passes through NOR gate 34, and reaches node N44C, and the maximum operating frequency of this circuit is determined by the delay time characteristics of this portion.

(Problem to be solved by the invention) However, in the flip-flop circuit as described above,
The NOR gate 32 and the NOR dart 33 have a large fan-out number of 3, and these NOR gates have a large propagation delay time. In addition, the number of NORr stages is large, and the delay time of the entire circuit becomes large.

For these reasons, high frequency input clocks! There was a problem in that the frequency division operation did not work properly in the RUS.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a flip-flop circuit that can operate normally with high frequency input clock pulses.

(Means for Solving the Problems) In order to solve the problems mentioned above, the present invention consists of two inverter circuits connected to each other in a feedback manner with the output of one inverter circuit being the input of the other inverter circuit. A flip-flop circuit, a field effect transistor (hereinafter referred to as FET) and an amplifying inverter circuit connected to at least one input and output of the basic flip 20-tub circuit, respectively, are provided, and an input signal passes through the FET to the basic flip-flop circuit. A clock pulse signal is input to the flip-flop circuit, and a clock pulse signal is input to the gate of this FET, and the output of the basic flip-flop circuit is outputted via the amplifying inverter circuit.

(Function) As described above, according to the present invention, the basic structure is composed of an amplifying inverter circuit and a flip-flop circuit using a transfer dart using FET, and two inverter circuits whose inputs and outputs are interconnected. Since the flip-flop circuit is configured by adding two flip-flop circuits, the propagation delay time of the critical path that determines the maximum operating frequency of the flip-flop circuit can be reduced.

(Example) FIG. 1 is a circuit diagram of a flip-flop circuit that does not provide a detailed explanation of the present invention, and FIG. 2 is a time chart for explaining the operation of the flip-flop circuit shown in FIG. 1. . This will be explained below using the drawings.

The flip-flop circuit shown in FIG. It has a phase output terminal point, between which two basic clip-flop circuits each consisting of two inverter circuits, four amplification inverter circuits, and four FETs are connected.

The data input terminal is connected to the drain of FET 1,
The reverse phase data input terminal is connected to the drain of FET 2. The source of FET 1 is connected to the input of inverter 3 and the input of amplifying inverter 5, which constitute the first basic flip-flop circuit, and the source of FET 2 is connected to the input of inverter 4, which also constitutes the first basic flip-flop circuit. , also connected to the input of the amplifying inverter 6. The output of inverter 3 is connected in feedback to the input of inverter 4, and the output of inverter 4 is connected in feedback to the input of inverter 3. The output of the amplification inverter 5 is an FET
The output of the amplifying inverter 6 is connected to the drain of the FET 8. The source of FET 7 is connected to the input of inverter 9 that constitutes the second basic 797767071 circuit and the input of amplification inverter 11, and the source of FET 8 is connected to the input of inverter 9 that constitutes the second basic flip-flop circuit. Similarly to the input of the inverter 10, it is connected to the input of the amplifying inverter 12. The output of inverter 9 is connected in feedback to the input of inverter IO, and the output of inverter 10 is connected in feedback to the input of inverter 9. The output of the amplifying inverter 11 is connected to the output terminal Q, and the output of the amplifying inverter 12 is connected to the negative phase output terminal d.

The clock pulse input terminal CL is connected to the gate of FET 7 and the gate of FET 8, and the reverse phase clock pulse input terminal CL is connected to the gate of FET 1 and the gate of FET 2.
- Connected to

Next, the operation of this flip-flop circuit is explained by converting the output of the amplifying inverter 11 into a FET
The second circuit is connected to the drain of FET 2, and the output of amplifier input 9-12 is connected to the drain of FET 1.
This will be explained using figures.

In FIG. 2, the horizontal axis indicates the time to-t5, and the vertical axis indicates the clock pulse input terminal CL shown in FIG.
The logic levels of the output terminal Q and the negative phase output terminal d are determined.

As shown in FIGS. 1 and 2, at time t. , clock terminal CL is L1, reverse phase clock terminal CL is H1 node Nll, H1 node N12 is L1 node N13, L1 node N14 is H1 node N15, node N16 is H1 output terminal Q, L1 reverse phase output terminal d is Suppose it is H. At time t1, when the clock terminal becomes H1 and the reverse phase clock terminal becomes negative, FET 1 and FET 2 become non-conductive, and FET 7 and FET 8 become conductive.
The node N15 becomes H1 and the node N16 becomes L, so the output terminal Q becomes H1 and the negative phase output terminal becomes L. Node Nil
~N14 does not change. Next, at time t2, the clock terminal C
When L becomes L1 and reverse phase clock terminal CL becomes H, FET
1 and FET 2 become conductive, and FET 7 and FET
8 becomes non-conductive, node N11 becomes non-conductive, and node N
12 becomes H, and node N13 becomes I(,)-de N14 becomes L. Node N15. N16, output terminal Q, and negative phase output terminal Q do not change. Subsequently, at time t3, the clock terminal CL becomes H1, and the reverse phase clock terminal CL becomes L, the node N15 becomes L1, the node N16 becomes H, and the output terminal Q becomes L.
1 The negative phase output terminal d becomes H. Nodes Nil to N14 do not change. Subsequently, at time t4, the clock terminal CL becomes L1.
When the reverse phase clock terminal CL becomes H, the node Nil becomes H1
Node N12 becomes L, node N1.3 becomes L1, node N14 becomes H. Node N75. N13, output terminal Q, and negative phase output terminal d do not change. At time t4, time to
return to the same state.

The critical parts of this circuit start from the data input terminal, pass through FET 1, pass through node Nil, pass through amplifying inverter 5, pass through node N13, and then connect to FET.
7, node N15, amplification inverter 11, and output terminal Q. Due to the propagation delay time characteristics of FET 1, amplification inverter 5 (FET 7, and amplification inverter 11), the maximum operating frequency of this circuit is Decide.

As explained in detail above, in the flip-flop circuit of the embodiment of the present invention, the critical-nos FET and inverter have a smaller fan-out number than the NOR gate of the conventional circuit and can shorten the propagation delay time, so the maximum operating frequency can be increased. be able to. For example, in a computer simulation, it was confirmed that the circuit according to the embodiment of the present invention operates at a frequency 1.5 times that of a conventional circuit. Additionally, compared to conventional circuits, there is greater freedom in setting the immobility of the amplification inverter circuit for the inverter circuit that makes up the basic flip-flop circuit, making it easier to achieve more appropriate operation. be.

In the embodiment of the present invention, the inverter circuits 3 and 4 and the inverter circuits 9 and 9 constituting the basic flip-flop circuit are
10 includes FETs J, 2, amplifying inverter circuits 5, 6, and FETs 7, ! ? and amplification inverter circuits 11 and 12 are provided, but D-7 Linop 7
When used as a
When used as a flip-flop, the FETs 2 and 8 and the amplifying inverter circuit 6°11 may not be provided.

Furthermore, the inputs of the amplification inverter circuits 5.6 and 11.12 are connected to the inputs of inverter circuits 3.4, 9 and 1θ, respectively, which constitute the basic flip-flop circuit.
The inputs of the amplifying inverter circuits 5, 6, 11.12 may be connected to the outputs of the inverter circuits 3, 4, 9.10, respectively.

(Effects of the Invention) As explained in detail above, according to the present invention, the inverter circuit is configured by an amplifying inverter circuit and a flip-flop circuit using a transfer gate using an FET, and two inverter circuits whose inputs and outputs are interconnected. Since the flip-flop circuit is configured by adding two basic flip-flop circuits, it is possible to reduce the critical/Ps propagation delay time that determines the maximum operating frequency of the flip-flop circuit, and therefore the maximum operating frequency can be increased. A flip-flop circuit that performs highly and appropriately can be obtained.

[Brief explanation of the drawing]

1 and 2 are flip-flop circuit diagrams for explaining the present invention in detail and time charts for explaining its operation, and FIGS. 3 and 4 are conventional flip-flop circuit diagrams and their It is a time chart for explaining the operation. D...Data input terminal, b...Negative phase data input terminal, CL...Clock pulse input terminal, CL...Negative phase clock pulse input terminal, Q...Output terminal, d...
Negative phase output terminal, 1, 2, 7.8...FET, J, 4,
9゜10... Inverter circuit, 5, 6, 11.12.
...Amplification inverter circuit, N1-N4, N
11~N16... Node, 31~36 ・
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Claims (1)

[Scope of Claims] 1) A basic flip-flop circuit consisting of two inverter circuits, in which the output of one of the inverter circuits is fed back as an input to the other inverter circuit, and at least one input of the basic flip-flop circuit. and a field effect transistor and an amplifying inverter circuit connected to the output, respectively, an input signal is input to the basic flip-flop circuit via the field effect transistor, and a clock pulse signal is input to the gate of the field effect transistor. A flip-flop circuit, wherein an output of the basic flip-flop circuit is outputted via the amplification inverter circuit.