JPH03228297A - Shift register circuit - Google Patents

Abstract

PURPOSE:To attain the fast working and a small structure for a shift register by using the rear stage part of two pairs of latch circuits connected in series and forming a single bit as a 2-input NOR gate where a clock is used as one of both inputs. CONSTITUTION:Each of register parts 1a1 - 1a5 consists of a latch circuit L1 where a transfer gate TG, an inverter 2, and a clocked inverter 3 are cascaded in a parallel circuit and a NOR gate 4 where a clock signal phi is inputted via one of two input terminals. In other words, the rear stage part of two pairs of latch circuits connected in series forming a single bit is used as a NOR gate 5. When an input signal DIN is inputted, the data of an H level is shifted to a higher rank bit from a lower rank bit at the rise and fall time points of a clock phi. This shift speed is doubled. Thus the faster working and a small structure are attained for a shift register.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a shift register circuit, and particularly to a shift register circuit for transferring 1-bit data.

[Conventional technology]

FIG. 5 is a circuit diagram of an example of a conventional shift register circuit.

This shift register circuit has a 4-stage register section l in which two latch circuits L1 and L2 are cascade-connected, in which a transfer gate (TG) having an 0MO8 structure, an inverter 2, and a clocked inverter 3 are cascade-connected.

1 to IC4, each bit of signal S1. ~S4. is outputting.

As shown in Figure 6, when inputting data D,
At each rising point of clock signal φ, "H" level data is shifted to the upper bit one bit at a time.

[Problem to be solved by the invention]

In the conventional shift register circuit described above, data is shifted from the lower bit to the upper bit at the rising edge of the clock φ.

That is, only one bit of data can be shifted in one cycle of clock φ.

Therefore, when shifting data at high speed, there is a drawback that the clock φ must also be input at the high speed period.

Further, when the number of bits is 2, there is a drawback that the number of MOS transistors forming the circuit is large, making it difficult to miniaturize the circuit.

An object of the present invention is to provide a compact shift register circuit having high-speed characteristics.

[Means to solve the problem]

The shift register circuit of the present invention supplies the input signal from the lower bit to the source of the transfer gate, connects the drain to the input terminal of the inverter and the output terminal of the clocked inverter which are arranged in anti-parallel, and connects the input signal from the lower bit to the output terminal of the inverter. and the input end of the clocked inverter are connected to one input end of a two-input logic gate, a clock signal is input to the other input end, and the output end of the two-input logic gate is connected to the input end of the upper bit. It is constructed by cascading multiple register sections.

[Example] The shift register circuit of this example includes each register section 1a+
1.5 is composed of a latch circuit L1 in which a transfer gate TG and a parallel circuit of an inverter 2 and a clocked inverter 3 are connected in cascade, and a NOR gate 4 whose input terminal receives a clock signal φ.

That is, two sets of serially connected latch circuits Ll-L forming the conventional register section IC+ shown in FIG.
In the embodiment of the present invention, the portion L2 subsequent to 2 is the NOR gate 5.

~FIG. 2 is a timing diagram of each signal for explaining the operation of the circuit of FIG. 1.

When the input signal DIN is input, "H" level data is shifted from the lower bit to the upper bit at each rise and fall of the clock φ.

Here, the shift speed is twice that of the conventional one.

FIG. 3 is a circuit diagram of a second embodiment of the invention.

In this embodiment, the shift register section 1.1 in FIG.
The shift register circuit of the first embodiment is the same as the shift register circuit of the first embodiment except that the NOR gate 4 of .about.1.5 is replaced with a NAND gate 5.

In this shift register circuit, as shown in FIG.
Since the clock signal φ of the same phase is input to the AND gate 5 and the transfer gate (TG), one bit of "L" level data is transferred from the lower bit to the upper bit at each rising and falling point of the clock. Shifting to high speed.

〔Effect of the invention〕

As explained above, the present invention enables the latter part of two series-connected latch circuits constituting one bit of a conventional shift register to be connected to a two-input NOR gate or a two-input NOR gate with a clock as one input. By using an input NAND gate, data can be shifted from the lower bits to the upper bits at the rising and falling points of the clock.

That is, data can be shifted by two bits in one clock cycle, and the data shift speed can be increased.

In addition, compared to the latch circuits that make up conventional shift register circuits, a 2-input NOR gate or a 2-input NAND gate has 4 fewer elements when calculated at the transistor level, so the second reason is that the number of elements can be reduced. effective.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a timing diagram of each signal to explain the operation of the circuit of FIG. 1, and FIG. 3 is a circuit diagram of a second embodiment of the present invention. An example circuit diagram, FIG. 4 is a timing diagram of each signal to explain the operation of the circuit in FIG. 3, FIG. 5 is a circuit diagram of an example of a conventional shift register circuit, and FIG. 6 is a timing diagram of each signal for explaining the operation of the circuit of FIG. 5. FIG. 1ml~1a5+14II~Ibs...Shift register section, 2...Inverter, 3...
・Clocked inverter, 4...2 input NOR
Gate, 5... river, 2 input NAND gate, DIN...
...input signal, Do...group output signal, L+,
L 2...Latch circuit %Sl□~s5゜Sl
b~S5b...Hit signal, TG...
Transfer gate, φ...Clock signal.

Claims (1)

[Claims] The input signal from the lower bit is supplied to the source of the transfer gate, the drain is connected to the input terminal of the inverter and the output terminal of the clocked inverter which are anti-parallel, and the output terminal of the inverter and the input terminal of the clocked inverter are connected. A plurality of register sections are cascaded in multiple stages, in which the terminal is connected to one input terminal of a two-input logic gate, a clock signal is input to the other input terminal, and the output terminal of the two-input logic gate is connected to the input terminal of the upper bit. A shift register circuit characterized in that: