JP3031173B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device forming a central data processing device, a peripheral device, a memory device and the like which are components of a computer, and more particularly to a parallel processing computer, a semiconductor integrated circuit device for space, and the like. And a semiconductor integrated circuit device requiring high reliability and high performance.

[0002]

2. Description of the Related Art In recent years, the performance of computers has been remarkably improved. As a typical circuit technology that supports this progress, fully complementary static CMOS (Complementary metal
xidesemiconductor) circuit. Compared to bipolar circuits, it consumes less power and is more highly integrated. As is well known, a completely complementary static CMOS circuit includes a P-type logic block composed of P-type MOS transistors and an N-type logic block.
N-type logic blocks composed of MOS transistors are connected in series, and the two logic blocks operate complementarily. The rise time of the output signal depends on the characteristics of the PMOS transistor, and the fall time of the output signal depends on the characteristics of the NMOS transistor. In general, the gain coefficient β of a PMOS transistor is smaller than the gain coefficient β of an NMOS transistor. Therefore, when the channel width and the channel length of the PMOS transistor and the NMOS transistor are designed to be equal, the rise time of the output signal is later than the fall time. Conversely, in order to make the rise time and fall time of the output signal equal, the channel width of the PMOS transistor must be larger than the channel width of the NMOS transistor, which causes an increase in input capacitance and an increase in area.

As an example of a circuit for solving the problem of the completely complementary type static CMOS circuit, a CMO
S Domino logic circuit (RHKRAMBECK, CHARLES
M.LEE and HUNG-FAI STEPHEN LAW, “High-Speed Com
pact Circuits with CMOS, "IEEE JOURNAL OF SOLID-S
TATE CIRCUITS, VOL. SC-17, NO. 3, JUNE 1982). FIG. 9 shows an example of a CMOS domino circuit. The CMOS domino circuit has N
This is a dynamic circuit in which logic is constituted only by MOS transistors. Therefore, the signal propagation delay is NM
It depends on the characteristics of the OS transistor. There is no problem of an increase in delay time due to a P-type logic block which is a problem in a completely complementary static CMOS circuit. Further, since the logic is constituted only by the N-type logic block, the input capacitance and the parasitic capacitance inside the circuit are small, so that the operation speed is high and the area is small.

However, the CMOS domino circuit has the following three problems. First, since the CMOS domino circuit is a dynamic circuit, it is susceptible to α-ray noise. FIG. 10 shows a circuit diagram and operation waveforms. The CMOS domino circuit performs a precharge operation while a clock signal input to the circuit is at a low level, and logic propagates during a high level. When the input signal is at the low level during the logic determination period in which the clock signal is at the high level, the node A is at the high level and the charge at the point A is dynamically held. At this time, when an α ray hits the drain of the N-type transistor 100, the charge at the point A is discharged, and the potential level at the point A decreases.
Since there is no path for charging the discharged electric charge, the potential level once lowered will not return to the original level, and will cause a malfunction.

Second, since the CMOS domino circuit is a dynamic circuit, it is susceptible to leak current noise. When the input signal is at the low level during the logic determination period in which the clock signal is at the high level, the node A is at the high level and the charge at the point A is dynamically held. At this time, N
The charge at point A is discharged by the leak current via the type transistor, and the potential level at point A drops. Since there is no path for charging the discharged electric charge, the potential level once lowered will not return to the original level, and will cause a malfunction.

A third problem is the charge redistribution shown in FIG. The capacitance at the node A of the CMOS domino circuit is represented by CA,
It is assumed that the capacitance at the node B is CB. In the logical judgment period 1,
Assuming that the input signal A is at the low level and the input signal B is at the high level, the potential at the node A is at the high level “Vdd”, and the potential at the node B is at the low level “0 V”. Since the NMOS transistors 101 and 102 are off during the precharge period, the potential at the node A is at the high level “Vd
d ”and the node B remain at“ 0 V. ”Then, when the logic determination period 2 starts and the input signal A goes high, N
MOS transistor A turns on, and node A and node B
The electric charge is redistributed between the points A and B, and the potentials at the points A and B become “(CA / (CA + CB)) Vdd”. When the capacitances of CA and CB are substantially equal, the potentials at points A and B become about "(1/2) Vdd", which causes a malfunction.

As a means for solving the problems of the α-ray noise, the leak current and the charge redistribution which are the problems of the CMOS domino circuit, a method of adding a feedback pull-up PMOS transistor 103 shown in FIG. 12 has been proposed. The point A of the dynamic node is weakly pulled up by the feedback pull-up PMOS 103, thereby compensating for the α-ray noise and the charge discharged due to the charge redistribution. However, the N-type logic block 10
The feedback pull-up PMOS transistor 103 prevents the node 4 from extracting the electric charge at the node A to the low level. Not only the power consumption increases due to the flow of through current, but also the switching speed of the circuit is significantly reduced. Therefore,
Since this method impairs the high-speed operation, it cannot be applied to a system that requires high-speed circuit.

A static circuit for precharging an output in advance to speed up a completely complementary static CMOS circuit is disclosed in Japanese Patent Application Laid-Open No. 2-277315. However, in this circuit, a circuit for precharging the output to a high level voltage and a circuit for precharging to a low level are alternately connected in series, so that the PMOS transistor and the NMOS transistor operate alternately, and the signal is generated only by the NMOS transistor. Cannot be propagated.

[0009]

As described above, a CMOS domino circuit has been proposed as a circuit faster than a completely complementary static CMOS circuit, but has a problem that it is susceptible to noise. Conversely, if a pull-up PMOS transistor is added to increase noise, high-speed performance will be impaired. An object of the present invention is to achieve both high noise resistance and high speed. That is, an object of the present invention is to provide a circuit that is resistant to noise and that is faster than a completely complementary static CMOS circuit.

[0010]

According to the semiconductor integrated circuit device of the present invention, a plurality of complementary static logic circuits connected to the first potential section and the second potential section and connected in series, and their complements are provided. And potential setting means connected to each output section of the static logic circuit for setting the output of the output section to the second potential in synchronization with a clock signal.

According to one embodiment of the potential setting means, the first
And a precharging means for setting the output of the complementary static logic circuit to the first potential in synchronization with the clock signal.
And an inverter for setting an output unit set to the second potential to the second potential.

Further, it is desirable that a timing control means for controlling the operation timing of the complementary static logic circuit in synchronization with the clock signal is provided between the complementary static logic circuit and the second potential section.

According to another embodiment of the semiconductor integrated circuit device of the present invention, the one conductivity type MOS transistor block connected to the first potential section and the output section and supplied with an input signal; And a plurality of complementary MOS transistor blocks each having the other conductivity type MOS transistor block connected to the potential section 2 and supplied with an input signal.
The plurality of complementary MOS transistor blocks are connected in series so that the output signal of the preceding complementary MOS transistor block is input as a complementary MOS transistor block input signal of the succeeding stage. A potential setting means for setting the output signal of the MOS transistor block to a second potential, and from the complementary MOS transistor block of the preceding stage to the complementary MOS transistor block of the subsequent stage by the operation of the conductive MOS transistor block. Is propagated.

Further, according to another embodiment of the semiconductor integrated circuit device of the present invention, the semiconductor integrated circuit device has a plurality of logic blocks substantially composed of MOS transistors, and at least one of the plurality of logic blocks is a first logic block. A MOS transistor block of one conductivity type connected to the potential portion and the output portion of the transistor and supplied with the input signal, and a MOS transistor block of the conductivity type connected to the output portion and the second potential portion and supplied with the input signal. Have a plurality of complementary MOS transistor blocks. The plurality of complementary MOS transistor blocks are connected in series such that the output signal of the preceding complementary MOS transistor block is input as the complementary MOS transistor block input signal of the subsequent stage. There is provided a potential setting means for setting the output signal of the preceding complementary MOS transistor block to the second potential in synchronization with the clock signal. Then, the signal is propagated from the preceding complementary MOS transistor block to the subsequent complementary MOS transistor block by the operation of the other conductivity type MOS transistor block.

Between these logic blocks, there is provided a latch circuit which operates in synchronization with a clock signal input to the potential setting means of the preceding logic block. As the clock signal input to the preceding logic block, an inverted signal of the clock signal input to the subsequent logic block is used.

FIG. 1 shows an outline of a preferred circuit example to which the present invention is applied. The source and the drain are the first power supply terminal 1
A P-type logic block 105 composed of one or more P-type field-effect transistors connected in series or parallel between the first internal terminal 109 and the first internal terminal 109 and having a gate connected to the input terminal 108; Second power supply terminal 1
And an N-type logic block 106 composed of one or more N-type field-effect transistors connected in series or parallel between the first internal terminal 109 and the first internal terminal 109 and having a gate connected to the input terminal 108. The logic block 105 and the N-type logic block 106 constitute a completely complementary static CMOS circuit that operates complementarily. An inverter circuit 138 is connected in series between the first internal terminal 109 and the output terminal 139. Further, an N-type field effect transistor 137 whose source and drain are connected to the N-type logic block 106 and the second power supply terminal 112 and whose gate receives the clock signal CK is connected, and the first internal terminal 109 is connected to the first internal terminal 109. Precharge element 10 for precharging to the power supply potential of
7 is connected between the first power supply terminal 111 and the first internal terminal 109. The clock signal CK is input to the control terminal of the precharge element 107.

[0017]

The operation and effect of the present invention will be described with reference to FIG.
Here, the potential of the first power supply terminal 111 is set to Vdd (hereinafter referred to as high level), and the potential of the second power supply terminal 112 is set to Vss (hereinafter referred to as low level). When the potential of the clock signal CK110 becomes low level, the precharge element 107 is turned on, the potential of the first internal terminal 109 is set to high level, and the potential of the output terminal 139 is set to low level. Even if the signal at the input terminal 108 changes while the potential of the clock signal CK is at the low level, the potential at the output terminal 139 remains at the low level because the N-type field effect transistor 137 is off. When the input signal changes from a low level to a high level while the potential of the clock signal CK is at a high level and the N-type field effect transistor 137 is on, the N-type logic block 1
06 turns on, the potential of the first internal terminal 109 changes to low level, and the potential of the output terminal 139 changes to high level. Conversely, even if the input signal changes from high level to low level and the P-type logic block is turned on, the output potential does not change because the first internal terminal is originally set to high level. Therefore, the output signal changes according to the input signal only when the input signal changes from the low level to the high level and the N-type logic block is turned on. As described above, the gain coefficient β of the N-type field effect transistor is equal to the gain coefficient β of the P-type field effect transistor.
, That is, the N-type logic block 106
This circuit, which causes a signal propagation delay only when is turned on, is fast. Further, the P-type field effect transistor constituting the P-type logic block only needs to compensate for the leak current and the external noise current of the N-type logic block 106 and does not participate in the propagation of the input signal. Therefore, since a large load driving force is not required for the P-type field effect transistor, the channel width of the P-type field effect transistor constituting the P-type logic block is designed to be sufficiently smaller than the channel width of the N-type field effect transistor. can do. That is, the input capacitance of the circuit of the present invention and the junction capacitance of the P-type field effect transistor can be reduced, and high-speed operation can be performed.

Another advantage of the circuit of the present invention is high noise resistance. As described above, the circuit of the present invention includes a P-type logic block 105 including a P-type field-effect transistor;
N-type logic block 1 composed of N-type field effect transistors
Reference numeral 06 is connected in series between the first power supply terminal 111 and the second power supply terminal 112, and the P-type logic block 105 and the N-type logic block 106 constitute a completely complementary static CMOS circuit which operates complementarily. . Therefore, the circuit of the present invention does not dynamically hold charges unlike the CMOS domino circuit of the prior art. Therefore, even if a leak current, α-ray noise, charge redistribution, or noise due to a power supply line or a signal line occurs in the circuit of the present invention,
P-type logic block 105 performing static complementary operation
Since the first internal terminal 109 and the N-type logic block 106 always pull up or pull down the first internal terminal 109 to the first or second power supply potential, generation of noise can be minimized. Alternatively, even if the output potential is inverted due to noise, the output potential can be returned to a correct potential level, so that high noise resistance can be realized.

[0019]

FIG. 2 shows an example of a parallel computer system according to the present invention. A plurality of central processing units 119 each composed of a processor and a memory are connected by a connection network 120 to form one computer system. The central processing unit 119 is also connected to the hard disk 121. By combining a plurality of central processing units 119, a computer system that is many times higher in performance than a system including one central processing unit 119 can be realized. Here, there may be a case where several to several thousand central processing units 119 are combined. In order for these central processing units 119 to operate without failure for a long time, each central processing unit 119 must have high reliability. Further, in order to realize a higher performance parallel computer system, each central processing unit 119 must have high performance. That is, the central processing unit 119 shown in this parallel computer system example needs to have both high reliability and high speed. As the logic circuit forming the central processing unit 119 having such characteristics, the logic circuit of the present invention having both high noise resistance and high speed is applied.

FIG. 3 shows the central processing unit 11 shown in FIG.
9 is an example of the internal configuration, and is composed of one chip or a plurality of chips. The internal components include a floating-point register file 122, a floating-point adder 123, a floating-point multiplier 124, a floating-point divider 125, a general-purpose register 126, integer arithmetic units (ALUs) 127 and 128, an address adder 129, and data. Cache 130, data TL
B131, instruction TLB 132, instruction cache 133, and the like. The floating-point register 122 and the general-purpose register 126
Address adder 1 coupled to data cache 130
29 and the instruction control unit 135 are the instruction cache 1
33. The data cache 130 and the instruction cache 133 access data from a plurality of external terminals 136. The floating point arithmetic units 123 to 125 are connected by a first local bus or local path. The integer arithmetic units 127 to 129 are connected by a second local bus or local path. In the central processing unit 119 having such a configuration, the logic circuit of the present invention is mainly used for an internal circuit constituting each of the units 122 to 135. Further, in some cases, the present invention is applied to a buffer circuit that connects each unit or an input / output circuit with an external chip.

The logic circuit of the present invention can be applied not only to a computer system but also to other systems requiring high reliability and high speed.

FIG. 4 shows an example in which a plurality of the logic circuits of the present invention shown in FIG. 1 are connected in series. The circuit operation when a plurality of the circuits of the present invention are connected in series will be described below. In this embodiment, the precharge element is constituted by the P-type field effect transistor 107. During the precharge period, the clock signal CK goes low, the N-type field effect transistor 137 turns off, and the precharge element 107 formed of a P-type field effect transistor turns on, so that the output terminals 116, 117, and 118 all go low. . Therefore, the complementary static logic circuit 11 of the present invention
The 3,114,115 N-type logic blocks are all turned off.
During the logic determination period, the clock signal CK becomes high level, the N-type field effect transistor 137 turns on, and the precharge element 107 formed of a P-type field effect transistor turns off. At this time, for example, if the N-type logic block of the complementary static logic circuit 113 of the present invention is turned on, the output terminal 116 goes high. If the N-type logic block of the complementary static logic circuit 114 of the present invention is turned on in accordance with the input signal, the output terminal 117 goes high. In this way, the signal propagates one after another like a domino. Since the signal is propagated by the operation of the N-type logic block having a large gain coefficient β, high speed is obtained.

FIG. 5 is an example in which the logic shown in FIG. 5A is shown in a transistor level circuit diagram (b). FIG. 5 (a)
The OR circuits 161, 162, and 163 shown in FIG.
Respectively correspond to the circuits 161, 162, 163 shown in FIG.
The buffer circuit 164 shown in FIG. 5A corresponds to the circuit 164 shown in FIG.

The complementary static logic circuit of this embodiment has a problem that the logic judgment operation cannot be performed during the precharge operation.
The fact that a continuous logic decision operation is possible will be described. FIG. 6 shows a configuration example of the complementary static logic circuit of the present invention which operates in one cycle of the clock. The clock signal is CK1
And a case where two-phase clocks CK2 and CK2 are used. The logic circuit includes a preceding logic circuit group 168 constituted by the complementary static logic circuit of the present invention and a subsequent logic circuit group 169 similarly constituted by the complementary static logic circuit of the present invention. Latch circuits 165 and 167 operating in synchronization with the clock signal CK2 are connected to the start point and the end point of the one-cycle logic block, respectively. A latch circuit 166 that operates in synchronization with the clock signal CK1 is connected between the first-stage logic circuit group 168 and the second-stage logic circuit group 169. The complementary static logic circuit of the present invention in the preceding logic circuit group 168 is connected to the clock signal CK1, and the complementary static logic circuit of the present invention in the subsequent logic circuit group 169 is connected to the clock signal CK2. When the clock signal CK1 is at a high level and the clock signal CK2 is at a low level, the preceding logic circuit group 168 is in a logic determination period and signals are being propagated, and the later logic circuit group 169 is in a precharge period, and Output terminal becomes low level. On the other hand, when the clock signal CK1 is at a low level and the clock signal CK2 is at a high level, the preceding logic circuit group 168 is in a precharge period, all output terminals are at low level, and the latter logic circuit group 169 is in a logic determination period. The signal is propagating. As described above, the logic block of one cycle is divided into the former stage and the latter stage, and the precharge operation and the logical decision operation are alternately performed every half cycle, so that a continuous logic decision operation over one cycle can be executed. .

Next, a complementary static logic circuit of the present invention and a conventional complementary CMOS circuit having no precharge means are described.
An embodiment in which S circuits are mixedly configured will be described.
FIG. 7 shows a configuration diagram of a logic block operating in one clock cycle. First, the first stage comprises a logic block 170 comprising a conventional complementary CMOS circuit without precharge means, and the second stage comprises a logic block 1 comprising a conventional complementary CMOS circuit without precharge means.
It consists of 71. Latch circuits 165 and 167 connected to the clock signal CK1 are connected to the start point and the end point, respectively. The preceding logical block 170 and the following logical block 1
Between 71, a latch circuit 166 connected to the clock signal CK2 is connected. Between the preceding logic block 170 and the following logic block 171, a logic block 172 constituted by a complementary static logic circuit according to the present invention is provided.
Is connected. Logical block 172 and logical block 17
1, a latch circuit 173 is connected, and the logic block 1 is connected.
72 and the latch circuit 173 are connected to the clock signal CK2. In such a configuration, when the clock signal CK1 is at a high level and the clock signal CK2 is at a low level, the logic block 172 performs a precharge operation, and
When K1 is at a low level and the clock signal CK2 is at a high level, the logic block 172 performs a logic decision operation. In the path from the preceding logic block 170 to the logic block 172, it is necessary that the input signal of the logic block 172 be determined during the period when the clock signal CK2 is at the low level. Also, the logical blocks 172 to 17
In the path leading to 1, the input signal of the latch circuit 173 needs to be determined while the clock signal CK2 is at the high level.

FIG. 8 illustrates another embodiment in which a complementary static logic circuit according to the present invention and a conventional complementary CMOS circuit having no precharge means are mixed. FIG. 8 shows a configuration diagram of a logic block operating in one clock cycle. First, the preceding logic block comprises a logic block 172 constituted by a complementary static logic circuit according to the present invention and a logic block 170 constituted by a conventional complementary CMOS circuit having no precharge means. Logic block 1 composed of a conventional complementary CMOS circuit having no precharge means
It consists of 71. A latch circuit 165 is connected between the preceding logic block 172 and the logic block 170, and the logic block 172 and the latch circuit 165 are connected to the clock signal CK1. A latch circuit 166 is connected between the logic block 170 and the logic block 171, and a latch circuit 167 is connected to the end point of one-cycle logic. Latch circuit 166
Is connected to the clock signal CK2, and the latch circuit 167 is connected to the clock signal CK1. In such a configuration, when the clock signal CK1 is at a high level and the clock signal CK2 is at a low level, the logic block 172 performs a logic determination operation. When the clock signal CK1 is at a low level and the clock signal CK2 is at a high level, the logic block 172 performs a precharge operation. . The input signal of the logic block 172 needs to be determined during the period when the clock signal CK1 is at the low level, and the input signal of the latch circuit 166 is the clock signal C
K1 needs to be determined within the high level period.

FIG. 13 shows an embodiment of a 4OR circuit using a complementary static logic circuit according to the present invention. The configuration of the circuit will be described based on the correspondence between the components in FIG. 1 and FIG. The P-type logic block 105 in FIG. 1 corresponds to the four-stage P-type field-effect transistor 140 in FIG. The N-type logic block 106 in FIG. 1 corresponds to the four-stage parallel-connected N-type field-effect transistors 141 in FIG. The N-type field effect transistor 137 of FIG. 1 is the same as the N-type field effect transistor 137 of FIG. 13, and the precharge element 107 of FIG.
7 respectively. 108 is an input terminal and 139 is an output terminal. In the 4OR circuit, since the P-type field effect transistors are connected in series in four stages, the switching speed is greatly affected by the low gain coefficient β of the P-type field effect transistor, and the rise delay time of the internal terminal 109 is large. Therefore, in an OR-type circuit in which P-type field-effect transistors are connected in series in multiple stages, such as a 4-OR circuit, the effect of increasing the speed of the complementary static logic circuit according to the present invention is remarkably exhibited.

FIG. 14 is a layout diagram of the 40R circuit shown in FIG. The numbers indicating the components in the circuit diagram of FIG.
The corresponding parts in FIG. 14 are indicated by the same numerals. Vertical axis,
The scale on the horizontal axis is represented by the layout pitch. In FIG. 14, the vertical and horizontal unit pitch lengths are drawn to be different for the sake of clarity of the drawing, but the actual vertical and horizontal unit pitch lengths are assumed to be equal. According to this layout, the horizontal is 9 pitches and the vertical is 14 pitches, and the area of the cell is 126 square pitches. FIG. 15 shows an example in which the same logic as the 4OR circuit of the complementary static logic circuit according to the present invention shown in FIG. 13 is provided by a conventional complementary CMOS circuit having no precharge means, and FIG. 16 shows a layout example thereof. . According to this layout, the width is 7 pitches and the height is 18 pitches, and the cell area is 126 square pitches. FIG.
4 of the complementary static logic circuit according to the present invention.
The OR circuit can have the same layout area in spite of having two more transistors than a conventional complementary CMOS circuit having no precharge means. This is because, in the complementary static logic circuit according to the present invention, a higher speed can be achieved by designing the channel width of the P-type field effect transistor to be sufficiently small. This is offset by reducing the length in the direction.

FIG. 17 shows an embodiment of a 4-bit adder using a complementary static logic circuit according to the present invention.
140 is a P-type logic block, 141 is an N-type logic block, 107 is a P-type electric field transistor for precharging, 1
37 is an N-type electric field transistor for preventing a through current at the time of precharge, 110 is a precharge signal input terminal, 13
9 is an output terminal. The logical meaning of input and output signals is described in “Neil HEWeste and Kamran Eshraghian: Pri
As disclosed in “nciples of CMOS VLSI Design”.

The i-th carry Ci is expressed by the following equation.

C _i = G _i + P _i × C _{i -1} where G _i = A _i × B _i (generated signal) P _i = A _i + B _i (propagation signal).

In the case of 4 bits, the following equation is obtained.

C ₁ = G ₁ + P ₁ C ₀ C ₂ = G ₂ + P ₂ G ₁ + P ₂ P ₁ C ₀ C ₃ = G ₃ + P ₃ G ₂ + P ₃ P ₂ G ₁ + P ₃ P ₂ P ₁ C _{0 C 4 = G 4 + P 4} G 3 + P 4 P 3 G 2 + P 4 P 3 P 2 G 1 + P 4 P 3
Focusing on the P ₂ P ₁ C ₀ C ₄ can be expressed by the following equation.

C ₄ = G ₄ + P ₄ (G ₃ + P ₃ (G ₂ + P ₂ (G ₁ + P ₁ C ₀ ))) FIG. 17 shows a circuit that realizes this function. This function is a P-type logic block 140 and an N-type logic block 14.
1, an output inverter 138. Fourth Embodiment
When the bit adder is constituted by a conventional complementary CMOS circuit having no precharge means, five P-type field effect transistors are connected from the first power supply terminal 111 to the internal terminal 109.
The stages are connected in series. Therefore, the rise delay time of internal terminal 109 becomes extremely long. In the 4-bit adder using the complementary static logic circuit according to the present invention, the voltage of the internal terminal 109 is raised in advance by the precharge operation, so that the internal circuit is different from the conventional complementary CMOS circuit having no precharge means. There is no problem that the rise time of the terminal 109 is long, and high speed can be obtained. FIG.
The basic circuit configuration of the embodiment shown in FIG. 8 is the same as that of the embodiment shown in FIG. In the embodiment of FIG. 18, each of the nodes 142 to 142 of the N-type field-effect transistor forming the N-type logic block
145 and 109 are precharged by the respective P-type field effect transistors to shorten the precharge time and reduce the influence on the circuit performance due to charge redistribution.

FIG. 19 shows the embodiment shown in FIG. 18 in which the number of transistors is reduced. In the embodiment shown in FIG. 18, the P-type logic block is constituted by completely complementary logic. However, in this embodiment, the P-type field effect of the P-type logic block is obtained by using the node 145 and the logic signal of the input signal P4. The number of transistors has been reduced to 33%.

FIG. 20 shows a complementary static logic circuit 185, 186, 18 having a voltage setting element according to the present invention.
7 is an example of a logic block including conventional static logic circuits 189 and 190 and latch circuits 191 and 192 having no voltage setting element. The latch circuit 191 on the input side is connected to the clock signal CK1. Complementary static logic circuits 185, 186, 187 having an output side latch circuit 192 and a voltage setting element according to the present invention
Is connected to the clock signal CK2. The output of the latch circuit 191 on the input side is connected to a complementary static logic circuit having a voltage setting element according to the present invention. Further, the logic block of this embodiment does not include an inversion logic circuit. In such a configuration, while the clock signal CK2 is at the low level, the output terminal 180 of the complementary static logic circuit 185 having the voltage setting element according to the present invention is set to the low level voltage. Next, since the input terminal 180 of the conventional complementary static logic circuit 189 having no voltage setting element is a low level voltage, the output terminal 181 is also set to the low level voltage. Similarly, all output terminals 180, 181, 182, 183, 184 are set to the low level voltage. Thus, the clock signal C
A period in which all output terminals are set to a low level voltage while K2 is at a low level is a precharge period. Further, during the precharge period, the clock signal CK1 is at the high level, the latch circuit 191 allows the input data to pass to the output, and determines the input data signal of the complementary static logic circuit 185 having the voltage setting element according to the present invention. . Assuming that the input data signal of the complementary static logic circuit 185 is a signal of a high level voltage, when the clock signal CK2 rises to a high level, the NMOS transistor of the complementary static logic circuit 185 is turned on and the output terminal 180 is at the high level voltage. Stand up. If the other terminal of the complementary static logic circuit 189 is at a high level,
Turn on, and the output terminal 181 rises to the high level voltage. In this way, data propagates one after another. Conversely, if the input data signals of the complementary static logic circuit 185 are all low level voltage signals,
Are turned on, and the output terminal 180 remains unchanged at the low level. Further, the input of the complementary static logic circuit 189 remains at the low level, and the output terminal 181 does not change at the low level voltage. As described above, in all circuits, the signal propagates only when the NMOS transistor is turned on, and when the PMOS transistor is turned on, the output does not change with the precharged voltage. Therefore, the decision of the propagation delay time of the signal of the logic block shown in this embodiment is based on NM
This is a case where the OS transistor is turned on. Of course, the PMOS of the output inverter of each circuit is turned on, but only the PMOS of one stage is always turned on. Since signal propagation is always performed only by the NMOS transistor having a large gain coefficient, high speed can be obtained. In this way, even if the complementary static logic circuit having the voltage setting element according to the present invention and the conventional complementary static logic circuit having no voltage setting element are mixed, the output is set to the low-level voltage in advance,
It can be seen that a configuration is possible in which the signal propagates only when the NMOS transistor is turned on.

FIG. 21 shows a complementary static logic circuit 185, 186, 18 having a voltage setting element according to the present invention.
7 and conventional complementary static logic circuits 189, 193, 194 having no voltage setting element and latch circuit 191,
192 is an example of a logical block composed of 192. The latch circuit 191 on the input side is connected to the clock signal CK1.
Complementary static logic circuits 185, 18 having an output side latch circuit 192 and a voltage setting element according to the present invention
6,187 are connected to the clock signal CK2. The output of the latch circuit 191 on the input side is connected to a complementary static logic circuit having a voltage setting element according to the present invention. The logic blocks include inverted logic circuits 193, 19
4 is included. An output terminal of the inversion logic circuit 193 is connected to another complementary static logic circuit block 217. Complementary static logic circuit block 217 is constituted by a conventional complementary static logic circuit having no voltage setting element.

In such a configuration, the clock signal CK2
Is low level, the output terminal of the complementary static logic circuit 185 having the voltage setting element according to the present invention.
180 is set to the low level voltage. Next, a conventional complementary static logic circuit 189 having no voltage setting element is used.
Since the input terminal 180 is a low level voltage, the output terminal 181 is also set to the low level voltage. Similarly, the output terminals 182, 183, and 184 are set to the low level voltage, while the output terminal 195 is set to the high level voltage.

As described above, in the logic circuit block having the complementary static logic circuit having the voltage setting element according to the present invention, when there is a terminal set to the high level voltage during the precharge period, the terminal is always inverted. It is converted to a low level voltage by a logic circuit. According to the present embodiment, the signal at the terminal 195 is inverted by the inverter circuit 194 and is input to the complementary static logic circuit 187 having the voltage setting element according to the present invention. With this configuration, the input terminals of all the logic circuits except the inversion logic circuit are set to the low level voltage.

As described above, the period in which all the input terminals except the inversion logic circuit are set to the low level voltage while the clock signal CK2 is at the low level is the precharge period. Further, during the precharge period, the clock signal CK1 is at the high level, and the latch circuit 191 allows the input data to pass through the output, and determines the input data signal of the complementary static logic circuit 185 having the voltage setting element according to the present invention. . Assuming that the input data signal of the complementary static logic circuit 185 is a signal of a high level voltage, when the clock signal CK2 rises to a high level, the NMOS transistor of the complementary static logic circuit 185 is turned on and the output terminal 180 is at a high level voltage. Stand up. If the other terminal of the complementary static logic circuit 189 is at a high level, the NMOS transistor of the complementary static logic circuit 189 turns on and the output terminal 18
1 rises to a high level voltage. In this way, data propagates one after another.

On the contrary, the output terminal 195 of the inversion logic circuit falls from the high level voltage to the low level voltage, but the input terminal of the complementary static logic circuit 187 having the voltage setting element according to the present invention changes from the low level voltage to the high level voltage. The rising signal propagates without interruption. Conversely, if the input data signals of the complementary static logic circuit 185 are all low level voltage signals, the PMOS transistor of the complementary static logic circuit 185 is turned on and the output terminal 180 remains at the low level. Further, the input of the complementary static logic circuit 189 remains at the low level, and the output terminal 181 does not change at the low level voltage. The output terminal 195 of the inverting logic circuit 193 does not change with the high level voltage, but the input terminal of the complementary static logic circuit 187 having the voltage setting element according to the present invention does not change with the low level. Thus, for all circuits except the inverted logic circuit, N
The signal propagates only when the MOS transistor is turned on, and when the PMOS transistor is turned on, the output does not change with the precharged voltage.

Accordingly, the propagation delay time of the signal of the logic block shown in the present embodiment is determined when the NMOS transistor except the inversion logic circuit is turned on. Since signal propagation is always performed only by the NMOS transistor having a large gain coefficient, high speed can be obtained. As described above, even when the complementary static logic circuit having the voltage setting element according to the present invention, the conventional complementary static logic circuit having no voltage setting element, and the inverted logic circuit are mixed, the output is previously set to the low level voltage. , The signal propagates through the NMO
It can be seen that a configuration in which only the S transistor is turned on is possible.

[0043]

As described above, according to the present invention, a semiconductor integrated circuit device capable of transmitting a signal at high speed can be realized. Further, a semiconductor integrated circuit device having high noise resistance can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a circuit to which the present invention is applied and its operation.

FIG. 2 is a diagram showing an embodiment of a parallel computer system to which the present invention is applied.

FIG. 3 is a diagram showing one embodiment of a central processing unit of the system shown in FIG. 2;

FIG. 4 is a diagram showing an example in which a plurality of circuits to which the present invention is applied are connected in series.

FIG. 5 is a diagram showing another example using a plurality of circuits to which the present invention is applied.

FIG. 6 shows a static domino type CMO to which the present invention is applied.
1 shows an embodiment of an S logic circuit.

FIG. 7 is a diagram showing a configuration example of a logic block operating in one clock cycle to which the present invention is applied.

FIG. 8 is a diagram showing another configuration example of a logic block operating in one clock cycle to which the present invention is applied.

FIG. 9 is a diagram showing a conventional CMOS domino circuit.

FIG. 10 is a diagram showing a problem of the circuit shown in FIG. 9;

FIG. 11 is a diagram showing another problem of the conventional CMOS domino circuit.

FIG. 12 is a diagram showing another conventional circuit example.

FIG. 13 is a diagram illustrating an example of a 4OR circuit to which the present invention is applied.

FIG. 14 is a diagram illustrating a layout example of the circuit illustrated in FIG. 13;

FIG. 15 is a diagram illustrating an example of a conventional 4OR circuit.

16 is a diagram illustrating a layout example of the circuit illustrated in FIG. 15;

FIG. 17 is a diagram showing an embodiment of a 4-bit adder to which the present invention is applied.

FIG. 18 is a diagram illustrating another example of a 4-bit adder to which the present invention is applied.

FIG. 19 is a diagram showing another example of a 4-bit adder to which the present invention is applied.

FIG. 20 is a diagram showing an example in which a complementary static logic circuit to which the present invention is applied and a conventional complementary static logic circuit are mixed.

FIG. 21 is a diagram showing another example in which a complementary static logic circuit to which the present invention is applied and a conventional complementary static logic circuit are mixed.

FIG. 22 is a diagram showing another example in which a complementary static logic circuit to which the present invention is applied and a conventional complementary static logic circuit are mixed.

FIG. 23 is a diagram illustrating an example of a buffer circuit to which the present invention is applied.

FIG. 24 is a diagram showing an example in which a plurality of complementary static logic circuits to which the present invention is applied are connected.

FIG. 25 is a diagram showing another example in which a plurality of complementary static logic circuits to which the present invention is applied are connected.

[Explanation of symbols]

100 to 102: NMOS transistor, 103: PM
OS transistor, 104... N-type logic block, 105
... P-type logic block, 106 ... N-type logic block, 10
7: Precharge element, 108: Input terminal, 109: Internal terminal, 110: Precharge signal input terminal, 111: First power supply terminal, 112: Second power supply terminal, 113, 11
4,115 ... Static domino type CMOS logic circuit,
116 to 118: input / output terminals, 119: central processing unit, 120: connection network, 121: hard disk, 122: floating point register file, 123: adder, 124: floating point multiplier, 125: floating point divider , 126 ... general-purpose register, 127, 128 ... integer arithmetic unit, 129 ... address adder, 130, 133 ... cache, 131, 132 ... TLB, 134 ... memory control unit, 135 ... instruction control unit, 136 ... external terminal, 137 ... N-type field effect transistor
47 ... Inverter, 139 ... Output terminal, 140 ... P-type logic block, 141 ... N-type logic block, 142-14
5 internal node, 161, 162, 163, 164 static domino type CMOS logic circuit, 165, 16
6,167,173 ... Latch circuit, 168,169,1
72: a logic block composed of a static domino type CMOS logic circuit; 170, 171: a logic block composed of a completely complementary CMOS circuit.

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Hiromichi Yamada 7-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 19/096

Claims (12)

(57) [Claims] A plurality of complementary static logic circuits connected to a first potential section and a second potential section and connected in series; and a clock signal connected to respective output sections of the complementary static logic circuits. And a potential setting unit that sets the output of the output unit to the second potential in synchronization with the operation of the semiconductor integrated circuit device. 2. The method according to claim 1, wherein the complementary static type is used.
Connected to the logic circuit and the second potential unit,
Of the complementary static logic circuit in synchronization with the clock signal.
Half having a timing control unit for controlling operation timing
Conductor integrated circuit device. 3. The electric potential setting section according to claim 2, wherein
Connected to the first potential section and synchronized with the clock signal.
The output of the complementary static logic circuit
A precharge unit for setting the potential to 1;
The output section, which is set to a first potential by the
Semiconductor integrated circuit having an inverter set to 2 potentials
Road equipment. 4. An input circuit connected to a first potential section and an output section,
While the signal is supplied, the conductive type MOS transistor block
And the input connected to the output section and the second potential section.
The other conductivity type MOS transistor block to which the signal is supplied
Multiple complementary MOS transistor blocks
Having a semiconductor integrated circuit device, the plurality of complementary MOS transistors blocks, series
Connected to the complementary MOS transistor block in the preceding stage.
The output signal is input to the complementary MOS transistor block at the subsequent stage.
Input between the plurality of complementary MOS transistor blocks.
Output signal of the complementary MOS transistor block
A potential setting section for setting the potential to the second potential;
The phase of the previous stage is determined by the operation of the
From the complementary MOS transistor block to the subsequent complementary MO
Semiconductor integration where signal is propagated to S transistor block
Circuit device. 5. The electric potential setting section according to claim 4, wherein
Connected to the first potential section, and synchronized with the clock signal,
The output of the complementary MOS transistor block is connected to the
A precharge unit for setting the potential to 1;
The output section, which is set to a first potential by the
Semiconductor integrated circuit having an inverter set to 2 potentials
Road equipment. 6. The NMOS transistor according to claim 4, wherein
Connected between the star block and the second potential unit,
The NMOS transistor block is synchronized with a clock signal.
It has a timing control unit that controls the operation timing of the
Semiconductor integrated circuit device. 7. At least one of the plurality of logical blocks includes:
An input signal is connected to the first potential section and the output section.
One conductivity type MOS transistor block,
The input signal is connected to the input portion and the second potential portion.
Other conductivity type MOS transistor block
A plurality of complementary MOS transistor blocks , wherein the plurality of complementary MOS transistor blocks
Output signal of the complementary MOS transistor block
Input as a complementary MOS transistor block input signal
And a plurality of complementary MOS transistor blocks are connected in series .
In synchronization with the clock signal, the complementary MOS transistor
To set the output signal of the star block to the second potential.
A position setting unit, which operates according to the operation of the other conductivity type MOS transistor block.
From the preceding complementary MOS transistor block
Signal is propagated to complementary MOS transistor block
Semiconductor integrated circuit device. 8. The logic circuit according to claim 7, wherein
Is the clock input to the potential setting section of the previous logic block.
Semiconductor having a latch circuit operating in synchronization with a clock signal
Integrated circuit device. 9. The logic block according to claim 8, wherein
The input clock signal is input to the subsequent logic block.
Semiconductor integrated circuit device which is an inverted signal of
Place. 10. The electronic device according to claim 7, 8, or 9,
A potential setting unit connected to the first potential unit;
The complementary MOS transistor block is synchronized with a signal.
Precharge section for setting an output section of the battery to the first potential
Is set to the first potential by the precharge unit.
An inverter for setting the output unit to the second potential.
Semiconductor integrated circuit device having the same. 11. The NMOS transistor according to claim 10,
Connected between the transistor block and the second potential portion;
The NMOS transistor is synchronized with the clock signal.
Timing control unit that controls the operation timing of blocks
A semiconductor integrated circuit device having: 12. A method according to claim 11, wherein the plurality of field effect transistors are the same half.
In a semiconductor integrated circuit device formed on a conductive substrate, a source and a drain are connected between a first power supply terminal and an internal terminal.
Connected in series or in parallel, with the gate connected to the input terminal.
Consisting of one or more P-type field effect transistors connected
The first P-type logic block and the source and drain
2 in series or in parallel between the power supply terminal 2 and the internal terminal.
Connected to one or more N gates connected to the input terminals.
A first N-type logic block comprising a field-effect transistor
And a source and a drain having a gate connected to the internal terminal.
Is connected between the first power supply terminal and the output terminal.
A P-type field effect transistor and a gate connected to the internal terminal
Connected source and drain to second power supply terminal and output
A first N-type field effect transistor connected between the first terminal and the terminal
An inverter circuit, which is connected between the first power supply terminal and the internal terminal;
The internal terminal is connected to the first power supply by a voltage setting control signal.
And a voltage setting element for setting the voltage level of the semiconductor device.
Integrated circuit device.