JPH09116422A - Semiconductor logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten response time in a judgment period and to shorten floating time by adding a floating protection circuit to a latch-type dynamic logic circuit. SOLUTION: The floating prevention circuit 1 is controlled to operate after prescribed time, subsequently, the dynamic logic circuit 1 is changed from a precharge period to the judgment period. The floating prevention circuit F2 is controlled in such a way that output Z1 operates at the time of high potential and it is prevented from operating at the time of low potential. When an input signal A is high potential, charge accumulated in output Z2 is discharged at high speed and the signal becomes low potential. Thus, response time in the judgment period of the logic circuit 1 can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic logic circuit, and more particularly to a semiconductor logic circuit which has a shortened response time in a judgment period and a floating time.

[0002]

2. Description of the Related Art A logic circuit having a circuit for discharging a charge precharged in a capacitor is called a dynamic logic circuit. 2A and 2B are configuration diagrams of a conventional dynamic logic circuit. The operation of these dynamic logic circuits is described, for example, in "Principles of CMOS VLSI Design" (translated by Tomizawa and Matsuyama, Maruzen), pages 138 to 144. FIG. 2A shows a basic type dynamic CMOS (complementary field effect transistor) gate, which is connected to the output node Z1 from the first power source (potential) VDD through the p-type MOS transistor MP3.
Will be precharged. Further, it is configured to include an n-type logic circuit that is conditionally discharged from the output node Z1 via the n-type transistor MN3 connected to the second power source VSS. (b) is a latch type, basic type output node
A circuit composed of a CMOS inverter and a p-type MOS transistor MP2 is connected to Z1. The advantage of these dynamic logic circuits is that since only one transistor is used for each signal A (one or more) input to the n-type logic circuit, the input capacitive load is reduced. is there. On the other hand, two normal CMOS gates are connected per input signal, that is, two gates of a p-type MOS transistor and an n-type MOS transistor.

[0003]

However, in the basic form of FIG. 2 (a), there is a case where the output node Z1 becomes floating without being connected to the power supply potential, while in the latch form of FIG. 2 (b), Floating is prevented because it is connected to the power supply potential through a transistor, but it is known that the stray capacitance due to the transistor is added and the operating speed due to this is slowed down. This will be described in more detail with reference to the operation explanatory diagram of the conventional circuit shown in FIG. When the control signal φ is low potential, it is a precharge period, and the output Z1 is high potential because it is precharged by the p-type MOS transistor MP3 regardless of the potential of the input A. When the control signal φ1 changes from the low potential to the high potential, the P-type MOS transistor MP3 becomes non-conductive, and the determination period (evaluation period, response period) starts. At this time, in the basic form of FIG. 2A, when the input A is at a high potential (case 1), the n-type logic circuit and the n-type MOS transistor MN3 are conductive, so the charge accumulated at the output Z1 is high-speed. There is no problem with delay time or floating. However, when the input A has a low potential (case 2), the n-type logic circuit becomes non-conductive, the electric charge accumulated at the output Z1 is not discharged, and the high potential remains in the floating state. It is known that noise resistance is weak during this floating period. Therefore, it is desirable to reduce the period of this state. On the other hand, in the latch type of FIG. 2B, when the input A has a low potential (case 2),
(Case 2) As shown by the broken line, output Z1
Is still at a high potential, but the p-type MOS transistor MP2 is in a conductive state, so that it does not enter a floating state. However, if input A is at high potential (case 1),
As shown by the (case 1) broken line in (a), as in the basic type, the output Z1 is discharged, but the p-type MOS transistor MP2 is in the conductive state, so the speed is slower than in the basic type.
In order to increase the speed with this circuit type, it is necessary to make the p-type MOS transistor MP2 small (weak) and increase the on-resistance, but the smaller the p-type MOS transistor MP2 is, the more noise resistant it becomes. It becomes weak. An object of the present invention is to provide a semiconductor logic circuit which solves such a conventional problem and can shorten the response time in the determination period and the floating time.

[0004]

To achieve the above object, the semiconductor logic circuit of the present invention receives one or a plurality of input signals A and a control signal .phi.1 for determining a precharge period or a determination period. Dynamic logic circuit 1
And the control signal φ1 of the dynamic logic circuit 1 is input, the drain side and the source side of the first MOS transistor are output, and the drain side or the source side is connected to the output Z1 of the dynamic logic circuit 1. First
Of the floating prevention circuit F1 and the output Z1 of the dynamic logic circuit 1 are input, the drain side of the second MOS transistor is output, and the output is the first MO
The second floating prevention circuit F2 is connected to the source side or the drain side of the S-transistor. Where the dynamic logic circuit
The first and second floating prevention circuits F2 are the conventional latch type dynamic logic circuit shown in FIG. 2B, and the present invention adds a floating prevention circuit F1 to this circuit.

[0005]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, after the dynamic logic circuit 1 is changed from the precharge period to the determination period, a fixed time is delayed (at least the time until the charge accumulated in the output Z1 is discharged at high speed). The first floating prevention circuit F1 is controlled to operate. Further, the second floating prevention circuit F2 is controlled so that the output Z1 operates when the potential is high and does not operate when the potential is low. As a result,
When the input signal A has a high potential, the electric charge accumulated in the output Z1 is discharged at a high speed and becomes a low potential. Further, when the input signal A has a low potential, the output Z1 remains at a high potential, but at this time,
Although the first floating prevention circuit F1 does not operate for a certain period of time, it is in a floating state, but thereafter, the first floating prevention circuit F1 and the second floating prevention circuit F2 both operate, so that the floating state disappears. As a result, the response time in the determination period of the dynamic logic circuit can be shortened and the floating time can be shortened, so that the speedup and the reliability can be improved.

[0006]

1 is a circuit configuration diagram of a semiconductor logic circuit showing a first embodiment of the present invention. Dynamic logic circuit 1
Is the basic dynamic CMOS gate shown in FIG.
Is one. In addition, the first floating prevention circuit F1
3 stages of inverter (if it is an odd stage) delay circuit DL,
First p-type MOS which receives at its gate the output φ2 of the delay circuit DL
The control signal φ1 is connected to the input (first terminal) of the delay circuit DL, which is composed of a transistor MP1 and is a p-type MOS transistor M.
The output Z1 of the dynamic logic circuit 1 is connected to the drain (second terminal) of P1. Further, the second floating prevention circuit F2 includes an inverter N1 and an output of the inverter N1.
It consists of a second p-type MOS transistor MP2 that receives Z2 at its gate, the input (fifth terminal) of the inverter N1 is connected to the output Z1 of the dynamic logic circuit 1, and the p-type MOS transistor MP2
The source is connected to the first power supply VDD, and the drain (fourth terminal) is connected to the source (third terminal) of the p-type MOS transistor MP1.

FIG. 3B is an explanatory diagram of the operation of the circuit of the present invention. When the control signal φ1 is at low potential (precharge period),
Regardless of the potential of the input A, the output Z1 is a high potential because it is precharged via the p-type MOS transistor MP3 of the dynamic logic circuit 1. When the control signal φ1 changes from low potential to high potential (judgment, evaluation period), the output φ2 of the delay circuit DL
Changes from high potential to low potential with delay time td1 delayed and p-type MOS
The transistor MP1 changes from non-conducting to conducting. Next, of the determination period, the period of delay time td1 and the period of remaining time td2 will be described. First, in the period of delay time td1,
When input A is at high potential (case 1), n-type logic circuit and n
-Type MOS transistor MN3 is conductive and p-type MO
Since the S transistor MP1 is non-conductive, the electric charge accumulated in the output Z1 is discharged at high speed through the second power supply VSS. Also, when the input A is low potential (case 2),
Since the n-type logic circuit is non-conducting and the p-type MOS transistor MP1 is non-conducting, the charge accumulated in the output Z1 is not charged / discharged and remains at a high potential, and is in a floating state.

Next, during the remaining time td2, the control signal φ1 is at a high potential (judgment and evaluation period) and the output φ2 of the delay circuit DL is at a low potential, so that the p-type MOS transistor MP1 is conductive. However, when the input signal A is high potential (case 1), the output Z1 is low potential and the output Z2 is high potential, so p-type MOS
The transistor MP2 is non-conducting and the output Z1 is kept at a low potential. Further, during the period of td2, as described above, when the p-type transistor MP1 is conductive and the input signal A is at a low potential (case 2), the output Z1 is at a high potential and the output Z2 is at a low potential. Since the transistor MP2 is conducting,
Since the output Z1 is connected to the first power supply potential VDD, it is connected to a high potential, and the floating state is lost. After all, as is apparent from FIG. 3A, in this embodiment, as shown in FIG. 3A, the non-conduction state of the p-type MOS transistor MP2 is set to the time td1 only, and the remaining time td2 is made conductive. I was in a state. This makes the response time faster,
Since the floating time is only td1, according to the present embodiment, the response time in the determination period of the dynamic logic circuit and the floating time can be shortened.

FIGS. 4A and 4B are circuit configuration diagrams of another dynamic logic circuit applied to the first embodiment.
These are conventionally known circuits and are shown in FIG.
Is for preventing penetration of the dynamic logic circuit 1 shown in FIG.
In this circuit, the MOS transistor MN3 is removed. Therefore, when this circuit is used, a through current flows unless the input signal A is controlled to be kept at a low potential during the precharge period. In addition, in FIG. 4B, the input signal A is input to C.
MOS inverter (or NAND circuit, or n-type logic circuit) N
2 and a CMOS inverter N3 that receives the control signal φ1 as input. The source of the n-type MOS transistor MN5 of the CMOS inverter N3 is connected to the output of the inverter N2.
The output of N3 is the output Z1 of the dynamic logic circuit 1. This circuit performs the same operation as the dynamic logic circuit 1 shown in FIG. That is, the p-type MOS transistor MP3 and the n-type MOS transistor M of the dynamic logic circuit 1 of FIG.
The CMOS consisting of N3 is the p-type MOS transistor M of FIG.
The n-type logic circuit of FIG. 1 corresponds to the CMOS composed of P5 and the n-type MOS transistor MN5, and the p-type MOS transistor of FIG.
Corresponds to CMOS consisting of MP4 and n-type MOS transistor MN4.

FIG. 5 is a diagram showing another first floating prevention circuit F1 applied to the first embodiment. This circuit is a delay circuit with two stages of inverters (if it is an even number).
It is composed of DL and a first n-type MOS transistor MN1 whose gate receives the output φ2 of the delay circuit DL. In this way, the first floating prevention circuit F1 shown in FIG.
When MOS transistors are used, the inverter of the delay circuit DL needs to have an even number of stages. Also, it is necessary to invert the polarity of only the signal φ2 shown in the operation explanatory diagram of FIG. As described above, the dynamic logic circuit 1 and the first floating prevention circuit F1 shown in FIGS.
By configuring the circuit configuration in which the second floating prevention circuit F2 and the second floating prevention circuit F2 are combined, the same effect as that of the first embodiment can be obtained.

Next, FIG. 6 is a circuit configuration diagram of a semiconductor logic circuit showing a second embodiment of the present invention. In this embodiment, the dynamic logic circuit 1 is a dynamic logic circuit including a p-type logic circuit. In this case, the dynamic logic circuit 1 and the first floating prevention circuit F1,
The connection relationship between the second floating prevention circuit F2 and the second floating prevention circuit F2 is almost the same as that of the first embodiment shown in FIG. 1, except for the following points. That is, p-type MOS transistors MP1 and MP
Use n-type MOS transistors MN1 and MN2 instead of 2.
The source of the n-type MOS transistor MN2 is connected to the second power supply VSS. In addition, n-type MOS transistor MN1
Since the polarity of the output φ2 of the delay circuit DL that drives the gate of is required to be opposite to the polarity of the control signal φ1, the number of inverter stages of the delay circuit DL needs to be an odd number.
It is necessary to consider the circuit operation of the present embodiment by reversing the polarities of the signals in the operation explanatory diagram shown in FIG. Further, it is necessary to consider the relationship between the charge and discharge of the precharge and the determination period in the opposite manner to the case of the first embodiment. For example, the control signal φ1 in FIG. 6 is high level during the precharge period and low level during the evaluation period, and the signal φ2 of the first floating prevention circuit F1 is low level during the precharge period and high level during the evaluation period. .

FIGS. 7A and 7B are diagrams showing another dynamic logic circuit applied to the second embodiment. These are conventionally known circuits, and FIG. 7A shows a p-type MOS for preventing penetration of the dynamic logic circuit 1 shown in FIG.
This is a circuit in which the transistor MP3 is deleted. Therefore, when using this circuit, a through current flows unless the input signal A is controlled to be kept at a high potential during the precharge period. Further, FIG. 7B shows a CMO in which the input signal A is input.
S inverter (or NOR circuit, or p-type logic circuit) N4
And a source of a p-type MOS transistor MP7 of the CMOS inverter N5 is connected to the output of the inverter N4, and the output of the CMOS inverter N5 is connected to the output of the dynamic logic circuit 1. The output is Z1. This circuit performs the same operation as the dynamic logic circuit 1 shown in FIG.

FIG. 8 is a diagram showing another first floating prevention circuit F1 applied to the second embodiment. This circuit is a delay circuit with two stages of inverters (if it is an even number).
It is composed of DL and a first p-type transistor MP1 whose gate receives the output φ2 of the delay circuit DL. When a p-type MOS transistor is used instead of an n-type MOS transistor in the first floating prevention circuit F1 shown in FIG. 6, as shown in FIG. 8, the number of inverters in the delay circuit DL is set to an even number and its output φ2. To the p-type MOS transistor MP1. As described above, the dynamic logic circuit 1 shown in FIGS. 6, 7, and 8, the first floating prevention circuit F1, and the second
By configuring the floating prevention circuits F2 of FIG. 3 in combination, the same effect as that of the first embodiment can be obtained.

FIG. 9 is a circuit configuration diagram of a semiconductor logic circuit showing a third embodiment of the present invention. In this embodiment, the input signal
CMOS inverter (or NAND circuit) N6 with A as input,
A dynamic logic circuit 1 comprising a CMOS inverter N7 having the control signal φ1 as an input, the source of an n-type MOS transistor MN9 of the CMOS inverter N7 being connected to the output of the inverter N6, and the control signal φ1 being input P-type MOS transistor whose gate receives the output φ2 of the delay circuit DL
It is composed of a third floating prevention circuit F3 composed of MP10, the source of the p-type transistor MP10 is connected to the output Z1 of the dynamic logic circuit 1, and the drain is connected to the output of the inverter N6. In this way, FIG.
When the dynamic logic circuit 1 shown in FIG. 1 is used, the same effect as that of the semiconductor logic circuit of FIG. 1 can be obtained only by adding the third floating prevention circuit 1 having a simple structure as shown in FIG.

First, the operation of the dynamic logic circuit 1 will be described. This circuit is a conventionally known circuit, and is basically the same as the operation shown by the solid line in the operation explanatory view of the conventional circuit shown in FIG. That is, the control signal φ1
Is high potential (judgment, evaluation period) and input signal A is low potential
(Case 2), output Z1 is p-type MOS transistor MP8, and n
Although it is charged to the VDD potential through the MOS transistor MN9, the noise resistance is weak because the n-type MOS transistor MN9 is used as a source follower. That is, n-type MO
If the threshold voltage of the S transistor MN9 is Vth, the output Z
1 easily drops to the (VDD-Vth) potential, the output Z1 has a weak ability to charge, and it takes a long time to reach the VDD potential again. In order to solve this problem, the third floating prevention circuit F3 is provided. As a result, as shown in FIG. 3B, the response period is shortened and the floating period is td1.
It has been shortened to only. In this case, when the control signal φ1 changes from the low potential to the high potential (from the precharge period to the evaluation period), the p-type MOS transistor MP10 becomes conductive with a delay of the delay time of the delay circuit DL. Since the p-type MOS transistor MP10 is used with the source grounded, the output Z1 is easily charged to the VDD potential, so that the problem of weak noise immunity is eliminated.

FIG. 10 is a circuit configuration diagram of a semiconductor logic circuit showing a fourth embodiment of the present invention. In this embodiment, the dynamic logic circuit 1 in the circuit configuration of FIG.
Instead of the circuit shown in (b), the p-type MOS transistor MP10 of the third floating prevention circuit F3 is composed of an n-type MOS transistor MN13 to form a fourth floating prevention circuit. CMOS inverter with input signal A as input
(Or NOR circuit) N8 and CM that receives the control signal φ1
It consists of an OS inverter N9, and the p-type MO of the CMOS inverter N9.
The source of the S transistor MP12 is composed of a dynamic logic circuit 1 connected to the output of the inverter N8, and an n-type MOS transistor MN13 which receives at its gate the output φ2 of the delay circuit DL which receives the control signal φ1 as the fourth. Of the n-type MOS transistor MN13 is connected to the output Z1 of the dynamic logic circuit 1 and the drain thereof is connected to the output of the inverter N8. It is necessary to consider the circuit operation of the present embodiment by reversing the polarities of the signals in the operation explanatory diagram shown in FIG. Further, it is necessary to consider the relationship of charge and discharge in the precharge and determination (evaluation) periods in the opposite manner to that in the first embodiment. For example, the control signal φ1 in FIG. 10 is high level during the precharge period and is low level during the determination (evaluation) period, and the signal φ2 of the first floating prevention circuit F1 is low level during the precharge period and is determined (evaluation). High level during the period.

This dynamic logic circuit 1 is also a conventionally known circuit, and is basically the same as the operation of inverting the polarity of the signal shown by the solid line in the operation explanatory diagram of the conventional circuit shown in FIG. 3 (a). is there. Further, there is a problem similar to that of the third embodiment. That is, the control signal φ1 has a low potential (judgment, evaluation period)
When input signal A is at high potential (case 2), output Z1 is n-type M
Although it is discharged to the VSS potential through the OS transistor MN11 and the p-type MOS transistor MP12, noise resistance is weak because the p-type MOS transistor MP12 is used as a source follower. That is, p-type MOS transistor MP12
If the threshold voltage of is Vth, the output Z1 easily rises to the (VSS + Vth) potential, and it takes a long time to fall to the VSS potential again. A fourth floating prevention circuit F4 is provided to solve this problem. This shortens the response period and reduces the floating period, as shown in FIG. 3 (b).
Shortened to td1 only. In this case, when the control signal φ1 changes from the high potential to the low potential (from the precharge period to the evaluation period), the n-type MOS transistor MN13 becomes conductive with a delay of the delay time of the delay circuit DL. Since the n-type MOS transistor MN13 is used with the source grounded, the output Z1 is easily discharged to the VSS potential, and the problem of weak noise immunity is eliminated.

FIG. 11 is a circuit configuration diagram of a semiconductor logic circuit showing a fifth embodiment of the present invention, and FIG. 12 is a circuit configuration diagram of a semiconductor logic circuit showing a sixth embodiment of the present invention. . Hereinafter, a case where a plurality of circuits of the present invention are driven by the control signal φ1 will be described. First, the case of driving a plurality of the first embodiment of FIG. 1 will be described with reference to FIG. In this embodiment,
For simplification, the case where four drivers DR1 to DR4 are driven is shown. Here, the drivers DR1 to DR4 include the dynamic logic circuit 1 shown in FIG. 1, a circuit obtained by removing the delay circuit DL from the first floating prevention circuit F1 and the second floating prevention circuit F2. Control signal φ1 is driver DR1 ~
Input signals A to D are commonly input to DR4 and drivers DR1 to DR
One is entered in each of 4. Further, there is one delay circuit DL that receives the control signal φ1 as its input, and its output signal φ2
Is commonly input to the gates of the p-type MOS transistors MP1 of the drivers DR1 to DR4. In this way, the same control signal φ1
In the case of driving a plurality of circuits according to the present invention, the delay circuit DL can be made common to be one, so that the same effect as that of the first embodiment can be obtained without increasing the power consumption and the layout area so much. it can. Next, FIG. 12 shows a case where a plurality of the third embodiments of FIG. 9 are driven. Here, the drivers DR1 to DR4 are the dynamic logic circuit 1 shown in FIG.
And a circuit obtained by removing the delay circuit DL from the third floating prevention circuit F3. As shown in FIG. 12, in this embodiment as well, when a plurality of the circuits of the present invention are driven by the same control signal φ1, the delay circuit DL can be made common to one, so that it is similar to the first embodiment. The effect of can be obtained. It is obvious that the same applies when a plurality of the second and fourth embodiments are driven.

[0019]

As described above, according to the present invention, it is possible to shorten the response time and the floating time during the determination (evaluation) period of the dynamic logic circuit, so that the operation of the logic circuit can be reduced. The speed and reliability can be improved.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a semiconductor logic circuit showing a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a conventional dynamic logic circuit.

FIG. 3 is an explanatory diagram of operations of the present invention and a conventional logic circuit.

FIG. 4 is a diagram showing another dynamic logic circuit applied to the first embodiment.

FIG. 5 is a diagram showing another floating prevention circuit applied to the first embodiment.

FIG. 6 is a circuit configuration diagram of a semiconductor logic circuit showing a second embodiment of the present invention.

FIG. 7 is a diagram showing another dynamic logic circuit applied to the second embodiment.

FIG. 8 is a diagram showing another floating prevention circuit applied to the second embodiment.

FIG. 9 is a circuit configuration diagram of a semiconductor logic circuit showing a third embodiment of the present invention.

FIG. 10 is a circuit configuration diagram of a semiconductor logic circuit showing a fourth embodiment of the present invention.

FIG. 11 is a circuit configuration diagram of a semiconductor logic circuit showing a fifth embodiment of the present invention.

FIG. 12 is a circuit configuration diagram of a semiconductor logic circuit showing a sixth embodiment of the present invention.

[Explanation of symbols]

φ1 to φ ... Control signal, A ... Input signal, 1 ... Dynamic logic circuit, DL ... Delay circuit, F1 to F2 ... First and second floating prevention circuits, MN3 ... n-type MOS transistor, MP1
~ MP3 ... p-type MOS transistor, N1 to N9 ... Inverter, Z1
… Output, MP4 to MP12… p-type MOS transistor, MN4 to MN9, M
N11 to MN13 ... n-type MOS transistor, VDD ... Power supply potential (high level), VSS ... Power supply potential (low level), F3, F4 ... Third and fourth floating prevention circuits, DR ... Driver circuit, Z11-Z14, Z21 to Z24 ... Output, B, C, D ... Input signal.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takeshi Kusunoki 3681 Hayano, Mobara-shi, Chiba Hitachi Device Engineering Co., Ltd.

Claims (12)

[Claims] 1. A dynamic logic circuit 1 to which one or a plurality of input signals A and a control signal .phi.1 for determining a precharge period or a determination period are inputted, and a control signal .phi.1 of the dynamic logic circuit 1 to be inputted.
A first floating prevention circuit F1 having the drain side and the source side of the first MOS transistor as outputs, the drain side or the source side being connected to the output Z1 of the dynamic logic circuit 1, and the dynamic logic circuit 1 A second floating prevention circuit F2 having the output Z1 as an input, the drain side of the second MOS transistor as an output, and the output connected to the source side or the drain side of the first MOS transistor. A semiconductor logic circuit characterized by. 2. The semiconductor logic circuit according to claim 1, wherein the dynamic logic circuit 1 is a dynamic logic circuit including an n-type logic circuit having an input signal A as an input. 3. The dynamic logic circuit 1 includes a CMOS inverter N2 which receives an input signal A, and a control signal φ.
A CMOS inverter N3 having 1 as an input is connected, the source of an N-type MOS transistor MN5 constituting the CMOS inverter N3 is connected to the output of the CMOS inverter N2, and the output of the CMOS inverter N3 is of the dynamic logic circuit 1. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is an output. 4. The first floating prevention circuit F1
Is composed of a delay circuit DL which receives the control signal φ1 and a first p-type or n-type MOS transistor MP1 or MN1 whose gate receives an output φ2 of the delay circuit DL. n-type MOS transistor M
The drain of P1 or the source of MN1 is connected to the output Z1 of the dynamic logic circuit 1, and the source of MP1 or the drain of MN1 is the second floating prevention circuit F2.
The output terminal is connected to
1 to 3. The semiconductor logic circuit described in any one of 3 to 3. 5. The second floating prevention circuit F2
Is composed of a CMOS inverter N1 and a second p-type transistor MP2 whose gate receives the output Z2 of the CMOS inverter N1.
Is connected to the output Z1 of the dynamic logic circuit 1, and the drain of the second p-type transistor MP2 has the first
First p-type or n-type MO of the floating prevention circuit F1 of
5. The semiconductor logic circuit according to claim 1, wherein the source of the S-transistor MP1 or the drain of MN1 is connected, and the source of MP2 is connected to the first power supply VDD. 6. The semiconductor logic circuit according to claim 1, wherein the dynamic logic circuit 1 is a dynamic logic circuit including a p-type logic circuit having an input signal A as an input. 7. The dynamic logic circuit 1 comprises a CMOS inverter N4 which receives an input signal A, and a control signal φ.
Is composed of a CMOS inverter N5 which receives
2. The semiconductor logic circuit according to claim 1, wherein the source of the p-type transistor MP7 of the MOS inverter N5 is connected to the output of the inverter N4, and the output of the CMOS inverter N5 is the output of the dynamic logic circuit 1. 8. The first floating prevention circuit F1
Is composed of a delay circuit DL which receives the control signal φ1 and a first n-type or p-type MOS transistor MN1 or MP1 which receives the output φ2 of the delay circuit DL at its gate. p-type MOS transistor M
The drain of N1 or the source of MP1 is connected to the output terminal of the dynamic logic circuit 1, and the source of MN1 or the drain of MP1 is the second floating prevention circuit F2.
7. It is connected to the output terminal of
7. The semiconductor logic circuit according to any one of 1 to 7. 9. The second floating prevention circuit F2.
Is composed of a CMOS inverter N1 and a second n-type MOS transistor MN2 whose gate receives the output Z2 of the CMOS inverter N1, and the input of the CMOS inverter N1 is connected to the output Z1 of the dynamic logic circuit 1. The drain of the second n-type MOS transistor MN2 is connected to the source or drain of the first n- or p-type MOS transistor MN1 or MP1 of the first floating prevention circuit F1, and the source of MN2 is connected to the second power supply VSS. It is connected, It is characterized by the above-mentioned.
The semiconductor logic circuit according to any one of items 1 to 8. 10. A CMOS inverter N6 which receives one or a plurality of input signals A and a CMOS inverter N7 which receives a control signal φ1. The source of an n-type MOS transistor MN9 of the CMOS inverter N7 is the CMOS. A third floating prevention circuit F3 including a dynamic logic circuit 1 connected to the output of the inverter N6 and a p-type transistor MP10 whose gate receives the output φ2 of the delay circuit DL which receives the control signal φ1 as an input.
And the source of the p-type MOS transistor MP10 is connected to the output Z1 of the dynamic logic circuit 1,
A semiconductor logic circuit having a drain connected to the output of the CMOS inverter N6. 11. A CMOS inverter N8 which receives one or a plurality of input signals A, and a C which receives a control signal φ1.
The output of the delay circuit DL which is composed of a MOS inverter N9, and the source of the p-type MOS transistor MP12 of the CMOS inverter N9 is connected to the output of the CMOS inverter N8 and the delay signal DL which receives the control signal φ1. and a fourth floating prevention circuit F4 composed of an n-type MOS transistor MN13 which receives φ2 at its gate.
A semiconductor logic circuit, wherein the source of 3 is connected to the output Z1 of the dynamic logic circuit 1, and the drain thereof is connected to the output of the CMOS inverter N8. 12. A plurality of the semiconductor logic circuits are provided, and one delay circuit DL of the plurality of semiconductor logic circuits is commonly provided, and the plurality of delay circuits DL are provided with a control signal φ1 and an output φ2 of the shared delay circuit DL. 12. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is driven in common.